Abstract: A method of forming an improved interpoly oxide-nitride-oxide (ONO) stricture in stacked gate memory cells is provided. The top oxide layer of an interpoly ONO stack is formed using Low Pressure Chemical Vapor Deposition (LPCVD) of tetraethylorthosilicate (TEOS). As a result of the relatively low processing temperatures necessary for this step, degradation of the tunnel oxide and memory cell performance associated with high thermal-budget oxide growth processes is greatly reduced. Steam densification of the TEOS layer produces a robust top oxide for the ONO dielectric, and thus, greatly reduces erosion of the top layer TEOS during subsequent processing steps (i.e., in the context of a memory array embedded in CMOS core technology).

Abstract: In one implementation, A method of forming semiconductive material active area having a proximity gettering region received therein includes providing a substrate comprising bulk semiconductive material. A proximity gettering region is formed within the bulk semiconductive material within a desired active area by ion implanting at least one impurity into the bulk semiconductive material. After forming the proximity gettering region, thickness of the bulk semiconductive material is increased in a blanket manner at least within the desired active area. In one implementation, a method of processing a monocrystalline silicon substrate includes forming a proximity gettering region within monocrystalline silicon of a monocrystalline silicon substrate. After forming the proximity gettering region, epitaxial monocrystalline silicon is formed on the substrate monocrystalline silicon to blanketly increase its thickness at least over the proximity gettering region.

Abstract: A solid state image sensor according to the present invention includes a p-type conductivity type well formed in a surface of an n-type conductivity type semiconductor substrate in which a photoelectric conversion region is defined. A photoelectric conversion device (i.e., photodiode) is formed of a PD-N region and a PD-P region in a surface of the p-type conductivity well in the photoelectric conversion region, for converting a signal of light to an electrical signal. A vertical charge transfer region is formed in a surface of the p-type conductivity well in which the photodiode is not formed, and a channel stop layer is formed in a surface of the p-type conductivity well around the PD-N region except for a region between one side of the photodiode and the vertical charge transfer region. A gate insulating film is formed on the semiconductor substrate except for the photodiode, and a transfer gate is formed on the gate insulating film.

Abstract: Cubic or metastable cubic refractory metal carbides act as barrier layers to isolate, adhere, and passivate copper in semiconductor fabrication. One or more barrier layers of the metal carbide are deposited in conjunction with copper metallizations to form a multilayer characterized by a cubic crystal structure with a strong (100) texture. Suitable barrier layer materials include refractory transition metal carbides such as vanadium carbide (VC), niobium carbide (NbC), tantalum carbide (TaC), chromium carbide (Cr3C2), tungsten carbide (WC), and molybdenum carbide (MoC).

Abstract: A method of fabricating a copper capping layer. A silicon rich nitride layer is formed on an exposed copper layer. Since the silicon rich nitride layer has more dangling bonds inside, the silicon in the silicon rich nitride layer easily reacts with the copper and a copper silicide layer is formed between the copper and the silicon rich nitride layer. Therefore, adhesion of the copper and the silicon rich nitride layer can be improved.

Abstract: A circuit assembly is provided with a lower die and an upper die offset and stacked on the lower die. A supporting material, such as a dielectric molding compound or epoxy resin, is dispensed along the side surfaces of the lower die under the overhanging parts of the upper die to provide support for the upper die, thereby preventing cracking of the upper die during wire bonding.

Abstract: The present invention relates to the impurity ion segregation precluding layer, the fabrication method thereof, the isolation structure for the semiconductor device using the segregation precluding layer and the fabrication method thereof, which are provided to prevent impurity ions from segregating into a device isolation region in a semiconductor substrate and eventually restrain decrease in a threshold voltage due to the segregation of impurity ion, particularly, boron ions in the semiconductor substrate. The isolation structure of the semiconductor device is fabricated by forming a trench in a portion of the semiconductor substrate; placing the semiconductor substrate into a high-temperature furnace; annealing the semiconductor substrate flowing a nitride gas at about 20 l/min into the furnace; and filling an insulator in the trench.

Abstract: A capacitor processing method includes forming a capacitor comprising first and second electrodes having a capacitor dielectric region therebetween. The first electrode interfaces with the capacitor dielectric region at a first interface. The second electrode interfaces with the capacitor dielectric region at a second interface. The capacitor dielectric region has a plurality of oxygen vacancies therein. After forming the capacitor, an electric field is applied to the capacitor dielectric region to cause oxygen vacancies to migrate towards one of the first and second interfaces. Oxygen atoms are preferably provided at the one interface effective to fill at least a portion of the oxygen vacancies in the capacitor dielectric region. Preferably at least a portion of the oxygen vacancies in the high k capacitor dielectric region are filled from oxide material comprising the first or second electrode most proximate the one interface.

Abstract: Die bonding equipment for fine pitch ball grid array package includes: a semiconductor chip pickup stage for inspecting a status of a loaded semiconductor chip and a corresponding position thereof; an alignment stage on which the semiconductor chip fixed on a mount head is aligned; a chip transfer unit for transferring the semiconductor chip from the semiconductor chip pickup stage to the alignment stage; a guide rail for guiding a mount tape frame; a status inspecting unit disposed at a selected position over the guide rail, for inspecting a status and a position of the land pattern on the mount tape frame; and a bonding unit for bonding the land pattern to the semiconductor chip which is mounted on the mount head. The equipment only bonds semiconductor chips (good or defective) to lands patterns having the same status (good or defective).

Abstract: Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In one implementation, openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place. In separate steps, the substrate is doped with impurities, and material of the substrate is etched through the mask openings. In another implementation, two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines. Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line.

Abstract: The present method of forming a silicon oxide layer comprises providing two frequency excitation plasma CVD device which comprises a high frequency electrode, a susceptor electrode, and two matching box for impedance matching between the electrodes and a power supply, wherein one side electrode constituting a tuning condenser of a matching box toward the high frequency electrode is the high frequency electrode; placing a substrate on the susceptor electrode; applying high frequency electric power on the high frequency electrode and the susceptor electrode respectively; and forming a silicon oxide layer on the substrate by generating plasma with using a reaction gas of which main reaction gas is a mixing gas of monosilane and nitrous oxide.

Abstract: A method of manufacturing a semiconductor device in which a cobalt silicide layer is formed on a semiconductor substrate. In the method, the semiconductor substrate is prepared, and cobalt is deposited on the semiconductor substrate by sputtering while heating the semiconductor substrate at a temperature approximately equal to 200 degrees Celsius. Thereafter, cobalt is deposited on the semiconductor substrate by sputtering while heating the semiconductor substrate at a temperature between 300 degrees Celsius and 400 degrees Celsius without exposing the semiconductor substrate to the atmosphere. Preferably, the semiconductor substrate is thereafter rapid thermal annealed at a temperature equal to or higher than 500 degrees Celsius in nitrogen atmosphere for a predetermined time. Further, at least a part of cobalt portion or cobalt oxide portion on the semiconductor substrate is removed by wet etching.

Abstract: The present invention provides for a method and an apparatus for performing automatic control adjustments during photolithography processes. A plurality of semiconductor devices are processed. Optical data analysis is performed upon at least one of the processed semiconductor device. Control adjustments to the processing is performed in response to the optical data analysis.

Abstract: A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed is arranged to have a gate electrode which is formed on the surface of a silicon substrate through an insulating film. An elevated source film and an elevated drain film each having at least a surface portion constituted by a metal silicide film, being conductive and elevated over the surface of the silicon substrate are formed on a source region and a drain region on the surface of the silicon substrate. Thus, a MOS transistor having a structure in which the surfaces of the source region and the drain region are elevated over the surface of the silicon substrate is formed. A first gate-side-wall insulating film is formed on the side wall of the gate electrode of the MOS transistor and having a bottom surface formed apart from the surface of the silicon substrate.

Abstract: The present invention relates generally to a new structure and method for chip burn-in and/or testing. More particularly, the invention encompasses a baseplate that is secured to a delicate chip and a method for such an invention is also disclosed. The inventive baseplate provides an added strength to a complex chip while it is being tested and/or burned-in, and then during normal use the baseplate of this invention is an integrated component of the chip.

Abstract: In a method of manufacturing bump electrodes, a solder paste material is filled in concave parts provided on one surface of a jig for forming bumps, and the solder paste material is melted under the condition in that the concave parts of the jig for forming bumps face electrode pads provided on one surface of a substrate (a semiconductor chip or a circuit board), to form bump electrodes on the electrode pads of the substrate, whereby the size of the bump electrodes formed on electrode pads can be uniform. Furthermore, a short circuit among the electrode pads of the substrate (a semiconductor chip or a circuit board) can be prevented. Furthermore, the yield in a production process of a semiconductor device having bump electrodes can be increased.

Abstract: A dual-gate SOI transistor that has the back gate self-aligned to the front gate is formed on an SOI substrate by forming a conventional gate stack having an etch resistant layer on the top; growing epitaxial silicon on the upper surface of the silicon device layer, which leaves apertures on both sides of the gate stack; filling the apertures with etch resistant spacers; defining an etch window bracketing the gate stack and etching alignment trenches down to the bulk silicon. A shallow layer of etch resistant aligning material is deposited on the bottom of the alignment trenches, after which the conventional back end processing as followed of deposition of a supporting layer that supports the layers of the circuit during later processing. The bulk silicon is removed and the back side is patterned to expose the buried oxide below the transistors; an oxide etch leaves a self-aligned backside aperture below the transistors, defined by the etch resistant aligning material.

Abstract: A method of forming the shallow trench isolation by introducing a silicon nitride etching back step and a nitrogen treatment after the step of forming the trench is disclosed. The exposed pad oxide layer located on the upper portion of the trench is transferred into silicon oxynitride layer. Therefore, the formation of the bird's break and electric influence of the device are avoided. Accordingly, the scale down requirement of the future device is also satisfied.

Abstract: A gate wire including a plurality of gate lines and gate electrodes in the display area, and gate pads in the peripheral area is formed on a substrate having a display area and a peripheral area. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor layer are sequentially deposited, and the conductor layer and the ohmic contact are patterned to form a data wire including a plurality of data lines, a source electrode and a drain electrode of the display area and data pads of the peripheral area, and an ohmic contact layer pattern thereunder. A passivation layer is deposited and a positive photoresist layer is coated thereon. The photoresist layer is exposed to light through one or more masks having different transmittance between the display area and the peripheral area. The photoresist layer is developed to form a photoresist pattern having the thickness that varies depending on the position.

Abstract: In the invention, a photoresist layer is first spread on a semiconductor structure, and then using a photomask with a specially designed pattern exposes the photoresist layer. Next, the photoresist layer is developed to form a patterned photoresist layer. Thereafter, using the patterned photoresist layer as a mask, a trench is formed in the semiconductor structure by selective etching. The pattern of the photomask according to the invention is formed as in the following steps. At first, a first pattern extending in a first direction and having a first side and a second side that is opposite to the first side is formed. Next, a second pattern extending in a second direction that is perpendicular to the first direction is formed in such a way that an end of the second pattern is connected with the first side of the first pattern. Thereafter, a concave edge is formed on the second side to substantially face the second pattern.