Abstract: Provided are an organic light-emitting display panel and an organic light-emitting display apparatus. The organic light-emitting display panel includes an array base substrate including a plurality of driving elements, and includes a plurality of organic light-emitting devices. Each of the plurality of organic light-emitting devices is corresponding to a respective one of the plurality of driving elements, and the each of the plurality of organic light-emitting devices includes an anode and a cathode, a cathode, an organic luminous layer, an electron transport layer, and a transition layer. The organic luminous layer is disposed between the anode and the cathode, the electron transport layer is disposed between the luminous layer and the cathode, and the transition layer is disposed between the cathode and the electron transport layer, and the transition layer includes an organic material.

Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of forming a target layer surrounding a vertical nanostructure. In one aspect, a method includes providing a substrate having a substrate surface. The method additionally includes forming a vertical nanostructure extending outwardly from a substrate surface. The vertical nanostructure has a sidewall surface, where the sidewall surface has an upper portion and a lower portion. The method additionally includes forming a target layer at least along the sidewall surface of the vertical nanostructure and on the substrate surface. The method additionally includes forming a protection layer covering the target layer and removing an upper portion of the protection layer, thereby exposing the target layer along the upper portion of the sidewall surface of the vertical nanostructure.

Abstract: This patent describes embodiments of systems, apparatus and methods to provide improved control and coordination of a multiplicity of electric distribution grid-connected, energy storage units deployed over a geographically-dispersed area.

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

Abstract: Provided is a nanosheet semiconductor device. In embodiments of the invention, the nanosheet semiconductor device includes a channel nanosheet formed over a substrate. The nanosheet semiconductor device includes a buffer layer formed between the substrate and the channel nanosheet. The buffer layer has a lower conductivity than the channel nanosheet.

Abstract: A display device includes a base, a light emitting device on a first surface of the base, and a plate-like inorganic layer on a second surface of the base, the plate-like inorganic layer including a first plate-like inorganic particle with a first size and a second plate-like inorganic particle with a second size different from the first size.

Abstract: A fan-out semiconductor package includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, an encapsulant encapsulating the semiconductor chip, and an electromagnetic wave shielding layer disposed on the semiconductor chip and including a plurality of degassing holes. The electromagnetic wave shielding layer includes a first region and a second region in which densities of the degassing holes are different from each other, the first region having a density of the degassing holes higher than a density of the degassing holes in the second region.

Abstract: Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. A dielectric spacer is formed adjacent to a vertical sidewall of the gate structure. A semiconductor layer is formed on the top surface of the semiconductor body. The semiconductor layer is arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located in a space between the semiconductor layer and the vertical sidewall of the gate structure. A second section of the dielectric spacer that is located above a top surface of the semiconductor layer is removed. An air-gap spacer is formed in a space from which the second section of the dielectric spacer is removed.

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dual thickness fuse structures and methods of manufacture. The structure includes a continuous wiring structure on a single wiring level and composed of conductive material having a fuse portion and a thicker wiring structure.

Abstract: Apparatus and methods for powering micron-scale implantable and injectable integrated circuit (IC) chips for in-vivo sensing and acquisition of various physiological signals are provided. The disclosed subject matter includes the integration of piezoelectric transducers, such as polyvinylidene fluoride (PVDF) or lead zirconate titanate (PZT), onto implantable and injectable IC chips for power transfer and data transmission using ultrasound waves generated from commercial ultrasound imaging equipment.

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin.

Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, each comprising a first part, on the first semiconductor region, wherein the second semiconductor regions are spaced apart in a first direction, a third semiconductor region of the first conductivity type on each of the second semiconductor regions, an insulation portion between two of the second semiconductor regions, the insulation portion having one side in contact with one of the first parts and the other side in contact with one of the third semiconductor regions, a first electrode within the insulation portion, a gate electrode spaced apart from the first electrode and within the insulation portion, and a second electrode on the third semiconductor region and electrically connected to the first electrode and the third semiconductor region.

Abstract: A method for forming packaged electronic devices includes providing a substrate having pads connected by conductive pad linking portions and semiconductor devices attached to the pads in different orientations. A second substrate is provided having conductive connectors each with a plate portion, a conductive member extending from a side segment of the plate portion, and a connective portion extending from the conductive member distal to the plate portion. The second substrate further has conductive linking portions physically connecting adjoining plate portions together. Each plate portion is attached to one of the semiconductor devices to provide a subassembly. The conductive linking portions are configured to maintain the adjoining plate portions in substantial alignment with the semiconductor devices and to maintain the connective portions is a desired alignment during the plate portion attachment step.

Abstract: A semiconductor device is provided comprising an active portion and a terminating structure. The semiconductor device is provided comprising the active portion provided in the semiconductor substrate and a terminating structure provided at a termination of the front surface side of the semiconductor substrate and that mitigates an electric field of the termination. In the electric field distribution of the front surface side of the terminating structure, during rated voltage application, an electric field at the end portion of the active portion side may be smaller than a maximum value of an electric field distribution of the front surface side. In addition, the electric field distribution of the terminating structure may have a maximum peak of the electric field on the edge side opposite to the active portion with respect to a center of the terminating structure.

Abstract: Embodiments of three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. A method for forming a 3D memory device includes the following operations. An initial channel hole in a structure is formed. The structure includes a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers can be formed on a sidewall of the initial channel hole to form a channel hole. The channel hole with a channel-forming structure can be formed to form a semiconductor channel. The channel-forming structure can include a memory layer extending along a vertical direction. The plurality of second layers can then be replaced with a plurality of gate electrodes.

Abstract: A light emitting device having a light-emitting element, a covering resin covering the light-emitting element, a wavelength converting material contained in the covering resin, and a light diffusing agent contained in the covering resin is provided. The light diffusing agent contains glass particles. A first refractive index n1 of the covering resin at a peak wavelength of a light emitted by the light-emitting element and at 25° C. is in a range of 1.48 to 1.60, a second refractive index n2 of the covering resin at the peak wavelength and at 100° C. is at least 0.0075 lower than the first refractive index n1, and a third refractive index n3 of the light diffusing agent at the peak wavelength and at 25° C. is higher than the first refractive index n1.

Abstract: A method is provided and includes the following steps. A first wafer is coupled to a first support of a bonding tool and a second wafer is coupled to a second support of the bonding tool. The second wafer is bonded to the first wafer with the first wafer coupled to the first support. Whether a bubble is between the bonded first and second wafers in the bonding tool is detected.

Abstract: A display device includes: pixels; gate lines for connecting to the pixels; a first gate driving block for connecting to first and second gate lines that are adjacent to each other; and a second gate driving block for connecting to the first gate line and the second gate line, wherein the first gate driving block includes: a first gate signal generating portion; a first transistor connected between a first output terminal of the first gate signal generating portion and the first gate line; and a second transistor connected between the first output terminal and the second gate line, wherein the second gate driving block includes: a second gate signal generating portion; a third transistor connected between a second output terminal of the second gate signal generating portion and the first gate line; and a fourth transistor connected between the second output terminal and the second gate line.

Abstract: A sealing structure with a surface of a base material with a through-hole, an underlying metal film, and a sealing member bonded to the underlying metal film to seal the through-hole. The sealing member includes a compressed product of a metal powder including gold having a purity of 99.9% by mass or more and a lid-like metal film including a bulk-like metal including gold and having a thickness of not less than 0.01 ?m and not more than 5 ?m. The sealing material includes an outer periphery-side densified region in contact with an underlying metal film and a center-side porous region in contact with the through-hole. The shape of pores in the densified region is specified, and the horizontal length (l) of a pore in the radial direction at any cross-section of the densified region and the width (W) of the densified region satisfy the relationship of l?0.1W.