Patents Examined by Charles D. Garber
  • Patent number: 11322489
    Abstract: A tiled display device is provided. The tiled display device includes a first substrate, a second substrate and a light-emitting unit. The first substrate includes a first main substrate and a first flexible substrate. The first flexible substrate is disposed on the first main substrate. The second substrate is disposed adjacent to the first substrate. The light-emitting unit is disposed on the first flexible substrate. In addition, a portion of the light-emitting unit protrudes from an edge of the first main substrate.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 3, 2022
    Assignee: INNOLUX CORPORATION
    Inventors: Hao-Jung Huang, Chao-Chin Sung
  • Patent number: 11316063
    Abstract: According to various embodiments, there is provided a diode device including a semiconductor substrate of a first conductivity type, a first semiconductor region formed within the semiconductor substrate, an epitaxial region of the first conductivity type, and a second semiconductor region of a second conductivity type different from the first conductivity type. The first semiconductor region includes a chalcogen. The epitaxial region is formed over the first semiconductor region. The second semiconductor region is formed over the epitaxial region.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: April 26, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sandipta Roy, Khee Yong Lim, Lanxiang Wang, Kiok Boone Elgin Quek, Jing Hua Michelle Tng
  • Patent number: 11315990
    Abstract: The present application discloses a display panel comprising a substrate, a transistor layer on the substrate, and a pixel-defining layer on a side of the transistor layer distal to the substrate to divide the display panel into a plurality of subpixel regions. At least one subpixel region includes a display sub-region and a light-sensitive sub-region. The display panel further includes a plurality of organic light-emitting diodes formed on the transistor layer respectively on the plurality of subpixel regions. Additionally, the display panel includes a plurality of pixel circuits formed in the transistor layer respectively on the plurality of subpixel regions. Each pixel circuit includes at least a display-driving sub-circuit coupled to one organic light-emitting diode. At least one pixel circuit in the at least one subpixel region includes a light-sensing sub-circuit formed on the light-sensitive sub-region and coupled to the display-driving sub-circuit formed on the display sub-region.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: April 26, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Libin Liu, Xiaowei Xu
  • Patent number: 11302597
    Abstract: A semiconductor device is provided with a heat dissipating face side skirt portion, which is a frame-form projection, on a heat dissipating face of a lead frame. Because of this, creepage distance increases with a small increase in an amount of resin, and insulating properties improve. Also, the heat dissipating face side skirt portion is molded via two transfer molding steps, wettability of the second molding resin with respect to a first molding resin and the lead frame increases, and adhesion improves. Furthermore, an end face of an inner lead is exposed in an element sealing portion on a mounting face side, and covered with a second thin molded portion molded using the second molding resin, whereby heat generated in a semiconductor element can efficiently be caused to escape from faces of both a first thin molded portion and the second thin molded portion, because of which heat dissipation improves.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: April 12, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takanobu Kajihara, Katsuhiko Omae, Takashi Nagao, Masayuki Funakoshi, Norio Emi, Atsuki Fujita, Yuki Okabe
  • Patent number: 11217460
    Abstract: A method of assembling a flip chip IC package includes applying core underfill material to a surface of a package substrate in a pattern including an area corresponding to a core region of an IC die thereon that is to be attached, that excludes of an area corresponding to corners of the IC die. The IC die is bonded to the package substrate by pushing the IC die with a sufficient force for the core underfill material is displaced laterally by the bumps so that the bumps contact the land pads. After the pushing the corners of the IC die are not on the core underfill. Edge underfilling includes dispensing a second underfill material that is curable liquid to fill an area under the corners of the IC die. The second underfill material is cured resulting in it having a higher fracture strength as compared to the core underfill.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: January 4, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Makarand Ramkrishna Kulkarni, Tae Kim
  • Patent number: 11215861
    Abstract: The present disclosure provides a display panel and a method for improving display quality of the display panel. The display panel includes a temperature control apparatus. Specifically, the temperature control apparatus includes a temperature sensor in a non-display area of the display panel for detecting a temperature of the display panel, a change-temperature component in a display area of the display panel for performing a change-temperature treatment on the display panel, and a controller electrically connected to the temperature sensor and the change-temperature component for controlling the change-temperature component to operate according to the temperature of the display panel.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: January 4, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Lijun Zhao
  • Patent number: 11211292
    Abstract: Some embodiments include an assembly having a CMOS tier. The CMOS tier includes a PMOS deck and an NMOS deck, with the decks being vertically offset relative to one another. The PMOS deck has p-channel transistors which are substantially identical to one another, and the NMOS deck has n-channel transistors which are substantially identical to one another. An insulative region is between the PMOS deck and the NMOS deck. The CMOS tier has one or more circuit components which include one or more of the n-channel transistors coupled with one or more of the p-channel transistors through one or more conductive interconnects extending through the insulative region. Some embodiments include methods of forming assemblies to comprise one or more CMOS tiers.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Kurt D. Beigel
  • Patent number: 11183656
    Abstract: The present disclosure provides an organic electroluminescent device, a display substrate including the organic electroluminescent device, and a display apparatus including the display substrate. The organic electroluminescent device includes an anode, a cathode, and a light emitting layer between the anode and the cathode, wherein a hole transport layer is provided between the anode and the light emitting layer and includes a hole transport material and a P-type doping material, electrons of the highest occupied molecular orbit of the P-type doping material are excitable to the lowest unoccupied molecular orbit of the P-type doping material under the excitation of light to cause an electron transfer reaction from the highest occupied molecular orbit of the hole transport material to the highest occupied molecular orbit of the P-type doping material.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: November 23, 2021
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Tiancheng Yu
  • Patent number: 11183414
    Abstract: In semiconductor packaging technologies, a secondary packaging method of a TSV chip and a secondary package of a TSV chip are provided. The TSV chip has a forward surface and a counter surface that are opposite to each other, a BGA solder ball is disposed on the counter surface, and the secondary packaging method includes: placing at least one TSV chip on a base on which a stress relief film layer is laid; cladding the TSV chip via a softened molding compound; removing the base after the molding compound is cured, to obtain a secondary package of the TSV chip; and processing a surface of the secondary package to expose the BGA solder ball.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: November 23, 2021
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventors: Baoquan Wu, Wei Long, Yuping Liu
  • Patent number: 11165040
    Abstract: The present disclosure relates to package structure, packaging method and display device. A package structure comprises: a first substrate and a second substrate disposed opposite to each other, a peripheral portion of at least one of the first substrate and the second substrate being provided with a sealing hole; a first sealing structure disposed between the first substrate and the second substrate and located at a peripheral region of the first substrate; and a second sealing structure disposed in the sealing hole, wherein the first sealing structure is bonded to the second sealing structure.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: November 2, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventor: Zhiliang Jiang
  • Patent number: 11152324
    Abstract: A method of making a plurality of integrated circuit (“IC”) packages includes picking up a plurality of physically unconnected IC components; and simultaneously placing each of the physically unconnected IC components on corresponding portions of an unsingulated IC package strip that includes a sheet of integrally connected leadframes.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: October 19, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Roxanna Bauzon Samson, Ruby Ann Maya Merto, Lorraine Rivera Duldulao, Jason Binay-an Colte
  • Patent number: 11145544
    Abstract: The present disclosure provides an integrated circuit with an interconnect structure and a method for forming the integrated circuit. In one embodiment, a method of the present disclosure includes receiving a workpiece that includes a first recess in a dielectric layer over the workpiece, depositing a contact fill in the first recess and over the dielectric layer to form a contact feature, planarizing a top surface of the workpiece to remove the contact fill over the dielectric layer, depositing an interlayer dielectric layer over the planarized top surface of the workpiece, forming a second recess in the interlayer dielectric layer to expose the contact fill in the dielectric layer, recessing the contact fill by soaking the workpiece in a room temperature ionic liquid, and depositing a conductive layer over the recessed contact fill. The material forming the contact fill is soluble in the room temperature ionic liquid.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Andrew Joseph Kelly
  • Patent number: 11145794
    Abstract: Light Emitting Devices (LEDs) are fabricated on a wafer substrate with one or more thick metal layers that provide structural support to each LED. The streets, or lanes, between individual LEDs do not include this metal, and the wafer can be easily sliced/diced into singulated self-supporting LEDs. Because these devices are self-supporting, a separate support submount is not required. Before singulation, further processes may be applied at the wafer-level; after singulation, these self-supporting LEDs may be picked and placed upon an intermediate substrate for further processing as required. In an embodiment of this invention, protective optical domes are formed over the light emitting devices at the wafer-level or while the light emitting devices are situated on the intermediate substrate.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: October 12, 2021
    Assignee: Lumileds LLC
    Inventors: Salman Akram, Jyoti Kiron Bhardwaj
  • Patent number: 11139219
    Abstract: A bypass thyristor device includes a semiconductor device providing a thyristor with a cathode electrode on a cathode side, a gate electrode on the cathode side surrounded by the cathode electrode and an anode electrode on an anode side; an electrically conducting cover element arranged on the cathode side and in electrical contact with the cathode electrode on a contact side; and a gate contact element electrically connected to the gate electrode and arranged in a gate contact opening in the contact side of the cover element; wherein the cover element has a gas expansion volume in the contact side facing the cathode side, which gas expansion volume is interconnected with the gate contact opening for gas exchange.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: October 5, 2021
    Assignee: ABB Schweiz AG
    Inventors: Tobias Wikström, Remo Baumann, Sascha Populoh, Bjoern Oedegard
  • Patent number: 11139267
    Abstract: Packaging structure and method of forming a packaging structure are provided. A substrate is provided, and an adhesive layer is formed on the substrate. An improvement layer is formed on the adhesive layer. The improvement layer contains openings exposing surface portions of the adhesive layer at bottoms of the openings. A plurality of chips is provided and includes functional surfaces. The plurality of chips is mounted on the substrate such that the functional surfaces are bonded to the adhesive layer at the bottoms of the openings.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: October 5, 2021
    Assignee: TONGFU MICROELECTRONICS CO., LTD.
    Inventor: Lei Shi
  • Patent number: 11139282
    Abstract: A semiconductor package structure includes a first package, a second package over the first package, a plurality of connectors between the first package and the second package and a plurality of baffle structures between the first package and the second package. The second package includes a bonding region and a periphery region surrounding the bonding region. The connectors are disposed in the bonding region to provide electrical connections between the first package and the second package. The baffle structures are disposed in the periphery region and are separated from each other.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuo-Chiang Ting, Tu-Hao Yu, Ting-Yu Yeh, Chia-Hao Hsu, Weiming Chris Chen, Wan-Yu Lee, Yu-Jie Su
  • Patent number: 11133399
    Abstract: A semiconductor device includes a semiconductor layer which has a first device formation region and a second device formation region, a first HEMT which is formed in the first device formation region and has a first two-dimensional electron gas region as a channel, a second HEMT which is formed in the second device formation region and has a second two-dimensional electron gas region as a channel, and a region separation structure which is formed in the semiconductor layer and defines the first device formation region and the second device formation region.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: September 28, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Kenichi Yoshimochi
  • Patent number: 11127692
    Abstract: A semiconductor package includes a semiconductor chip, and a connection structure disposed on at least one side of the semiconductor chip, and including an insulating layer and a redistribution layer electrically connected to the semiconductor chip, wherein the redistribution layer includes a plurality of conductive patterns, and at least two of the plurality of conductive patterns have different degrees of surface roughness, and a conductive pattern having a higher surface roughness has a width wider than a width of a conductive pattern having a lower surface roughness.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: September 21, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gun Lee, Jun Gul Hwang, Ji Eun Woo, Sung Keun Park
  • Patent number: 11121228
    Abstract: Disclosed is a manufacturing method of a thin film transistor, comprising: sequentially preparing a gate, a gate insulation layer and an active layer on the substrate; preparing an etching stopper layer on the active layer; depositing an ohmic contact layer film on the etching stopper layer and the active layer, and depositing a source drain conductive film on the ohmic contact layer film; processing the source drain conductive film to form a source and a drain, which are patterned, and processing the ohmic contact layer film by a dry etching process to form an ohmic contact layer, which is patterned; removing the etching stopper layer after preparing the ohmic contact layer. Since the etching stopper layer is disposed above the channel of the transistor before preparing the ohmic contact layer, the damage to the active layer by dry etching can be effectively avoided to improve the performance of the transistor.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: September 14, 2021
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Huafei Xie
  • Patent number: 11101311
    Abstract: Photodetectors and fabrication methods thereof and imaging sensors are provided. An exemplary photodetector includes a first substrate formed with pixel circuits and common electrode connection members and first wiring boards electrically connected to the corresponding pixel circuits; and a second substrate formed with pixel units and isolation wall members isolating pixel units. Each isolation wall member includes a conductive member and a sidewall; second wiring boards are formed on a front surface of the second substrate; the second wiring boards are electrically connected to first terminals of the pixel units; a transparent electrode layer is formed on a back surface of the second substrate; and a second terminal of each pixel unit is electrically connected to the transparent electrode layer. The second wiring boards are bonded and electrically connected to the first wiring boards and the transparent electrode layer is electrically connected to the common electrode connection members.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 24, 2021
    Assignee: Ningbo Semiconductor International Corporation
    Inventor: Hailong Luo