Patents Examined by Charles D. Garber
  • Patent number: 10411092
    Abstract: A method comprises providing a cavity structure on the substrate comprising a first growth channel extending in a first direction, a second growth channel extending in a second direction, wherein the second direction is different from the first direction and the second channel is connected to the first channel at a channel junction, a first seed surface in the first channel, at least one opening for supplying precursor materials to the cavity structure, selectively growing from the first seed surface a first semiconductor structure substantially only in the first direction and in the first channel, thereby forming a second seed surface for a second semiconductor structure at the channel junction, growing in the second channel the second semiconductor structure in the second direction from the second seed surface, thereby forming the semiconductor junction comprising the first and the second semiconductor structure.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: September 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mattias B. Borg, Kirsten E. Moselund, Heike E. Riel, Heinz Schmid
  • Patent number: 10411044
    Abstract: The present disclosure relates to a display substrate comprising a substrate; a data line disposed over the substrate; a first insulating layer disposed on the data line; a second insulating layer disposed on the first insulating layer; a first transparent electrode disposed on the second insulating layer. The present disclosure further relates to a manufacturing method of a display substrate and a display device.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: September 10, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhenfei Cai, Wenjie Wang, Jing Hao
  • Patent number: 10410925
    Abstract: Some embodiments include an assembly having a CMOS tier. The CMOS tier includes a PMOS deck and an NMOS deck, with the decks being vertically offset relative to one another. The PMOS deck has p-channel transistors which are substantially identical to one another, and the NMOS deck has n-channel transistors which are substantially identical to one another. An insulative region is between the PMOS deck and the NMOS deck. The CMOS tier has one or more circuit components which include one or more of the n-channel transistors coupled with one or more of the p-channel transistors through one or more conductive interconnects extending through the insulative region. Some embodiments include methods of forming assemblies to comprise one or more CMOS tiers.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Kurt D. Beigel
  • Patent number: 10403497
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes, in order: polishing a silicon carbide semiconductor base body from a second main surface side thus forming unevenness on a second main surface; forming a thin metal film made of metal capable of forming a metal carbide on the second main surface of the silicon carbide semiconductor base body; irradiating a laser beam which falls within a visible region or within an infrared region to the thin metal film so as to heat the thin metal film thus forming a metal carbide on a boundary face between the silicon carbide semiconductor base body and the thin metal film; etching a metal containing byproduct layer possibly formed on a surface side of the metal carbide by a non-oxidizing chemical solution thus exposing a surface of the metal carbide; and forming a cathode electrode on the metal carbide.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: September 3, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Yusuke Fukuda, Yoshiyuki Watanabe, Shunichi Nakamura
  • Patent number: 10396034
    Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug. An interval between the first contact plug and the second contact plug may be about 10 nm or less.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Kong Siew, Wei Hsiung Tseng, Changhwa Kim
  • Patent number: 10396072
    Abstract: A semiconductor device is provided having a first region and a second region surrounding the first region includes a first electrode, a second electrode, a first semiconductor layer of a first conductivity type between the first electrode and the second electrode, a second semiconductor layer of the first conductivity type located over the first semiconductor layer, a third semiconductor layer of the second conductivity type on the second semiconductor layer in the first region, a fourth semiconductor layer of the first conductivity type between the third semiconductor layer and the second semiconductor layer, a fifth semiconductor layer of the second conductivity type on the second semiconductor layer in the second region, and a sixth semiconductor layer of the first conductivity type located between the fifth semiconductor layer and the second semiconductor layer, wherein the width of the fourth semiconductor layer is less than the width of the sixth semiconductor layer.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 27, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONICS DEVICES & STORAGE CORPORATION
    Inventor: Yoichi Hori
  • Patent number: 10396017
    Abstract: A lead frame includes a frame part, a lead extending inward from the frame part and having a front surface and a back surface, and an external connection terminal formed at a part of the lead in an extension direction and protruding from the back surface of the lead. The lead includes a pentagonal shape in a cross-section where the front surface of the lead faces upward, the pentagonal shape having a quadrangular main body part and a triangular protrusion protruding from a lower surface of the main body part. A width of a lower end of the main body part is smaller than a width of an upper end of the main body part.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: August 27, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Konosuke Kobayashi, Koji Ato, Makoto Takeuchi
  • Patent number: 10391823
    Abstract: A pressure deviation between a setpoint tire pressure and an actual tire pressure for a tire of a vehicle is determined by the following steps: Ascertaining a wheel load for the tire. Ascertaining a dynamic tire radius of the tire. Determining the pressure deviation as a function of the wheel load and the dynamic tire radius.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: August 27, 2019
    Assignee: VOLKSWAGEN AG
    Inventors: Simon Steinmeyer, Marc-Michael Meinecke, Pär Degerman, Carsten Deeg
  • Patent number: 10395919
    Abstract: According to the invention a method for filling one or more gaps created during manufacturing of a feature on a substrate is provided by providing the substrate in a reaction chamber and providing a deposition method. The deposition method comprises; providing an anisotropic plasma to bombard a bottom area of a surface of the one or more gaps with ions thereby creating adsorption sites at the bottom area; introducing a first reactant to the substrate; and, allowing the first reactant to react with the adsorption sites at the bottom area of the surface to fill the one or more gaps from the bottom area upwards.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: August 27, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Zaitsu Masaru, Atsuki Fukazawa
  • Patent number: 10395967
    Abstract: Provided is a method of manufacturing a semiconductor device with improved manufacturing efficiency for the semiconductor device. The method of manufacturing a semiconductor device includes the steps of: (a) forming a circuit at a front surface side of a wafer (semiconductor wafer) having the front surface and a back surface opposite to the front surface; (b) grinding the back surface of the wafer that has a center part (first part) and a peripheral edge part (second part) surrounding a periphery of the center part in such a manner that the center part is thinner than the peripheral edge part; (c) attaching an upper surface (bonding surface) of a holding tape to the front surface of the wafer; and (d) separating the center part from the peripheral edge part by cutting a part of the center part with a blade (rotary blade) while the wafer is held by the first tape.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: August 27, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takamitsu Yoshihara, Takahiro Kainuma, Hiroi Oka
  • Patent number: 10388661
    Abstract: Provided herein may be a semiconductor device and a method of manufacturing the same. The method of manufacturing the semiconductor device may include forming a tunnel insulating layer in a channel hole passing through a preliminary stack structure in which interlayer insulating layers and material layers are alternately stacked. The method may include forming recess areas by removing the material layers exposed through a slit passing through the preliminary stack structure. The method may include forming a data storage layer in the recess areas through the slit. The thickness of the data storage layer may be formed regardless of a size of the channel hole.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventors: Min Woo Park, Kyo Yeon Cho
  • Patent number: 10387500
    Abstract: A semiconductor device includes a fin, first to fourth gate electrodes, first and second storage devices, first and second search terminals, and first and second dummy search terminals. The fin extend in a first direction. The gate electrodes intersecting the fin. The storage devices are connected with the gate electrodes. The first search terminal is connected with the second gate electrode and is spaced from the fin by a first distance. The second search terminal is connected with the third gate electrode and is spaced from the fin by a second distance different from the first distance. The first dummy search terminal is connected with the second gate electrode and is spaced from the fin by the second distance. The second dummy search terminal is connected with the third gate electrode and is spaced from the fin by the first distance.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee Bum Hong, Chang Min Hong
  • Patent number: 10388784
    Abstract: A power chip and a transistor structure thereof are provided. The transistor structure includes a semiconductor substrate, a plurality of gate structures, a plurality of first doped regions and a second doped region. The gate structures are disposed on the semiconductor substrate. The first doped regions are formed respectively in a plurality of first areas surrounded by the gate structures. The second doped region is formed in a second area among the gate structures. Each of the gate structures is arranged in an enclosed ring, and the shape of each of the gate structures is octagon.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: August 20, 2019
    Assignee: Excelliance MOS Corporation
    Inventor: Chu-Kuang Liu
  • Patent number: 10388782
    Abstract: A semiconductor device includes a main transistor and a sense transistor. The main transistor is disposed in a semiconductor body and includes a plurality of sections which are individually controllable via separate gate electrodes disposed above the semiconductor body. The sense transistor is disposed in the same semiconductor body as the main transistor and has the same number of individually controllable sections as the main transistor. Each individually controllable section of the sense transistor is configured to mirror current flowing through one of the individually controllable sections of the main transistor and is connected to the same gate electrode as that individually controllable section of the main transistor. An electronic circuit that includes the semiconductor device and a current sense circuit that outputs a current sense signal representing the current mirrored by the sense transistor is also provided.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: August 20, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Giuseppe Bernacchia, Riccardo Pittassi, Oliver Blank
  • Patent number: 10388728
    Abstract: Structures that include an airgap and methods for forming a structure that includes an airgap. A layer stack is epitaxially grown on a substrate and includes a first semiconductor layer and a second semiconductor layer on a substrate. A plurality of openings are formed that extend through a device region of the first semiconductor layer to the second semiconductor layer. The second semiconductor layer is etched through the openings and selective to the substrate and the first semiconductor layer so as to form an airgap that is arranged in a vertical direction between the substrate and the device region. A device structure is formed in the device region of the first semiconductor layer.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Michael Zierak, Anthony K. Stamper, John J. Pekarik, Vibhor Jain
  • Patent number: 10388574
    Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: August 20, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Juyoun Kim
  • Patent number: 10381277
    Abstract: A chip and a method for producing the chip with a plurality of measurement regions which are provided with electrodes for electrically detecting reactions in which, in order to reliably separate the individual measurement regions from one another, a monolayer of a fluorosilane is formed on the chip surface which has strongly hydrophobic properties. Therefore, during spotting with a liquid, the drops of liquid applied by spotting can be reliably prevented from coalescing, and thus, causing mixing of the substances in the drops of liquid which are supposed to be immobilized in the measurement regions.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: August 13, 2019
    Assignee: BOEHRINGER INGELHEIM VETMEDICA GMBH
    Inventors: Markus Schieber, Heinz Schoeder
  • Patent number: 10381267
    Abstract: A method of forming source/drain contacts with reduced capacitance and resistance, including, forming a source/drain and a channel region on an active region of a substrate, forming a dielectric fill on the source/drain, forming a trench in the dielectric fill, forming a source/drain contact in the trench, forming an inner contact mask section on a portion of an exposed top surface of the source/drain contact, removing a portion of the source/drain contact to form a channel between a sidewall of the dielectric fill and a remaining portion of the source/drain contact, where a surface area of the remaining portion of the source/drain contact is greater than the surface area of the exposed top surface of the source/drain contact, and forming a source/drain electrode fill on the remaining portion of the source/drain contact.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Chi-Chun Liu, Peng Xu
  • Patent number: 10374024
    Abstract: A flexible display panel includes a display region and a non-display region. Capacitors are added to an empty region of the non-display region. The capacitors have ability to buffer a release of electrostatic charges, thereby reducing damage to inner devices and metal wiring film layers caused by the electrostatic charges and protecting the metal wiring film layers from being damaged and destroyed by the electrostatic charges during manufacturing active thin-film transistors of the flexible display panel.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: August 6, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Xing Wang
  • Patent number: 10373897
    Abstract: A device may include a carrier, a semiconductor chip arranged over a first surface of the carrier, and an encapsulation body comprising six side surfaces and encapsulating the semiconductor chip. A second surface of the carrier opposite to the first surface of the carrier is exposed from the encapsulation body. The device may further include electrical contact elements electrically coupled to the semiconductor chip and protruding out of the encapsulation body exclusively through two opposing side surfaces of the encapsulation body which have the smallest surface areas of all the side surfaces of the encapsulation body, and an electrically insulating layer arranged over the exposed second surface of the carrier.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: August 6, 2019
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Ralf Otremba, Felix Grawert, Amirul Afiq Hud, Uwe Kirchner, Teck Sim Lee, Guenther Lohmann, Hwee Yin Low, Edward Fuergut, Bernd Schmoelzer, Fabian Schnoy, Franz Stueckler