Patents Examined by Charles D. Garber
  • Patent number: 11895927
    Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: February 6, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Chang Hsu, Tang-Chun Weng, Cheng-Yi Lin, Yung-Shen Chen, Chia-Hung Lin
  • Patent number: 11862722
    Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a barrier layer, a third nitride semiconductor layer and a gate structure. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The barrier layer is disposed on the second nitride semiconductor layer and has a bandgap greater than that of the second nitride semiconductor layer. The third nitride semiconductor layer is doped with impurity and disposed on the barrier layer. The gate structure is disposed on the third nitride semiconductor layer.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: January 2, 2024
    Assignee: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.
    Inventors: Chao Yang, Chunhua Zhou, Qiyue Zhao
  • Patent number: 11430374
    Abstract: Provided is a display apparatus including a plurality of subpixels and configured to emit light based on each of the plurality of subpixels, the display apparatus including a substrate, a driving layer provided on the substrate and including a driving element which is configured to apply current to the display apparatus, a first electrode electrically connected to the driving layer, a first semiconductor layer provided on the first electrode, an active layer provided on the first semiconductor layer, a second semiconductor layer provided on the active layer, a second electrode provided on the second semiconductor layer, and a reflective layer provided on the second semiconductor layer, wherein light emitted from the active layer resonates between the first electrode and the reflective layer.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: August 30, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junhee Choi, Kiho Kong, Nakhyun Kim, Junghun Park, Jinjoo Park, Joohun Han
  • Patent number: 11424268
    Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a substrate having a first surface, a plurality of ferroelectric layers stacking over the first surface, and a plurality of metal layers stacking over the first surface of the substrate, wherein each of the metal layers is on each of the ferroelectric layers. The operations of the method for manufacturing the semiconductor structure includes providing a substrate having a first surface, and forming a plurality of stack units over the first surface of the substrate The forming of each of the stack units includes the operations of forming a ferroelectric layer and forming a metal layer on the ferroelectric layer.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Han-Jong Chia, Yu-Ming Lin, Zhiqiang Wu, Sai-Hooi Yeong
  • Patent number: 11393846
    Abstract: A ferroelectric memory device according to an aspect of the present disclosure includes a substrate having a channel layer, a first ferroelectric layer disposed on the channel layer, a ferroelectric induction layer disposed on the first ferroelectric layer, the ferroelectric induction layer including an insulator, a second ferroelectric layer disposed on the ferroelectric induction layer, and a gate electrode layer disposed on the second ferroelectric layer.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: July 19, 2022
    Assignee: SK hynix Inc.
    Inventors: Hyangkeun Yoo, Seho Lee, Jae-Gil Lee
  • Patent number: 11387382
    Abstract: The invention provides a bifacial photovoltaic cell comprising: a semiconductor substrate, the substrate comprising an n+ layer on a first surface, and a p+ layer on a second surface. The n+ layer comprises an n-dopant and the p+ layer comprises a p-dopant. The cell further comprises a passivating and/or antireflective coating on the doped first and second surfaces. The cell is characterized in that the second surface of the semiconductor substrate has an area substantially devoid of the p-dopant on an edge of the second surface having a width in the range of 0.1-0.5 mm; wherein the area is formed by etching the semiconductor substrate.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: July 12, 2022
    Assignee: SOLAROUND LTD.
    Inventors: Naftali Paul Eisenberg, Lev Kreinin
  • Patent number: 11380784
    Abstract: Provided is a semiconductor device that includes a first conductivity type well region below a gate runner portion, wherein a diode region includes first contact portions, a first conductivity type anode region, and a second conductivity type cathode region; wherein the well region contacts the diode region in the first direction, and when an end of the well region, an end of at least one of first contact portions, and an end of the cathode region that face one another in the first direction are imaginary projected on an upper surface of the semiconductor substrate, a first distance is longer than a second distance, the first distance being a distance between the end of the well region and the end of the cathode region, and the second distance being a distance between the end of the well region and the end of the at least one first contact portion.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: July 5, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Misaki Takahashi, Yuichi Harada, Kouta Yokoyama
  • Patent number: 11348850
    Abstract: A vehicle power conversion device includes: a housing configured to accommodate an electronic component therein and having an opening; and a cooling device. The cooling device includes a base being a plate-shaped member and heat sinks attached to the base. The base has a groove with refrigerant enclosed. The base has a first main surface to which the electronic component is to be attached, and covers the opening by the first main surface facing an interior of the housing. The heat sinks are joined, at intervals, onto the second main surface of the base.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: May 31, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hirokazu Takabayashi, Ryosuke Nakagawa, Shigetoshi Ipposhi, Masaru Shinozaki, Hiroyuki Ushifusa
  • Patent number: 11342916
    Abstract: Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: May 24, 2022
    Assignee: SCHOTTKY LSI, INC.
    Inventors: Augustine Wei-Chun Chang, Pierre Dermy
  • Patent number: 11335783
    Abstract: A FeFET and a method of its manufacture are provided, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm<dr<150 nm, without impairing the data retention property of not less than 105 seconds and the data rewrite endurance property of not less than 108 times, of those that have hitherto been developed, and the FeFET allowing a memory window of 0.40 V or more when a sweep amplitude of the gate voltage is not more than 3.3 V.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: May 17, 2022
    Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, WACOM R&D CORPORATION
    Inventors: Shigeki Sakai, Mitsue Takahashi, Masaki Kusuhara, Masayuki Toda, Masaru Umeda, Yoshikazu Sasaki
  • Patent number: 11335831
    Abstract: An optical device case (100A) of an embodiment includes: a light-transmitting window member (20A); and a housing (10) which has a space for accommodating a light-receiving element and/or a light-emitting element (OE), wherein the window member (20A) includes a light-transmitting member (22), a polymer film (50) provided on an outer surface of the light-transmitting member (22), the polymer film (50) having a moth-eye structure at its surface, a contact angle of the surface with respect to water being not less than 140°, and a resistance heater (24) provided on an inner surface of the light-transmitting member (22).
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: May 17, 2022
    Assignees: SHARP KABUSHIKI KAISHA, GEOMATEC CO., LTD.
    Inventors: Hidekazu Hayashi, Hiroyuki Sugawara
  • Patent number: 11322489
    Abstract: A tiled display device is provided. The tiled display device includes a first substrate, a second substrate and a light-emitting unit. The first substrate includes a first main substrate and a first flexible substrate. The first flexible substrate is disposed on the first main substrate. The second substrate is disposed adjacent to the first substrate. The light-emitting unit is disposed on the first flexible substrate. In addition, a portion of the light-emitting unit protrudes from an edge of the first main substrate.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 3, 2022
    Assignee: INNOLUX CORPORATION
    Inventors: Hao-Jung Huang, Chao-Chin Sung
  • Patent number: 11315990
    Abstract: The present application discloses a display panel comprising a substrate, a transistor layer on the substrate, and a pixel-defining layer on a side of the transistor layer distal to the substrate to divide the display panel into a plurality of subpixel regions. At least one subpixel region includes a display sub-region and a light-sensitive sub-region. The display panel further includes a plurality of organic light-emitting diodes formed on the transistor layer respectively on the plurality of subpixel regions. Additionally, the display panel includes a plurality of pixel circuits formed in the transistor layer respectively on the plurality of subpixel regions. Each pixel circuit includes at least a display-driving sub-circuit coupled to one organic light-emitting diode. At least one pixel circuit in the at least one subpixel region includes a light-sensing sub-circuit formed on the light-sensitive sub-region and coupled to the display-driving sub-circuit formed on the display sub-region.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: April 26, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Libin Liu, Xiaowei Xu
  • Patent number: 11316063
    Abstract: According to various embodiments, there is provided a diode device including a semiconductor substrate of a first conductivity type, a first semiconductor region formed within the semiconductor substrate, an epitaxial region of the first conductivity type, and a second semiconductor region of a second conductivity type different from the first conductivity type. The first semiconductor region includes a chalcogen. The epitaxial region is formed over the first semiconductor region. The second semiconductor region is formed over the epitaxial region.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: April 26, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sandipta Roy, Khee Yong Lim, Lanxiang Wang, Kiok Boone Elgin Quek, Jing Hua Michelle Tng
  • Patent number: 11302597
    Abstract: A semiconductor device is provided with a heat dissipating face side skirt portion, which is a frame-form projection, on a heat dissipating face of a lead frame. Because of this, creepage distance increases with a small increase in an amount of resin, and insulating properties improve. Also, the heat dissipating face side skirt portion is molded via two transfer molding steps, wettability of the second molding resin with respect to a first molding resin and the lead frame increases, and adhesion improves. Furthermore, an end face of an inner lead is exposed in an element sealing portion on a mounting face side, and covered with a second thin molded portion molded using the second molding resin, whereby heat generated in a semiconductor element can efficiently be caused to escape from faces of both a first thin molded portion and the second thin molded portion, because of which heat dissipation improves.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: April 12, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takanobu Kajihara, Katsuhiko Omae, Takashi Nagao, Masayuki Funakoshi, Norio Emi, Atsuki Fujita, Yuki Okabe
  • Patent number: 11215861
    Abstract: The present disclosure provides a display panel and a method for improving display quality of the display panel. The display panel includes a temperature control apparatus. Specifically, the temperature control apparatus includes a temperature sensor in a non-display area of the display panel for detecting a temperature of the display panel, a change-temperature component in a display area of the display panel for performing a change-temperature treatment on the display panel, and a controller electrically connected to the temperature sensor and the change-temperature component for controlling the change-temperature component to operate according to the temperature of the display panel.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: January 4, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Lijun Zhao
  • Patent number: 11217460
    Abstract: A method of assembling a flip chip IC package includes applying core underfill material to a surface of a package substrate in a pattern including an area corresponding to a core region of an IC die thereon that is to be attached, that excludes of an area corresponding to corners of the IC die. The IC die is bonded to the package substrate by pushing the IC die with a sufficient force for the core underfill material is displaced laterally by the bumps so that the bumps contact the land pads. After the pushing the corners of the IC die are not on the core underfill. Edge underfilling includes dispensing a second underfill material that is curable liquid to fill an area under the corners of the IC die. The second underfill material is cured resulting in it having a higher fracture strength as compared to the core underfill.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: January 4, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Makarand Ramkrishna Kulkarni, Tae Kim
  • Patent number: 11211292
    Abstract: Some embodiments include an assembly having a CMOS tier. The CMOS tier includes a PMOS deck and an NMOS deck, with the decks being vertically offset relative to one another. The PMOS deck has p-channel transistors which are substantially identical to one another, and the NMOS deck has n-channel transistors which are substantially identical to one another. An insulative region is between the PMOS deck and the NMOS deck. The CMOS tier has one or more circuit components which include one or more of the n-channel transistors coupled with one or more of the p-channel transistors through one or more conductive interconnects extending through the insulative region. Some embodiments include methods of forming assemblies to comprise one or more CMOS tiers.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Kurt D. Beigel
  • Patent number: 11183414
    Abstract: In semiconductor packaging technologies, a secondary packaging method of a TSV chip and a secondary package of a TSV chip are provided. The TSV chip has a forward surface and a counter surface that are opposite to each other, a BGA solder ball is disposed on the counter surface, and the secondary packaging method includes: placing at least one TSV chip on a base on which a stress relief film layer is laid; cladding the TSV chip via a softened molding compound; removing the base after the molding compound is cured, to obtain a secondary package of the TSV chip; and processing a surface of the secondary package to expose the BGA solder ball.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: November 23, 2021
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventors: Baoquan Wu, Wei Long, Yuping Liu
  • Patent number: 11183656
    Abstract: The present disclosure provides an organic electroluminescent device, a display substrate including the organic electroluminescent device, and a display apparatus including the display substrate. The organic electroluminescent device includes an anode, a cathode, and a light emitting layer between the anode and the cathode, wherein a hole transport layer is provided between the anode and the light emitting layer and includes a hole transport material and a P-type doping material, electrons of the highest occupied molecular orbit of the P-type doping material are excitable to the lowest unoccupied molecular orbit of the P-type doping material under the excitation of light to cause an electron transfer reaction from the highest occupied molecular orbit of the hole transport material to the highest occupied molecular orbit of the P-type doping material.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: November 23, 2021
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Tiancheng Yu