Abstract: A package includes a first dielectric layer, a device die over and attached to the first dielectric layer, an active through-via and a dummy through-via, and an encapsulating material encapsulating the device die, the active through-via, and the dummy through-via. The package further includes a second dielectric layer over and contacting the device die, the active through-via, and the dummy through-via. An active metal cap is over and contacting the second dielectric layer and electrically coupling to the active through-via. The active metal cap overlaps the active through-via. A dummy metal cap is over and contacting the second dielectric layer. The dummy metal cap overlaps the dummy through-via. The dummy metal cap is separated into a first portion and a second portion by a gap. A redistribution line passes through the gap between the first portion and the second portion of the dummy metal cap.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming multiple hybrid shallow trench isolation structures in a substrate; forming an alternating dielectric stack on the substrate, the alternating dielectric stack including multiple dielectric layer pairs each comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming multiple channel structures in the alternating dielectric stack; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction to divide the multiple channel structures and to expose a row of hybrid shallow trench isolation structures; replacing the second dielectric layers in the alternating dielectric stack with multiple gate structures through the slit; forming a spacer wall to fill the slit; and forming multiple array common source contacts each in electric contact with a corresponding hybrid shallow trench isolation structure.

Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier. The conductive structure can include a base and a plurality of interconnections extending continuously away from the base toward the carrier. The microelectronic element can be positioned between at least two adjacent interconnections of the plurality of interconnections. The conductive structure may be bonded to the carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The plurality of interconnections and the microelectronic element may be encapsulated. The carrier may be removed to expose free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and bond pads of the microelectronic element may be conductively connected with terminals of the microelectronic package. The conductive structure may be patterned to form external contacts.

Abstract: The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes forming a multi-material layer on a bottom structure on a substrate, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, selectively removing the second layer from the multi-material layer from the substrate, and selectively oxidizing the bottom structure on the substrate after removing the second layer from the multi-material layer.

Abstract: Integrated active-matrix light emitting pixel arrays based displays and methods of fabricating the integrated displays are provided. One of the methods includes: forming a plurality of light emitting elements on a substrate, each of the light emitting elements including multiple semiconductor layers epitaxially grown on the substrate and being configured to emit light with a single color, integrating the light emitting elements formed on the substrate with a backplane device, such that each of the light emitting elements is bonded and conductively coupled to a respective pixel circuit in the backplane device, and then removing the substrate from the light emitting elements that remain integrated with the backplane device.

Abstract: A minute transistor is provided. A transistor having low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. An electrode including the transistor is provided. A novel electrode is provided. The electrode includes a first conductive layer containing a metal, an insulating layer, and a second conductive layer. The insulating layer is formed over the first conductive layer. A mask layer is formed over the insulating layer. The insulating layer is etched using plasma with the mask layer used as a mask, whereby an opening is formed in the insulating layer so as to reach the first conductive layer. Plasma treatment is performed on at least the opening in an oxygen atmosphere. By the plasma treatment, a metal-containing oxide is formed on the first conductive layer in the opening. The oxide is removed, and then the second conductive layer is formed in the opening.

Abstract: A method of forming source/drain contacts with reduced capacitance and resistance, including, forming a source/drain and a channel region on an active region of a substrate, forming a dielectric fill on the source/drain, forming a trench in the dielectric fill, forming a source/drain contact in the trench, forming an inner contact mask section on a portion of an exposed top surface of the source/drain contact, removing a portion of the source/drain contact to form a channel between a sidewall of the dielectric fill and a remaining portion of the source/drain contact, where a surface area of the remaining portion of the source/drain contact is greater than the surface area of the exposed top surface of the source/drain contact, and forming a source/drain electrode fill on the remaining portion of the source/drain contact.

Abstract: A method of manufacturing an electronic device includes preparing an electronic component including a first substrate on a main surface of which a functional unit and a first resin layer are formed. The first resin layer has a first surface facing the main surface of the first substrate, a second surface opposed to the first surface, a cavity on the first surface enclosing the functional unit, and a portion defining a wall of the cavity. The first resin layer defines a recess provided with a solder layer on the second surface. The method further includes preparing a second substrate having an electrode pad formed on a main surface, aligning the electronic component with the second substrate to layer the solder layer and the electrode pad in contact with the solder layer, and forming the electronic component and the second substrate into the electronic device.

Abstract: A touch panel and a fabrication method thereof are provided. The touch panel includes a first axial electrode containing a plurality of first conductive units. Two adjacent first conductive units are separated and electrically connected by a first jumper and one first conductive unit has an extending part. The touch panel also includes a second axial electrode containing a plurality of second conductive units. Two adjacent second conductive units are connected through a connection part at the first jumper. Two adjacent second conductive units are separated and electrically connected by a second jumper at the extending part of the first conductive unit. The first axial electrode is insulated from and intersects the second axial electrode. The first and second jumpers have different axial directions.

Abstract: A semiconductor device includes: a first semiconductor element including a first signal electrode; a second semiconductor element, laminated on the first semiconductor element, including a second signal electrode; a sealing body; a first signal terminal connected to the first signal electrode; and a second signal terminal connected to the second signal electrode, wherein: the first signal terminal and the second signal terminal project from the sealing body and extend in a first direction; the first signal terminal and the second signal terminal are distanced from each other in a second direction; the first signal electrode and the second signal electrode are placed at different positions in the second direction; the first signal electrode is provided closer to the first signal terminal than to the second signal terminal; and the second signal electrode is provided closer to the second signal terminal than to the first signal terminal.

Abstract: Provided are an organic light-emitting display panel and an organic light-emitting display apparatus. The organic light-emitting display panel includes an array base substrate including a plurality of driving elements, and includes a plurality of organic light-emitting devices. Each of the plurality of organic light-emitting devices is corresponding to a respective one of the plurality of driving elements, and the each of the plurality of organic light-emitting devices includes an anode and a cathode, a cathode, an organic luminous layer, an electron transport layer, and a transition layer. The organic luminous layer is disposed between the anode and the cathode, the electron transport layer is disposed between the luminous layer and the cathode, and the transition layer is disposed between the cathode and the electron transport layer, and the transition layer includes an organic material.

Abstract: This patent describes embodiments of systems, apparatus and methods to provide improved control and coordination of a multiplicity of electric distribution grid-connected, energy storage units deployed over a geographically-dispersed area.

Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of forming a target layer surrounding a vertical nanostructure. In one aspect, a method includes providing a substrate having a substrate surface. The method additionally includes forming a vertical nanostructure extending outwardly from a substrate surface. The vertical nanostructure has a sidewall surface, where the sidewall surface has an upper portion and a lower portion. The method additionally includes forming a target layer at least along the sidewall surface of the vertical nanostructure and on the substrate surface. The method additionally includes forming a protection layer covering the target layer and removing an upper portion of the protection layer, thereby exposing the target layer along the upper portion of the sidewall surface of the vertical nanostructure.

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

Abstract: Provided is a nanosheet semiconductor device. In embodiments of the invention, the nanosheet semiconductor device includes a channel nanosheet formed over a substrate. The nanosheet semiconductor device includes a buffer layer formed between the substrate and the channel nanosheet. The buffer layer has a lower conductivity than the channel nanosheet.

Abstract: A display device includes a base, a light emitting device on a first surface of the base, and a plate-like inorganic layer on a second surface of the base, the plate-like inorganic layer including a first plate-like inorganic particle with a first size and a second plate-like inorganic particle with a second size different from the first size.

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

Abstract: A fan-out semiconductor package includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, an encapsulant encapsulating the semiconductor chip, and an electromagnetic wave shielding layer disposed on the semiconductor chip and including a plurality of degassing holes. The electromagnetic wave shielding layer includes a first region and a second region in which densities of the degassing holes are different from each other, the first region having a density of the degassing holes higher than a density of the degassing holes in the second region.

Abstract: Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. A dielectric spacer is formed adjacent to a vertical sidewall of the gate structure. A semiconductor layer is formed on the top surface of the semiconductor body. The semiconductor layer is arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located in a space between the semiconductor layer and the vertical sidewall of the gate structure. A second section of the dielectric spacer that is located above a top surface of the semiconductor layer is removed. An air-gap spacer is formed in a space from which the second section of the dielectric spacer is removed.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dual thickness fuse structures and methods of manufacture. The structure includes a continuous wiring structure on a single wiring level and composed of conductive material having a fuse portion and a thicker wiring structure.