Abstract: A technique for converting linearly encoded digital signals into non-linearly encoded digital signals using two separate ROMs.

Abstract: A self-bias circuit is employed for automatically changing the reference voltage of a comparator of an A/D converter of successive approximation type. The self-bias circuit is responsive to a voltage at a summing point where an input analog signal, an offset bias and an output analog signal from a D/A converter are added to each other. The self-bias circuit comprises a resistor and a capacitor so that the capacitor is charged by an average current passing through the resistor connected to the summing point, and the voltage across the capacitor will be used as the reference voltage of the comparator. When the input analog signal amplitude is small, the reference voltage is shifted so that noises superposed on the voltage at the summing point does not cause the comparator to produce an erroneous output signal with which the state of the MSB is undesirably changed.

Abstract: Apparatus for producing an analog signal--having a relative amplitude that is indicative of the direction and rate of rotation of a shaft--from a pair of pulse streams provided by a shaft encoder coupled to the shaft. The invention includes circuitry for comparing the phase relationship between the signals to determine direction, for generating a digital pulse of a fixed pulse-width for each pulse contained in one of the pulse streams, and integrating the time or inverted form of the digital pulse, depending upon the determined direction, to produce the analog signal.

Abstract: An encoding system for converting binary data to code sequences suitable for recording or reproducing where each 2-bit data word in a binary data sequence is converted into 4-bit codes so as thereby cause from not less than two and not greater than eight code bits of "0" value to exist between any code bit of value "1" and a next succeeding code bit of value "1" in this converted code sequence.

Abstract: A two-stage single pass adaptive modeling method and means for a finite alphabet first order MARKOV symbol source where the model is used to control an encoder on a per symbol basis thereby enabling efficient compression within a fixed preselected implementation complexity.

Abstract: A semiconductor circuit having an improved current switching function is disclosed. The circuit comprises at least one current switch unit including a current source, a current output node, a field effect transistor connected between the current output node and the current source, an inverting amplifier having an output supplied to a gate of the field effect transistor and an input connected to the junction point of the current source and the field effect transistor and means for controlling operation of the amplifier.

Abstract: A length oriented arithmetic decoder constrained to ONE-TO-ONE map in the data string to run length limited string direction and ONTO map in the run length limited to data string direction through an arithmetic encoder preserves the fixed rate of the RLL string and ensures representability. A finite state machine responsive to the arithmetic decoder output provides the trial augends and shift amounts necessary for the magnitude comparison decoding of the data string treated as if it were arithmetically compressed. A finite state machine is also used with the arithmetic encoder for providing trial augends and shift amounts but is responsive to successive RLL symbols as if it were ordinary source strings. The encoder combines the augends with a predetermined retained portion of the generated data string.

Abstract: For the automatic calibration of an analog-to-digital converter an analog calibration quantity is measured and the digital signal is compared with a digital calibration signal associated with the calibration quantity. A digital difference signal is applied to a register for influencing its counting capacity, while the register contents of pulses counted during the measurement also represents one of the parameters involved in the analog-to-digital conversion. Because of the fully digital character of the calibration, this calibration can be performed very rapidly and accurately.

Abstract: A converter includes a voltage selector which employs IGFETs as voltage switching elements, and a controller which controls the IGFETs. Each of the IGFETs in the voltage selector is made either the P-channel type or the N-channel type, depending upon a voltage level to be thereby switched and a level of a binary signal supplied from the controller. As a result, a voltage of comparatively great level can be switched by a binary signal of small level amplitude.

Abstract: A variable speed reproduction system includes a memory in which analog signal is stored as sampled digital data. A variable frequency digital low-pass filter is receptive of the data read out of the memory. A counter provides a binary representation of a count value of time base clock pulses to a comparator for detecting a coincidence with a variable speed setting of a variable resistor. The output of the comparator resets the counter and is used as a source of reading the data out of the memory. The cut-off frequency of the digital filter is controlled in response to the setting of the resistor so that the high frequency component of the analog equivalent of the input digital data which is higher than one-half of the data reading frequency is eliminated to prevent foldover distortion noise which might occur as a result of the difference between the recording and reproducing speeds.

Abstract: A multislope A/D converter is presented which employs a multislope integration technique enabling the use of a single comparator to detect polarity changes in the integrator output voltage. The A/D converter integrates a test signal during a run-up interval and integrates a discharging signal during the run-up interval as well as during a pre-run-down interval and a run-down interval subsequent to the run-up interval. The magnitude and polarity of the discharging signal are regulated in accordance with a switching scheme that converts circuit element mismatch error into offset measurement errors which can be eliminated by subtraction. The discharging current during the pre-run-down interval ensures that the slope of the integrator output voltage at the final polarity change is independent of test signal polarity thereby avoiding a comparator hysteresis error. A decade-run-down technique is employed during the run-down interval enabling the digital conversion to be implemented on a decade counter.

Abstract: An analog-digital converter designed to provide digital data by converting analog input voltage signals into pulse signals by a voltage-frequency converter, and counting said pulse signals by a counter, the improvement being that the A-D converter comprises a sequence controller which selectively supplies low-level or high-level input voltage signals to the A-D converter before analog input signals being measured are received therein.

Abstract: A system for encoding images by assigning variable-length code words to fixed positions in a dynamic stack. Each position in the dynamic stack is occupied by a representation of an encodable image feature, such as a run-length or a vertical correlation. These codes are arranged in order of their respective frequencies of occurrence. The order in which these features are stacked is varied dynamically by the system, in accordance with their respective frequencies of occurrence and a predetermined scheme. Thus, the system can adapt to different types of documents being scanned, or to changes of scanning resolution. A relationship exists between the code words and the stack positions, which are not permanently assigned to specific image features. This arrangement ensures that the lengths of code words will be inversely related to their frequencies of occurrence under all conditions.

Abstract: The sum of an analog input signal and a positive feedback signal is applied to an A/D converter. A D/A converter device including a D/A converter and a delay device for delaying an analog feedback signal which is a signal formed by D/A converting the output of the A/D converter by one conversion operation period of the A/D converter. The positive feedback signal is formed by multiplying the analog feedback signal by a given feedback coefficient.

Abstract: A system for digitizing transient signals comprises a plurality of high-speed sampling gates connected in parallel to a common input terminal, these gates working in interleaved relationship into respective charge-transfer devices each including a multiplicity of storage cells which are successively loaded in a first operational phase with analog samples delivered by the corresponding gate. After having been fully loaded, the several transfer devices are read out cell by cell in a second operational phase via a multiplexer into an analog/digital converter at a rate which is substantially lower than the sampling rate.

Abstract: Apparatus for decreasing the d.c. component of digital signals derived from an analogue signal which may be a television video or audio signal, comprises analogue to digital converter means for producing digital words corresponding to samples of the analogue signal, a memory device for subjecting the words to a specific code conversion and circuitry for combining the coded words together in groups of two words with one of the words ones complemented and preferably partially interleaved with the other of the words of each group. The apparatus is applicable to use for both the recording of color T.V. video signals as well as for the transmission of such signals.

Abstract: In the error signal feature sensor of the device, an analog synthesized signal is produced throughout the first portion of each period of the analog noisy test signal to be acquired by means of the digital value of samples memorizing in a random access memory and a digital-to-analog converter. The noisy signal and the synthesized signal are compared therebetween at predetermined sampling times in predetermined number. The sign and modulus of the error signal in relation to a predetermined threshold voltage are written in the memory. During the second portion of the period without the noisy signal, a processing unit as a microprocessor calculates the new digital values of the samples in term of comparison results and the preceding digital values of the samples in accordance with a particular algorithm. A new comparison and calculation cycle is performed and so on.

Abstract: A digital to analog converter is provided which comprises first and second reference voltage terminals to which are supplied positive voltages, a voltage divider which comprises a plurality of resistors connected in series between the first and second reference voltage terminals, and a switch array part connected to the voltage divider for producing a voltage according to the digital signal supplied to the gate terminals. The switch array part comprises CMOS field effect transistor circuits in which the first channel MOS field effect transistors are arranged at one side of the voltage divider, the second channel MOS field effect transistors are arranged at the other side of it, and the wirings of both channel field effect transistors cross the voltage driver with electrically insulated form from the voltage divider. The p-type well region as the back gate of the NMOS field effect transistor is connected to the reference voltage terminal to which a lower positive voltage is supplied.

Abstract: High-speed, digital/analog converter using a logic circuit with coupled emitters comprising a first stage formed by logic gates having a plurality of inputs and one output and a second current amplification stage formed by the same number of transistors as there are logic gates, e.g. transistor having an emitter, a base and a collector, each case of a transistor of the second stage being connected to the output of a logic gate of the first stage, said logic circuit also having a first supply line and a voltage V.sub.cc1 and connected to all the collectors of the transistors of the amplification stage, a second supply line at voltage V.sub.cc2, which differs from the first and is connected to the logic gates of the first stage and a third supply line at a voltage V.sub.EE and connected to the two stages, wherein the converter comprises resistors connected to the emitters of transistors, resistor connected to the transistor of rank k having the value R/2.sup.

Abstract: A logarithmic analog-to-digital converter which provides a digital representation of the logarithm of the ratio of an input voltage and a reference voltage. The converter determines the ouptut via a successive approximation technique. The input voltage is amplified by selected ones from among a plurality of exponentially related gains; and the reference voltage is attenuated by selected ones of a set of exponentially related attenuation factors. The amplified input signal and the attenuated reference signal are compared, and the results of this comparison for a series of attenuations and/or amplification factors produces the desired logarithmic representation.