Abstract: A monolithic integrated circuit D-to-A converter and programmable AC resistor network and current source is disclosed in which an array of FET cells formed on a semiconductor body is divided into a plurality of distinct sets which may be grouped in two groups of corresponding sets. The source and drain regions respectively of all of the cells in each group are connected in common. The gate regions of the cells in each distinct set are also connected. In embodiments comprising two groups of cells, gate control logic is included which may supply signals of opposite binary states respectively to the gate regions of corresponding sets of cells in the two groups.

Abstract: Disclosed is a pulse width decoder which receives a double frequency modulated (DFM) waveform and recovers therefrom the contained NRZ-L data and clock information. Basically, the decoder looks for long and short pulses in the DFM waveform. A long pulse is decoded as a "0", while a pair of short, opposite polarity pulses are decoded as a "1". In addition, in order to allow for pulse shortening in the DFM waveform, a short pulse followed by a long pulse is interpreted as a "1". The clock signal is primarily derived from two delayed versions of the DFM waveform to create one clock edge every bit time.

Abstract: A digital to analog converting apparatus is disclosed, which converts an analog output voltage into a digital value and compares the digital value with a digital input value, and corrects the analog output voltage according to the result of the comparison. The apparatus includes a current source for supplying current according to the result of the comparison and a capacitor which is charged and discharged by the current from the current source. The output voltage of the capacitor is provided as the analog output voltage.

Abstract: For the dynamic compensation of the offset voltage in such converters each non-inverting comparator input (+) is connected via a first transfer transistor (T11, T12, T1p) to the signal input (SE) and via a second transfer transistor (T21, T22, T2p) to the associated voltage divider tap of the voltage divider as applied to the reference voltage (Ur). Moreover, each inverting comparator input (-), via a capacitor (C1, C2, Cp) is applied to the associated voltage divider tap and, via a third transfer transistor (T31, T32, T3p) and across a resistor (R'1, R'2, R'p) arranged in series therewith, to the associated comparator output. The second and third transfer transistors are rendered conductive during short intervals (T) between conversions by the clock signal (F), and the first transfer transistors are rendered non-conductive via the inverter (IV), and during the conversion time (t) the first transfer transistors are rendered conductive, and the second and third transfer transistors are rendered non-conductive.

Abstract: A hybrid integrated circuit data acquisition channel apparatus employing an operational amplifier fed by a low current differential bipolar transistor preamplifier having separate feedback gain and signal gain determining elements and providing an amplified signal output to a sample and hold and analog-to-digital converter circuits. The disclosed apparatus operates with low energy and small space requirements and is capable of operation without the sample and hold circuit where the nature of the applied input signal permits.

Abstract: A music data compression system is disclosed which includes an analog to digital converter for converting the analog music signal to digital sample signal form, a digital compression filter for compression filtering the digital sample signals, and an encoder for truncated Huffman encoding the compression filter output. An entropy setting unit is included in the system for step control of the signal supplied to the digital compression filter in accordance with one or more threshold levels of the envelope of the music signal, and for reducing the entropy of the signal with increases in the energy level of the music signal. Different codes may be implemented in accordance with the threshold(s), and an identifying code word is inserted in the Huffman encoded stream. A decoder, digital reconstruction filter, and digital to analog converter are used to reconstruct the analog music signal.

Abstract: An improved method and means of determining reflection coefficients that characterize an electrical signal that obtains characteristics of an all-zero inverse lattice filter. The reflection coefficients are obtained by filtering the signal, sample the filtered signal, obtaining the elements of a correlation array from the samples, initializing values of arrays forward residuals, backward residuals, and cross correlation of residuals, combining array elements to obtain a first reflection coefficient, removing from the forward, backward and cross-correlation arrays the effect of the first reflection coefficient, calculating from the revised arrays a second coefficient, and repeating the calculations to the desired order. In a second embodiment of the present invention, samples are selected from the digitized signal and multiplied by a windowing function.

Abstract: A digital-to-analog converter generates an analog output signal which is subject to periodically occurring non-monotonic increments in response to consecutive increments of the value of a digital word. Apparatus in accordance with the present invention substantially reduces effects of the non-monotonic increments from disturbing the analog output signal by rapidly incrementing the value of the digital word after the occurrence of each of said non-monotonic increments.

Abstract: In an A/D converter in which a first comparator A/D converter for providing the most significant bits of a digital output and a second comparator A/D converter for providing the least significant bits of the digital output are cascaded, a switching circuit is provided between the first A/D converter and the second A/D converter. This switching circuit is responsive to the comparison between an analog input voltage and first comparison reference voltages in the first A/D converter to apply two adjacent first reference voltages between which the analog input voltages lies to both ends of a voltage dividing circuit network of the second A/D converter to thereby provide second comparison reference voltages. In the second A/D converter, the second comparison reference voltages are compared with the analog input voltage by comparators, to provide the least significant bits of a digital output.

Abstract: The converter system includes a conventional N bit analog-to-digital (A/D) converter and also includes an automatic gain control circuit and DC offset circuit to alter the input analog signal to utilize the full N bit capacity of the A/D converter regardless of the amplitude of the input signal, within the range of the calibration of the system.

Abstract: A digital-to-analog signal converter (1000) provides an analog output signal by subtracting bit currents reflecting a digital input signal from a constant current source (1004, 1018-1022) at a current summer (1003), with the difference current being applied to a constant load. The subtracting of the current, rather than switching the current, avoids the modulation of an associated power source since the total current demand remains the same. In that low power operation is possible, the converter is particularly suited for use in an arrangement where only a low level of operating current is available from a power source.

Abstract: The invention relates to a method of encoding a stream of data bits of a binary source signal into a stream of data bits of a binary channel signal. The stream of data bits of the source signal is divided into a sequence of five permissible source words of variable length. Each of these five permissible source words is converted into a channel word with twice the number of data bits. This conversion has been selected in such a way that the error propagation is very small and the electronics can be very simple.

Abstract: A calibration circuit for a recirculation of remainder analog-to-digital (A/D) converter heuristically solves a multiple variable conversion equation. Input analog calibration and analog reference signals are compared in a comparator, and when the two signals have a predetermined relationship, the comparator generates an indicator signal. A microprocessor determines a first pattern of digital reference signals that, together with digital calibration signals generated by the microprocessor, causes the comparator to generate the indicator signal and a second pattern of digital reference signals that, together with the input analog calibration signals, causes the comparator to generate the indicator signal. The difference between the first and second patterns of digital reference signals is stored as conversion coefficients.

Abstract: Method and apparatus for decoding Huffman encoded words are disclosed which include the use of logic gates connected in the form of a binary decoding tree which includes branches, interior and leaf nodes. Bits of the encoded word are sequentially supplied to gates of the binary tree. Simultaneously, gate enable signals are supplied to gates of the binary tree. Both the data bits and enable signals are supplied to gates at increasingly higher levels of the binary tree. When an output is obtained from a gate associated with one of the leaf nodes of the tree, the process of sequentially supplying data bits and enable signals to gates of the binary tree is repeated for the next encoded word. The original data words are regenerated by use of outputs from said gates associated with leaf nodes of the binary tree.

Abstract: An analog-to-digital converter for converting an analog input voltage signal to a digital output voltage signal of m upper bits and n lower bits includes at least (2.sup.m+n -1) resistors connected in a series circuit to a voltage source for establishing respective reference voltages; at least (2.sup.m -1) upper bit voltage comparators for generating outputs indictive of the m upper bits, and having first and second inputs, the analog input voltage being applied to the first inputs and the second inputs being connected to the series circuit at respective intervals defining groups of the resistors; an upper bit encoder receiving the outputs of the upper bit voltage comparators and generating a switch control signal and a digital output voltage signal of m upper bits; at least (2.sup.

Abstract: A switched-capacitor analog-to-digital converter implements a conversion scheme involving execution of an algorithmic technique of successive-approximation comprising a number of iterations dependent upon the conversion resolution desired. The algorithm used requires analog processing to produce an output voltage that is two times the output voltage resolved to realize the previous bit. The "times two" function is realized by adding the voltage of the last iteration to itself (i.e., V+V=2V). This is accomplished by storing the output voltage resolved into the previous bit and separately storing a voltage corresponding to that voltage. Both stored voltages are then transferred to an integrator circuit which adds the two voltages and produces the output voltage to be resolved into the next bit.

Abstract: A digital to analog converter is employed in the digital line circuit of a telephone system and operates to convert a digital signal indicative of an analog speech signal back into a replica of the analog signal. The converter operates with an interpolated input digital signal to detect by means of a sign bit, the characteristic of an input digital word as being indicative of a positive or negative level. An error correcting signal is provided by the converter which is added to the next digital word to provide a compensated word having a sign bit determined by the remainder and the sign bit of the previous digital word. This word is then processed in sequence to produce an output pulse stream from the sign detector indicative of successive positive or negative values as defined by the input digital words, each of which are modified according to the error correcting signal.

Abstract: A bipolar digitizer (A/D converter) is disclosed which uses a single comparator circuit for initially determining the polarity of a sampled input signal and for thereafter comparing the absolute magnitude of the signal to an applied ramp voltage. The time required for the ramp voltage to exceed the magnitude of the sampled input signal is converted into a digital waveform representative of the magnitude of the sampled input signal. Resistive means are selectively connected in shunt with a signal storage capacitor to achieve bipolar signal compression and increased dynamic range.

Abstract: A position measuring device includes a conventional encoder, a scale member and an index member together arranged to provide two periodic waveforms of the same frequency and in quadrature with one another. Errors in the waveforms are corrected, and the corrected waveforms used to produce an indication of the position represented by the waveforms. The two positional indications are combined to give a high-resolution output. The conventional encoder may be absolute or incremental, and the device may be used to measure linear or angular position relative to a datum.

Abstract: In an analog to digital converter of the type wherein an analog input voltage is compared, at a comparator with a known reference voltage selected based on a digital data produced from a control circuit, an updated digital data is generated based on a result of the comparison, and the above operation is repeated to perform digital conversion sequentially from higher bit to lower bit, there are provided two capacitors of capacitances at a predetermined ratio which is so determined as to reduce the number of serial resistors in a voltage generator circuit adapted to generate the reference voltage based on the digital data produced from the control circuit, and a voltage developing at a junction between the two capacitors is coupled to the input of the comparator, so that a change in voltage of the voltage generator circuit is reduced at a predetermined ratio in accordance with electric charge distributed on the two capacitors and is applied to the input of the comparator.