Abstract: An analog/digital converter wherein an analog input signal is applied to a variable gain input amplifier which has an output connected to a subtractor. Also connected to the subtractor is the output of a D/A converter, the input of which is connected to the output of an integrator. The subtractor forms from the output signal of the input amplifier and that of the D/A converter a difference signal which is used by a tracking circuit for generating tracking signals for the integrator. For the purpose of widening the dynamic range, the input amplifier contains four scaling amplifiers, one of which is connected by a selection switch to the output of the input amplifier. The scaling factors of the second, third, and fourth scaling amplifiers are 1/4, 1/16, and 1/64, respectively, of that of the first scaling amplifier.

Abstract: A method for statistically calibrating an analog-to-digital converter with an electronic test system. A digital-to-analog converter which has been calibrated by premeasured weighting coefficients with respect to two-state orthogonal signals is excited with two state signals at each input bit which together represent a single signal with uniform amplitude probability with respect to time, and wherein each excitation signal is orthogonal with respect to all other excitation signals. The output of the digital-to-analog converter is detected by the analog-to-digital converter under test. The digital time domain output signals are then mapped into a transform domain to obtain weighting coefficients of each bit of the output response. Finally the transform domain weighting coefficients are weighted by the reciprocal of the premeasured weighting coefficients to obtain the unbiased weight of each bit of the analog-to-digital converter under test.

Abstract: A decoder is provided for decoding variable word length (VWL) encoded serial data in which each non-zero word comprises a start bit and an end bit of one state and a number of intervening bits of a different state, the number of such bits representing the magnitude of the word. The decoder comprises a binary counter and means responsive to a start bit of an input word for clearing the counter; responsive to any intervening bits present to enable the counter to count such intervening bits; and responsive to an end bit of said variable word to output the contents of the counter as a parallel binary word.Where the number of intervening bits is one less than the actual magnitude the decoder may include means for adding one to the counter output.The decoder may also detect an additional bit in the input word, representing, for example, its polarity, and provide a corresponding bit in the fixed-length output word.

Abstract: A digital signal is divided into a series of base words with each m bits of data. Each base word is converted to a converted word having n bits of data, wherein each of n and m is an integer and n is greater than m and the converted word has a predetermined maximum number of consecutive digital zeroes. The value of every odd-numbered bits of said converted word is detected. The converted word is controlled in response to the result of the detection and modulated as an NRZI (non-return to zero, inverted)-coded digital signal with a DC component of zero.

Abstract: Being given the number among P of a data, an attempt is made to find the number among N of said data in a group of N data incorporating P selected data. The sequence numbers of these P data appear in a register having N locations and the sequence number of the chosen data among P appears in a second register with P locations. The locations of the second register are connected to the rows of a switching circuit, each of these rows having N cells, which connect the input of one cell to the following cell of the same rank or to the following cell of the lower rank, as a function of the content of the corresponding location of the first register. Thus, at the outputs of the columns there are signals, whereof only one is at a level different from the others and corresponding to the number j among N of the chosen data.

Abstract: An analog-to-digital converter using a frequency tunable laser having output radiation of a frequency determined by the input voltage to the laser is described.

Abstract: A screen is disclosed on the surface of which a certain number of resistant conducting emitter strips and insulated conducting receiver strips are laid, the emitter strips being parallel-mounted with the terminals of a voltage generator and the receiver strips being interlaid between the receiver strips such that a conducting receiver strip lies between two resistant emitter strips. The electronics of control comprises an exploring stage to control the receiver strip time-related exploration. Thus, when a sufficiently conducting object used to indicate a point, has touched the surface and bridges an emitter strip and a receiver strip, a higher potential is detected on the corresponding receiver strip and the ordinate Y is given by the strip order number--while the abscissa X is calculated from measuring the potential between each ends of the emitter strip and the object.

Abstract: Automatically adaptable radix conversion apparatus which provides for radix conversion of an input number by successive serial division using look-up tables contained in a programmable read only memory (PROM). The particular conversion performed is automatically determined in response to input control information provided along with the input number which is used to select the appropriate set of tables in the PROM applicable to the particular conversion desired. The input control information is also used by the apparatus to permit it to automatically adjust to handle variable input number lengths and also to automatically terminate the conversion operation after operations on the last digit of the input number have been completed.

Abstract: An encoder is provided for encoding fixed length binary words into (VWL) encoded serial data in which each non-zero word comprises a start bit and an end bit of one state and a number of intervening bits of a different state, the number of such bits representing the magnitude of the word. In a preferred embodiment the coder comprises a multiplexer, a PROM and a flip-flop. The PROM provides a feedback signal comprising three parts - a control signal, a binary word representing the magnitude of the input word, and an output signal having either of two states. The feedback signal is repeatedly applied to the PROM by the multiplexer.The PROM responds by reducing the magnitude part of the feedback signal by one. Each time the cycle repeats, another bit appears at the output of the coder as the output signal. Accordingly, the number of such output bits corresponds to the magnitude of the input word. Eventually, when the magnitude has been reduced to zero, the multiplexer selects a new word to apply to the PROM.

Abstract: An analog-to-digital converter for converting an analog input signal to a digital output signal with m upper bits and n lower bits includes 2.sup.m+n -1 resistors establishing 2.sup.m+n reference voltages for comparison with an amplitude of the analog input signal, 2.sup.m -1 voltage comparing circuits for comparing the analog input signal with 2.sup.n step-by-step reference voltages, a first encoder for encoding the output signals of the 2.sup.m-1 voltage comparing circuits for generating m upper bits of the digital output signal, a matrix circuit having 2.sup.m (2.sup.n -1) voltage comparators for comparing the analog input signal with the remaining reference voltages of the 2.sup.m+n references voltages, the other voltage comparing circuits being supplied output signals of the matrix circuit and a second encoder for encoding output signals of the other voltage comparing circuits for generating n lower bits of the digital output signal.

Abstract: The generation of NRZ representations of RLL encoded datastreams utilizes a length oriented arithmetically recursive RLL encoder whose finite state encoding transition space has assigned RLL symbols to state transitions. By constraining the paths, and hence restricting the set of allowable RLL symbol streams, then selectable notch frequencies in the spectra of the NRZ representation can be secured. Recovery of data is obtained by the logical dual of this process. Also, a NRZ bit stream representation exhibits a frequency spectrum notched at f/kn Hertz if k NRZ source codestreams are k-way interleaved.

Abstract: A method and optical arithmetic apparatus for converting residue numbers into positionally notated numbers utilize linear periodic structures which can be shifted relative to one another, each linear periodic structure being allocated to a prime number module of those prime number modules which are utilized in the residue representation of a decimal number, with the duration of the period for a structure being proportional to the module allocated thereto. The structures may be structures for generating standing light waves. The shift of the phase positions of the light waves is undertaken by respective phase modulators with the waves being shifted out of an original phase position in accord with the allocated residue module or the sum of the modules. The decoded result is obtained by noting the values occurring at positions where the structures coincided before shifting by means of the phase modulators and which coincide after the shift.

Abstract: A D/A converter that operates according to the parallel method, in which each of the conversion stages assigned to a given bit of the digital word to be converted has, in the conventional manner a current source that delivers a weighted constant current and an electronic switch with an output which is applied to the common output of the converter and which is controlled according to the command given by the control bit assigned to each particular stage. In order to prevent the errors in the output signal that occur in the customary D/A converters of this kind as a result of the differing response times of individual switches, each individual switching stage is controlled by a differential signal, in which the switching time for the rising edges is adjusted to be different from that for the falling edges.

Abstract: A stream of source characters, which occur with varying relative frequencies, is encoded into a compressed stream of codewords, each having one, two or three subwords, by ranking the source characters by their current frequency of appearance, encoding the source characters having ranks no higher than a first number as one sub-word codewords, source characters having ranks higher than the first number but no higher than a second number as two sub-word codewords, and the remaining source characters as three sub-word codewords. The first number is changed and the second number is recalculated as required by the changing frequencies of the source characters to minimize the length of the stream of codewords.

Abstract: A stream of source characters, which occur with varying relative frequencies, is encoded into a compressed stream of codewords, each having one, two or three subwords, by ranking the source characters by their current frequency of appearance, encoding the source characters having ranks no higher than a first number as one sub-word codewords, source characters having ranks higher than the first number but no higher than a second number as two sub-word codewords, and the remaining source characters as three sub-word codewords. The first number is changed and the second number is recalculated as required by the changing frequencies of the source characters to minimize the length of the stream of codewords.

Abstract: A data compressor compresses an input stream of data character signals by storing in a string table strings of data character signals encountered in the input stream. The compressor searches the input stream to determine the longest match to a stored string. Each stored string comprises a prefix string and an extension character where the extension character is the last character in the string and the prefix string comprises all but the extension character. Each string has a code signal associated therewith and a string is stored in the string table by, at least implicitly, storing the code signal for the string, the code signal for the string prefix and the extension character. When the longest match between the input data character stream and the stored strings is determined, the code signal for the longest match is transmitted as the compressed code signal for the encountered string of characters and an extension string is stored in the string table.

Abstract: A voltage-to-frequency and analog-to-digital conversion circuit using a microprocessor-controlled capacitor charge-discharge scheme provides high resolution and low component count and is particularly suitable for use with resistance bridge transducers.

Abstract: A data signal is processed to change its form and spectral content without introducing undesirable frequency and amplitude effects. Multiple data signal states, which determine the essential characteristics of the output signal wave configuration, are utilized in conjunction with clock signals at a rate substantially in excess of twice the largest frequency component of the data signal in order to read from a memory a bit-duration waveform sample set representing the desired output signal wave configuration. Predistortion to compensate for anticipated transmission effects is also included in that configuration. In one embodiment, an input data signal is in an NRZ format and is processed for conversion to the biphase, or Manchester, format by a ROM table look-up function addressed jointly by the input signal states and the clock signals.

Abstract: In order to obtain sufficiently long values of T.sub.min and T.sub.w data conversion, and to reduce the dc or the low frequency component, a method for converting a binary data train comprises a first step for dividing the binary data train into a plurality of successive blocks each having M (M being a natural number) bit data, a second step for converting the M bit data into N (N being a natural number, and where N.gtoreq.M+1), and a third step for converting the N bit data in every L (L being a natural number) blocks into J (J being a natural number) bit data.

Abstract: A floating point formatter for changing fixed point serial digital data, such as that received by a seismic data acquisiton system, is disclosed wherein fixed point serial digital data is received and scaled to remove any bias added by preamplification. The scaled data is shifted a predetermined number of bits and a resulting exponent is calculated. The shifted data signal and corresponding exponent are combined and further scaled to permit stacking the data without exceeding the system capacity.