Patents Examined by Charles E. Atkinson
  • Patent number: 5452437
    Abstract: In a data processing system comprising a plurality of processing elements coupled to a network, a method of single-stepping the processing elements aids in debugging the system. Only one processing element at a time is permitted to execute N steps while its data output is coupled to the network. Once it's finished executing, a time period greater than the maximum propagation delay time of the network is permitted to pass before stepping a succeeding processing element N steps. In another embodiment, the outputs of all processing elements to the network are first disabled, then all processing elements are allowed to execute N steps. Next the system is halted, and, one at a time, the data output of each processing element is coupled to the network, allowing sufficient time for each processing element's output to propagate through the network before coupling the output of a succeeding processing element.
    Type: Grant
    Filed: November 18, 1991
    Date of Patent: September 19, 1995
    Assignee: Motorola, Inc.
    Inventors: James M. Richey, George L. Wang
  • Patent number: 5450419
    Abstract: In an error checking apparatus for a serial signal transmission system comprising a plurality of nodes in a centralized control system of various devices such as presses, machine tools, constructing machines, ships, airplanes, unattended conveyer systems and unattended warehouses, plural types of error check codes are added to serial transmission data for each node. The node checks the received data for each of the received error check codes, adds error codes indicative of the result of the error check to the respective error check codes and sends them to a downstream node and a main controller.
    Type: Grant
    Filed: March 20, 1991
    Date of Patent: September 12, 1995
    Assignee: Kabushiki Kaisha Komatsu Seisakusho
    Inventor: Masao Hagiawara
  • Patent number: 5432926
    Abstract: A transaction network in which, in appropriate cases, a transaction is allowed to complete at each node and new work to commence, before all transaction resources at the node actually complete a syncpoint operation. This desirable result is obtained without the risk of unreported database corruption. At each node in response to a prepare to commit syncpoint command from a parent node, the node in question determines if it or any of its descendant nodes can make a unilateral heuristic decision to commit or backout the transaction irrespective of whether or not the final syncpoint command is to commit or backout. Each node informs its parent node that it is reliable or unreliable. Reliable means that neither this node nor any of its descendant nodes can make a unilateral heuristic decision. Unreliable means that this node or one or more of the descendant nodes may make such a unilateral decision.
    Type: Grant
    Filed: December 4, 1992
    Date of Patent: July 11, 1995
    Assignee: International Business Machines Corporation
    Inventors: Andrew P. Citron, James P. Gray
  • Patent number: 5426646
    Abstract: An instantaneous bit-error-rate meter provides an instantaneous, real-time eading of bit-error-rate for digital communications data. Bit-error pulses are input into the meter and are first filtered in a buffer stage to provide input impedance matching and desensitization to pulse variations in amplitude, rise-time and pulse-width. The bit-error pulses are transformed into trigger signals for a timing pulse generator. The timing pulse generator generates timing pulses for each transformed bit-error pulse, and is calibrated to generate timing pulses having a preselected pulse width corresponding to the baud rate of the communications data. An integrator generates a voltage from the timing pulses that is representative of the bit-error-rate as a function of the data transmission rate. The integrated voltage is then displayed on a meter to indicate the bit-error-rate.
    Type: Grant
    Filed: June 25, 1992
    Date of Patent: June 20, 1995
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Robert A. Slack
  • Patent number: 5423029
    Abstract: Disclosed are an apparatus and method for testing a direct memory access ("DMA") controller. The apparatus comprises (1) a virtual control device including a virtual control latch, the virtual control device coupled to a request input of the DMA controller and capable of transmitting a signal to the DMA controller representing a request to transfer data and (2) a virtual input/output ("I/O") device including a virtual I/O latch, an acknowledgement output of the DMA controller coupled to the virtual I/O device, the virtual I/O latch capable of storing the data for use by the DMA controller. In its preferred embodiment, the present invention operates within the confines of IBM-compatible personal computer architecture, allowing DMA controller functionality to be tested directly.
    Type: Grant
    Filed: May 11, 1993
    Date of Patent: June 6, 1995
    Assignee: Dell USA, L.P.
    Inventor: Eric W. Schieve
  • Patent number: 5423025
    Abstract: An error handling and reporting mechanism is capable of taking advantage of sophisticated error analysis performed after clocks have been stopped in response to an error detected in a controller. The controller provides services in a data processing system in response to requests for controller services from a plurality of requestors. The controller includes a plurality of ports for storing requests for controller services. A plurality of servers is coupled to the plurality of ports, and perform separate services associated with the requests for controller services stored in the plurality of ports. An error reporting mechanism is included which is responsive to a detected error in a particular server associated with a request in a particular port, for posting error status in the particular port and causing clock stoppage within a clock stop latency period. An error analysis mechanism analyzes the detected errors during the clock stoppage.
    Type: Grant
    Filed: September 29, 1992
    Date of Patent: June 6, 1995
    Assignee: Amdahl Corporation
    Inventors: Gary S. Goldman, Kent W. Wendorf
  • Patent number: 5421004
    Abstract: Disclosed is a method and system for providing a complex testing framework/scaffold. Also included are testing tools that automate and simplify the testing process. The disclosed design handles networking and task concurrency. The testing scaffold is aimed at being a flexible test case driver that can be used to execute functional verification tests on a single host or large networked system level integration tests involving dozens of hosts. The testing scaffold is designed to meet the requirements of large scale testing environments. The ability to execute these environments similarly allows manipulation of smaller scale environments.
    Type: Grant
    Filed: September 24, 1992
    Date of Patent: May 30, 1995
    Assignee: International Business Machines Corporation
    Inventors: Eric R. Carpenter, Christopher S. Claussen, James O. Cox
  • Patent number: 5418940
    Abstract: A method for detecting partial page writes in pages spanning multiple sectors of a sector organized multiple tracked storage facility in a page oriented, log based transaction management system. During a page write to storage from a buffer, a status bit is embedded at the end of each page sector and a status byte in the last page sector, the status byte is complemented, and each status bit is swapped with a counterpart in the status byte as it is being written out to storage. During a page read in the buffer from storage the status bit values of each page are swapped with their byte counterpart and a partial write detected as a mismatch of the bits in the status byte. Page recovery involves recreating a page from said log upon detection of either a partial sector write or a partial page write by redoing all accessing events on the log between a predetermined point to an end of log including unconditionally redoing of all format page events logged in said interval.
    Type: Grant
    Filed: August 4, 1993
    Date of Patent: May 23, 1995
    Assignee: International Business Machines Corporation
    Inventor: Chandrasekaran Mohan
  • Patent number: 5418941
    Abstract: A dynamic application editor builds new application definition entries for and edits existing application definition entries without a need for a user to have an innate knowledge of the exact method required to invoke applications. Application definition entries describe an application's initiation, execution, procedural command language, macro syntax, and communication capabilities in an application independent manner. The dynamic application editor automatically locates, or accepts user specified existing application definition entries and presents them in a user friendly user interface for the user to edit. The user can view existing application definition entries, cut, copy and paste between application definition entries, edit and delete application definition entries, or browse entire sections of the active application definition file.
    Type: Grant
    Filed: January 28, 1994
    Date of Patent: May 23, 1995
    Assignee: International Business Machines Corporation
    Inventor: Anthony M. Peters
  • Patent number: 5416785
    Abstract: A data communication apparatus having an error correction communication function includes a memory for storing received data, a processor for processing the data stored in the memory, and device for sending out a retransmission request signal for previously received data when next data cannot be stored in the memory.
    Type: Grant
    Filed: March 27, 1992
    Date of Patent: May 16, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventor: Teruyuki Nishii
  • Patent number: 5414833
    Abstract: A system and method provide a security agent, consisting of a monitor and a responder, that respond to a detected security event in a data communications network, by producing and transmitting a security alert message to a network security manager. The alert is a security administration action which includes setting a flag in an existing transmitted protocol frame to indicate a security event has occurred. The security agent detects the transmission of infected programs and data across a high-speed communications network. The security agent includes an adaptive, active monitor using finite state machines, that can be dynamically reprogrammed in the event it becomes necessary to dynamically reconfigure it to provide real time detection of the presence of a suspected offending virus.
    Type: Grant
    Filed: October 27, 1993
    Date of Patent: May 9, 1995
    Assignee: International Business Machines Corporation
    Inventors: Paul C. Hershey, Donald B. Johnson, An V. Le, Stephen M. Matyas, John G. Waclawsky, John D. Wilkins
  • Patent number: 5410686
    Abstract: A scan path debugger isolates and identifies hardware and software faults in a computer system containing scan path logic. A user can readily define what information is to be examined and in what format. The user can toggle between displaying information in data-aligned format or time-aligned format. The user may temporarily suspend control of the scan path debugger to allow the system to be controlled temporarily by a different, unrelated program. The user can check the operation of the system under different microcode files. The user can also save the complete logic state of the system under test, execute one or more scan path debugger instructions while observing the results, restore the saved state, execute the same or different instructions, and observe the results.
    Type: Grant
    Filed: November 1, 1993
    Date of Patent: April 25, 1995
    Assignee: Motorola, Inc.
    Inventor: Thomas J. Kish
  • Patent number: 5410546
    Abstract: The present invention discloses a method and apparatus for computing CRC codes for fixed length page buffers of user data where the user data arrives from a transmission device in variable length packets with the packet contents being out of sequential order. The received data is written to a storage device after being restored to the correct sequential order. The data packets are comprised of a header portion and a data portion. The transmission and compression methods commonly employed by the transmission device dictates that the header portion of each packet follows the data portion. The present invention computes a complete CRC code for the data stored in a page buffer in real time as the packets are received by using several registers for saving intermediate CRC codes and circuitry to combine partial CRC codes for those packet portions received out of order.
    Type: Grant
    Filed: November 1, 1993
    Date of Patent: April 25, 1995
    Assignee: Storage Technology Corporation
    Inventors: Keith G. Boyer, Kenneth R. Burns, Thomas H. Gohl, Terry R. Gottehrer, Bernie R. Marasco, Michael R. Stephens, Robert D. Thompson
  • Patent number: 5406564
    Abstract: A communication line backup system provides a backup line for backing up a communication line which connects first and second subscriber terminals. The communication line backup system includes a first backup unit which is coupled to the first subscriber terminal, a second backup unit which is coupled to the second subscriber terminal, and an integrated services digital network (ISDN) which is coupled to the first and second backup units via ISDN channels. The first and second backup units include a backup part for forming a backup communication channel between the first and second subscriber terminals in response to a failure which is generated on the communication line between the first and second subscriber terminals, and the backup communication channel is formed by at least one channel within the ISDN channels established in the integrated services digital network.
    Type: Grant
    Filed: November 22, 1991
    Date of Patent: April 11, 1995
    Assignee: Fujitsu Limited
    Inventor: Ryoji Okita
  • Patent number: 5406565
    Abstract: A fault tolerant data storage system comprises an array of memory chips having a plurality of rows and columns, each row of memory chips CO to CN having a spare chip CS. Each chip comprises an array of memory locations some of which may be faulty. When simultaneously writing or reading data via parallel data lines DO-DN to the respective chips, a map MAP identifies any chip having a fault in the addressed location (e.g. in the addressed column) and connects the data line to a good location in the spare chip. The logical addresses for the chips are skewed differently for each other as compared with their physical addresses, such that there are not coincident faults in the different chips e.g. only a single chip in a row has a fault in the columns being simultaneously addressed in the respective chips of that row.
    Type: Grant
    Filed: December 31, 1991
    Date of Patent: April 11, 1995
    Assignee: MV Limited
    Inventor: Neal H. MacDonald
  • Patent number: 5404498
    Abstract: Multiplex nodes (11, 12) connected via multiplex transmission lines (A, B and C), a voltage setting unit 16, which changes the voltage of the multiplex transmission line C to a specified value, a controller IC 14, which detects a failure in the multiplex transmission lines A and B, a protective circuit 15, which writes specified address data received from the controller IC 14 and key word data and sends a state signal corresponding to these pieces of data to the voltage setting unit 16, and a controller IC 14 which writes these pieces of data in a predetermined area of the protective circuit 15 are provided. The controller IC 14 detects a failure, the voltage setting unit 16 connects the specified multiplex transmission line C to a power supply or ground according to a state signal received from the protective circuit 15, thus changing the states of the multiplex transmission lines A and B.
    Type: Grant
    Filed: September 15, 1992
    Date of Patent: April 4, 1995
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Motoharu Tanaka, Kyosuke Hashimoto, Kiyoshi Inoue
  • Patent number: 5404502
    Abstract: A technique for integrity error detection in a temporal transaction oriented database system. The database system has records and processing rules. Each record has an effective time. Each processing rule has a range of effective times. The record types include transaction records, master records, shadow master records and snapshot records. Each transaction record or snapshot record is related to one master record and each master record may have a plurality of related transaction and snapshot records. Each snapshot record is a copy of its related master record at a given effective time. On the insertion of one or more backdated transaction records or reversal of one or more existing transaction records the master record is recalculated by replaying from a prior snapshot forward, all processing rules and transaction records, having appropriate effective times.
    Type: Grant
    Filed: February 25, 1993
    Date of Patent: April 4, 1995
    Assignee: Prologic Computer Corporation
    Inventors: Wes Warner, Greg Hope, Paul Oeuvray
  • Patent number: 5404361
    Abstract: The dynamically mapped data storage subsystem generates a two error correction, three error detection code of extent sufficient to cover not only the data but also the corresponding memory address for each data record stored therein. The error correction code is transmitted and stored with the data within the data storage subsystem to ensure the integrity of both the data and its memory address.
    Type: Grant
    Filed: July 27, 1992
    Date of Patent: April 4, 1995
    Assignee: Storage Technology Corporation
    Inventors: Anthony J. Casorso, David P. Haldeman
  • Patent number: 5402426
    Abstract: A check of the observance of prescribed transmission bit rates in an ATM switching equipment occurs using counter devices (RAM1, ALU) working according to the "leaky bucket" principle. These are individually allocated to virtual connections via the switching equipment (VA). The momentary counter readings of these counter devices are respectively decremented by a variable count value only upon arrival of a message cell of the respective virtual connection. This variable count value is proportional to the time difference between the arrival time of the respective message cell and the arrival time of the message cell of the same virtual connection that immediately preceded it. The transmission bit rates determined for the virtual connections are thereby allocated to defined bit rates classes.
    Type: Grant
    Filed: April 5, 1993
    Date of Patent: March 28, 1995
    Assignee: Siemens Aktiengesellschaft
    Inventors: Andreas Foglar, Oliver Von Soosten
  • Patent number: 5398253
    Abstract: A redundant array based data storage system used in computer systems for reducing the amount of time required to modify data records stored in the redundant array. The storage system reduces the number of transmissions between a storage unit within the redundant array and the array controller by incorporating a parity storage unit which is programmed to perform operations necessary to the calculation of a "parity code" which is used for error detection and correction. By integrating the redundancy information generation into the storage unit used to store the parity information, the number of transmissions between various component parts of the system is reduced, and so the amount of time required to perform a "read-modify-write" operation is reduced. Disk-type parity units having more than one read/write head are used to further increase the performance of the storage system by reducing the disk rotational latency time.
    Type: Grant
    Filed: June 2, 1992
    Date of Patent: March 14, 1995
    Assignee: EMC Corporation
    Inventor: David W. Gordon