Abstract: A bit detecting process for identifying binary bit values of digitized signals whose bit amplitudes may be distorted. A digital signal which represents the amplitude of a bit at discrete clock intervals is generated and the difference between a threshold value and the value of the digital signal is determined. A first integral method algorithm or a second second-order difference method algorithm, each of which identifies the binary value of the bit, is selected as a function of the determined difference.

Abstract: In a computer system having fault recoverable capability, there is included a first and second data processing unit (DPU), wherein each of the first and second DPU is executing the same task essentially in parallel. Each DPU comprises a processor, a memory and a protected memory. The protected memory stores system data, such that the system data stored in the protected memory is immune from transient conditions. Also included is a monitor, which is operatively connected to the monitor of the other DPU. The monitor detects the occurrence of an upset to reinitialize the DPU, the DPU being reinitialized to a condition just prior to the occurrence of the upset thus avoiding utilization of any potentially erroneous data, and thereby permitting the DPU to return to its normal processing with valid data.

Abstract: The present invention provides a system for supporting one or more memory requestors (CPU's and I/O DMA) accessing a plurality of DRAM memory banks. The present invention is a multiplexer that functions as a 16-bit slice of the interface between the CPU and a 64-bit slice of DRAM memory array. The invention includes an error correction (ECC) module, a 64-bit DRAM I/O channel, an 8-bit ECC "syndrome" I/O channel and an 8-bit slice of a DMA bus I/O channel. In a write operation, the CPU transmits data through the I/O channel to write the data to the DRAM. Each word is routed by the four-way multiplexer to one of the four memory registers. When the four registers have been filled with data words, the words are assembled into a multiple word burst and sent to the DRAM bank. The data is also passed through an error correction module. For a read operation, DRAM data is latched into the CPU register and transported to the CPU while the DRAM is potentially being accessed for another memory read.

Abstract: A system for determining the log of an element in Galois field GF(2.sup.m) using a small, selectable size table, a finite field multiplier, and a counter. The system allows for a flexible trade-off between speed and integrated circuit area, and applies for any GF(2.sup.m) for all possible m. The system allows for on-the-fly error location determination without the need for storing all possible logs for the GF(2.sup.m) under consideration.

Abstract: An error correction coding method and apparatus which can correct errors generated during the transmission or the storage, or the receiving or the reproducing of a digital image. The error correction coding method according to the present invention comprises the steps of: dividing one image into blocks to prevent the deterioration of the quality of a screen by preventing the generation of burst errors in a header during the transmitting or storing of the image information in the form of digital signals; compressing and coding each divided block into a block code having a header and video information; separating and arranging the compressed and coded header and video information so that successive headers do not overlap; and adding parity data into the separated and arranged header and video information. The apparatus for carrying out the error correction coding method of the present invention comprises an image divider, a data compressor, a parity data insert portion, and a data interleave portion.

Abstract: A test validation process for a semiconductor device applies signals indicating a test mode to the semiconductor device. The device produces output signals and the output signals are read to determine whether the device is in the indicated test mode. The test mode is conducted by operating the device. The output signals are read upon completion of the test mode to determine if the device is still in the indicated test mode. The test validation method is useful for memory chips and particularly Dynamic Random Access Memory, DRAM, devices that are burn-in stress tested.

Abstract: An approach for modeling and solving the problem of fault localization and alarm correlation in large communication networks is presented. Specifically, a new alarm structure is presented along with a general model for representing a communications network. Several specific processing algorithms are provided for solving alarm correlation and fault localization problems in the presence of one or more faults. These algorithms differ in the degree of accuracy achieved in locating a fault, and in the degree of complexity required for implementation.

Abstract: The present invention concerns an integrated circuit (1) comprising a standard cell (4), an application cell (2) and a test cell (3) designed in particular to store or to modify from outside the integrated circuit the value of communication signals passing between the standard cell and the application cell. The standard cell executing instructions provided on an instruction bus (3B4) by a program memory located in the application cell in response to an instruction address carried by an instruction address bus (3A4), the conductors of these buses constituting communication links. The integrated circuit further includes a branching circuit for replacing at least one erroneous instruction from the program memory with a replacement instruction previously stored in the integrated circuit in response to a predetermined state of the communication links.

Abstract: A fault recovery system of a ring network based on a synchronous transport module transmission system, having a fault data writing unit for writing, when an input fault is detected by a node, fault data in a predetermined user byte in an overhead of a frame flowing through both a working line and a protection line running in opposite directions to each other. By detecting the fault data in a supervision node or a node just before the fault position, the supervision node or the node just before the fault position executes a loopback operation.

Abstract: A method for handling data in a plurality of data storage disks having user data sectors and corresponding parity sectors, the method being used when the disks are being operated in a degraded mode wherein data in sectors of an inoperative user data disk are reconstructed from data in the corresponding sectors of the other user data disks and the corresponding parity entry. The reconstructed user data in a user data sector of the inoperative disk is written into the corresponding parity sector in place of the parity entry therein, before any new data is written into the corresponding sector of an operative disk. Information identifying the inoperative disk is written into a specified identification region of the parity disk to indicate that such operation has occurred. The new data is then written into the corresponding sector of the operative disk.

Abstract: An error correction and detection interface between a high speed data channel and a high capacity digital data recording tape system includes a data scrambling and translation scheme which provides an additional layer of error correction to the data as it is recorded. The data scrambling and translation scheme permits the correction of normally uncorrectable large error bursts on digital tape devices.

Abstract: A speech decoder includes a separating circuit, an error correction decoding circuit, an interpolating circuit, and a speech reproducing circuit. The separating circuit separates a code string of a filter parameter, a code string of a parameter associated with a pitch, and a code string of a parameter associated with an index and a gain of a codebook representing an excitation signal of speech from a received code string. The error correction decoding circuit detects a transmission error, which cannot be corrected, in the received code string. When a transmission error which cannot be corrected is detected, the interpolating circuit interpolates between parameters of past and future proper frames, thereby recovering parameters of a current frame. The speech reproducing circuit reproduces a speech signal on the basis of the interpolated parameters and other received codes.

Abstract: Processes for diagnosing boundary scan observed data produced pursuant to boundary scan testing of interconnected circuit devices having three-state bidirectional scan cells. A first set of observed data is produced by controlling each device individually to drive the I/O pins of the device pursuant to a set of test patterns and to scan out observed values, while the three-state bidirectional scan cells of the other devices that are in the high impedance state. The observed values for each device are diagnosed by a process that analyzes the observed data and refers to a pin connection list to isolate as to the pins of each device stuck-at faults, shorted pin faults, open faults between pins, and hardwire faults. A second set of observed data is produced by controlling each device in turn to be a driving device for driving its I/O pins to a first logical state, while the remaining devices are controlled to have their scan cells in the high impedance state and to scan out the signals observed on their I/O pins.

Abstract: In an information signal processing arrangement, an information signal, to which an error detecting code has been added and a part of which other than the error detecting code has been set to a code indicating a predetermined value, is received. Error detection capability is increased by detecting an error in the information signal according to the error detecting code added to the received information signal, and detecting whether or not the part of the information signal set to the predetermined value has changed.

Abstract: A control method and system for preventing the incorrect resetting of a common resource in a multicomputer system comprising a plurality of clusters each having a processor and a common memory which each cluster can access. The method includes steps of storing in a common memory an IPL (initial Program Load) generation ID (Identifier) which is unique to an IPL number of each cluster, setting an acquisition ID and the IPL generation ID in the common resource, when the right to use the common resource in the common memory is acquired, and comparing the IPL generation ID when the faulty cluster stops, with the IPL generation ID set in the common resource, and only when the two IPL generation IDs are equal, resetting the right to use the common resource, when the right to use the common resource which the stopped faulty cluster acquires is reset.

Abstract: A channel adapter monitoring device for tracing OEMI channel data and tags. The device is configurable via a support processor and supervisory microprocessor. A trace array memory stores events identified by a configurable write register. A timer is provided to permit a time stamp entry to be made with each data entry of detected events. The microprocessor can address the trace memory over an MMIO bus and recover the stored data for analysis.

Abstract: The present invention provides an apparatus for monitoring access by a processor in a computing system to certain defined portions of memory. According to the present invention, the user specifies an address or range of address (the "watchword") in memory to be monitored. Each processor contains hardware which monitors outgoing memory references. If the processor attempts to access the defined portion of memory, the present invention generates a signal which is sent back to the issuing processor to inform it that referenced the watchword in memory. The present invention has several applications. In particular however, the present invention can be used in conjunction with debugging software packages as an aid for debugging user software programs on multiprocessing computer systems. Specifically, the present invention can be used to pinpoint which processor in a multiprocessing computer system accessed the watchword portion of memory.

Abstract: Apparatus and method of a data cache which provides for the handling of errors during data copy-back from a data cache write buffer to external memory in a processing system including a processor. When data requested by the processor at an addressed storage location of the data cache is data which is valid, modified, and other than the data requested by the processor, the data is first transferred to the data cache write buffer and then written back to external memory after the requested data is fetched from a memory bus. If an error occurs during the write back of the data from the write buffer to external memory, the data is transferred from the write buffer to the storage location of the data cache originally addressed by the processor before the memory bus is released.

Abstract: In order to prevent a logic circuit including a multi-stage temporary storage array having both valid and invalid state combinations from locking up in an inadvertently entered invalid state and from alternating between invalid state combinations, support logic circuitry is employed which is configured to force the array back to a valid state combination. The forcing operation may be alternatively undertaken immediately or in synchronism with the next succeeding clock pulse following entry into the invalid state combination. A specific valid state combination to be entered following entry into a specific invalid state may be predetermined.

Abstract: The testing system is provided with a diagnostic processing apparatus which is independent from a computer to be tested. The diagnostic processing apparatus operates based on a clock signal which is separate from another clock signal used in the computer to asynchronously issue a fault generation command to the computer. The computer is provided with a register for storing particular fault mode information. The computer is responsive to the issued fault generation command for enabling the stored fault mode information so as to generate an asynchronous pseudo-fault in the computer for testing purpose.