Abstract: A fault tolerant data processing system which provides single fault Byzantine resilience which system uses a number of fault containment regions each of which includes at least one processing element. The fault containment regions of the system are arranged to utilize a shared memory, each of such regions including a portion of the shared memory. The shared memory portion of each fault containment region provides communication with the shared memory portions of each of the other fault containment regions. A shared memory portion includes an encoder for encoding a data byte from the processor in the region into a number of data byte symbols from which the data byte can be reconstructed. The data byte symbols can be stored in the shared memory portion of the region and can be transmitted to one or more of the shared memory portions of the other fault containment regions.

Abstract: A method and apparatus for transmitting data between computers. By determining an optimum time for which a sending computer (10) must set a strobe pulse on a strobe line (54) in order for a receiving computer (30) to be able to read data transmitted, the sending computer can transmit data without the need to poll an acknowledge line (56). The optimum strobe pulse duration is determined by sending a copy of a known pattern of data from the sending computer to the receiving computer using different strobe pulse durations. The receiving computer examines the received pattern of data to determine if an error occurred during transmission. If an error occurred, the sending computer sets the acknowledge line. The optimum hold time is determined to be the shortest hold time for which the sending computer can set the strobe line and the receiving computer can receive the known pattern of data without error.

Abstract: An integrated circuit memory is disclosed which has a parallel test read mode. The memory includes comparators for comparing multiple data words, on a bit-by-bit basis, during the parallel read mode, with the result of the comparison used to enable or disable the output buffers. In test mode, in the event of a failed parallel test comparison, the comparator causes the output buffers to go into a high-impedance state; for a passing parallel test, the actual data state is presented by the output terminals The comparison circuitry is in parallel with the output data path, so that the output data path is not adversely affected by the test circuitry, and so that the access time in test mode is the same as the access time during normal operation (assuming a passing test). The technique may be adapted to wide parallel test schemes.

Abstract: A system includes a system bus having data lines, an acknowledge line, an enable line, and a control line, a data storage device, a controller circuit, and an arrangement coupling the system bus, controller circuit and data storage device. The system bus can carry out a data transfer cycle in which the acknowledge, enable and control lines are actuated and the controller obtains and checks data from the data storage device and supplies it to data lines of the bus, and a verify cycle in which the acknowledge and enable lines are actuated and the control line is deactuated and the controller obtains and checks data from the storage device but does not supply it to the bus. The controller circuit is capable of operating in different modes, in one of which it forcibly sets a false error indication in response to the verify cycle.

Abstract: A boundary-scan circuit for a bidirectional pin of an integrated circuit which uses fewer standard cells if a cell design is considered, or fewer devices if non-standard cell integrated circuits are considered. In either case, the present invention provides the same functionality as provided in of the bidirectional boundary-scan circuits shown in TEEE 1149.1 in a circuit that should be more compact for the same logic family and integration technology.

Abstract: System and method for implementing a distributed state machine in which consistency is maintained despite the failure of any number of processes and communication paths. This machine and method are suitable for systems with modest reliability requirements that do not justify the expense of an extremely fault tolerant, real-time implementation. One process in a network of server processes is chosen as the leader, and that leader is responsible for broadcasting state machine commands to the other processes. The commands are numbered consecutively, and they are recorded in stable storage by the processes. Each command is broadcast through a uniquely numbered ballot or referendum, and each process participating in a ballot may either vote to accept the command or not vote. To be issued, a command must be voted for by a majority of the processes in the system.

Abstract: Test data applied serially from a data input terminal 6 is bypassed by a selecting circuit in modules that are not the object of testing and applied to a scan path in modules that are the object of testing. Test data is applied to the control point of the functional module from the scan path, and test result data provided from the observation point of the functional module and fetched by the scan path. The scan path shifts the fetched test result data to provide serially from a data output terminal 7. Each of selecting means 5a-5c operates in response to the selecting data held in the corresponding selecting data holding/propagating circuits 9a-9c. These selecting data holding/propagating circuits 9a-9c shift and hold selecting data applied serially from a data input terminal 10.

Abstract: A register circuit for scan path testing is provided and comprises a shifting means for shifting the data signal provided to the input means to the output means in response to a clock signal, a controllable connection means for connecting the input means and the output means, and a storage means for storing an enabling signal to enable the connection means. Preferably, the connection means will connect the input means to the output means in response to the enabling signal stored in the storage means when it is not necessary to apply data signals to the shifting means. Therefore, the data signal applied to the input means is provided to the output means without any delay in time via the connection means. As a result, the scan input of the data signal from scan path may be accomplished in a short time.

Abstract: The indicator circuit and method of this invention include an OR circuit having at least two inputs and an output. A signature mode signal input is connected to one input of the OR circuit and a special test mode signal input is connected to a second input of the OR circuit. A logic circuit for providing indicator signals has at least three inputs and at least two outputs. A first input to the logic circuit is connected to the output of the OR circuit. At least one signature address signal is connected to a second input of the logic circuit. The signal indicating the results of the special test mode is connected to a third input of the logic circuit. A first preprogrammed code indicator circuit has an input connected to a first output of the logic circuit and a second preprogrammed code indicator has an input connected to a second output of the logic circuit. The first preprogrammed code indicator may contain, for example, a manufacturer code.

Abstract: The error correction apparatus of this invention maintains a set of pointers which are used to supplement the error correction characters written into the data tracks of the data frame. These pointers consist of indicators stored in a memory that note the location and nature of errors detected in the present data frame or in previous data frames read from the magnetic tape and stored in a buffer memory. The pointer information can be used by the error correction circuitry to determine which tracks typically produce the errors in the data frame. The error correction circuitry can then generate error patterns which can be combined with the data read and reread from the buffer to correct the errors contained therein.

Abstract: A method of testing a source program includes the steps of converting the source program into a load module while dividing statements of the source program associated with access to same data into a plurality of processes, executing the load module while generating access information representing a process defining the data or a process using the data each time the data is accessed, and determining in accordance with said access information whether or not the using process coincides with the defining process or whether or not the use by the using process precedes the definition by the defining process.

Abstract: A VLSI chip debug and production test apparatus that allows an engineer to view the state of hundreds of signals internal to a chip in real-time without probing, which greatly simplifies the isolation of circuit, speed, logic, and microcode bugs. For production testing, it also provides the ability to check the state of these internal signals on a clock-by-clock basis. The mechanism uses a gated XOR-input serial shift-register cell (10), which is stepped out underneath major buses in otherwise unpopulated areas of the chip. Several of these cell groups are linked together to form a scanout path of the desired length, the operation of which is controlled with a single input pin (40). Output data is channeled through a shared output pin (19) to a VLSI tester (16). In the tester (16) the data (19) is checked and accumulated by back-end software over multiple test-loop iterations, and formatted into a readable form.

Abstract: Apparatus is provided to provide a start of frame signal for an incoming bipolar information signal wherein one binary state is alternately encoded with positive and negative level pulses, each of a given duration, and the other binary state is encoded with a zero or reference level. The apparatus responds to said bipolar signal to provide a first series of pulses indicative of positive pulses and a second series of pulses indicative of negative pulses. A clock is provided which operates at a higher frequency than the bipolar signal. Counting means are provided and are responsive to said first and second signals and said clock to provide third and fourth signals each of said signals indicative of the true polarity of the input signal transitions to enable the processing of true data as compared to noise.

Abstract: An electronic printing system with plural hard disks for storing system files, each disk having a bad page table, from the individual disk bad page tables, generating a composite bad page table, providing a common allocation table for controlling allocation of disk file space for storing system files on the disks, and precluding allocating of system files to areas of the disks identified in the composite bad page table as being unusable.

Abstract: A primary transceiver having a driver/receiver initially drives a bus while a secondary transceiver having a driver/receiver receives the signals present on the bus. The system compares the signals received by the secondary driver/receiver and the inputs to the primary driver/receiver. If a difference is detected, the system controller disables the primary driver/receiver and enables the secondary driver/receiver which drives the bus.

Abstract: A test circuit which utilizes a multi-bit impact signature register and an additional register coupled to the output of the signature register and configured as a linear feedback multi-stage shift register. The total number of stages in the two registers is larger than the width of the test data (number of bits) to be input. A single feedback loop couples the output of the last additional register stage back to the first stage of the signature register. Each bit of the test data is input to an exclusive-or element at the input to each stage of the shift register and is exclusive-or-operated sequentially with the result of an exclusive-or operation stored in the preceding stage, and the result of the operation in the last stage is fed from the additional register back to the first-stage exclusive-or- element of the signature register with a delay.

Abstract: A checksum is generated for a bit string in an information packet to be transmitted across a network, by grouping contiguous bit groups in the bit string and, in sequence, processing each of the bit groups to produce a checksum component for each bit group, with the final checksum for the bit string being produced as an accumulation of the checksum components.

Abstract: A method for online editing of compressed digital test vectors in an automated circuit test system, without requiring re-compilation of the test program source code. A method is provided for online editing of vectors compressed in both "indirect" and "keep/toggle (K/T)" compression formats. The test system environment within which the method operates comprises a computer and associated random access memory. The method can be summarized as follows: First, a new vector is created in random access memory (RAM) by storing a copy of the target vector to be modified. Next, pointers in RAM are adjusted to point to the new vector. Then, in order to compensate for K/T compression, the vector following the target vector must be examined to determine whether it requires modification, because of a "ripple effect" caused by modification to the previous vector. If the following vector requires modification, then a copy of the vector must also be created in RAM.

Abstract: On confirming whether or not a matrix switch correctly carries out cross-connection between input and output terminals of the switch in accordance with connection information signals memorized in a memory included in a controller, a cross-connection confirming system makes use of input digital signals which are sent from input lines to output lines through the matrix switch. Connected between the input lines and the input terminals, processing circuits make the input digital signals comprise input terminal codes assigned to the input terminals to which the processing circuits are connected, respectively. Judging circuits are connected to the output terminals to judge whether or not the input terminal codes included in output digital signals are coincident with output signals sent from the memory, respectively.

Abstract: Very large dynamic RAM integrated circuits are rendered self-testing by using on-chip generation of data test patterns with very high fault coverage, and concurrent testing of storage cell subarrays to reduce overall testing time. A test generator, which may operate in combination with the refresh control and timing system of the RAM integrated circuit, supplies the initial data test pattern which is loaded into the storage arrays. The conventional sense amplifier array is modified, and coupled with a gate control system for shifting data in each column of each storage subarray to an adjacent column. Alternatively, a two-terminal bilateral storage cell may be used to effect the shifting function, which effectively converts the memory into a shift register. The use of complementary data test patterns will permit detection of symmetrical faults within storage arrays.