Patents Examined by Charles Garber
  • Patent number: 10211240
    Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: February 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka
  • Patent number: 10203231
    Abstract: An apparatus can include a controller; memory accessible to the controller; a bus operatively coupled to the controller; sensor circuitry operatively coupled to the bus where the sensor circuitry generates measurement information representative of an environmental condition; and where the controller determines codes, each of the codes representative of an individual operational state of the apparatus, and where the controller associates, in the memory, at least a portion of the measurement information with at least one of the codes.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: February 12, 2019
    Assignee: HACH COMPANY
    Inventors: Tom Benson, Dennis Clark, Erik Host-Steen, Scott David Janson, Ken Labar
  • Patent number: 10205074
    Abstract: A semiconductor light emitting device package includes a semiconductor light emitting device including a plurality of electrodes, a circuit board including a mounting region, the semiconductor light emitting device being positioned on the mounting region of the circuit board, and a plurality of electrode pads on the circuit board, the plurality of electrode pads being electrically connected to the plurality of electrodes, wherein each of the plurality of electrode pads includes a first region and a second region, the first region overlapping the mounting region, and the second region excluding the first region, and wherein the plurality of electrode pads is arranged in a shape of rotational symmetry around a pivot point of the mounting region.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jong Sup Song
  • Patent number: 10186452
    Abstract: An asymmetric stair structure includes multiple unit layers and has m regions (m?2). In each of the m regions, a different part of unit layers having an interval of m unit layers each have a portion not covered by an upper adjacent unit layer, so that a stair having a step difference of m unit layers is formed. In arbitrary two of the m regions, the two different parts of unit layers include no repeated unit layers.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: January 22, 2019
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Yao-Yuan Chang
  • Patent number: 10170616
    Abstract: One illustrative method disclosed herein includes, among other things, defining a cavity in a plurality of layers of material positioned above a bottom source/drain (S/D) layer of semiconductor material, wherein a portion of the bottom source/drain (S/D) layer of semiconductor material is exposed at the bottom of the cavity, and performing at least one epi deposition process to form a vertically oriented channel semiconductor structure on the bottom source/drain (S/D) layer of semiconductor material and in the cavity and a top source/drain (S/D) layer of semiconductor material above the vertically oriented channel semiconductor structure. In this example, the method further includes removing at least one of the plurality of layers of material to thereby expose an outer perimeter surface of the vertically oriented channel semiconductor structure and forming a gate structure around the vertically oriented channel semiconductor structure.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Steven J. Bentley, Jody A. Fronheiser
  • Patent number: 10170612
    Abstract: Embodiments include epitaxial semiconductor stacks for reduced defect densities in III-N device layers grown over non-III-N substrates, such as silicon substrates. In embodiments, a metamorphic buffer includes an AlxIn1-xN layer lattice matched to an overlying GaN device layers to reduce thermal mismatch induced defects. Such crystalline epitaxial semiconductor stacks may be device layers for HEMT or LED fabrication, for example. System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits may be provided on the semiconductor stacks in a first area of the silicon substrate while silicon-based CMOS circuitry is provided in a second area of the substrate.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: January 1, 2019
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Niloy Mukherjee, Marko Radosavljevic, Robert S. Chau
  • Patent number: 10166632
    Abstract: A method for aligning a scan laser beam on a wafer include scanning a scan laser beam across a laser beam sensor along a scan line, picking up a scan laser beam, at a first position, using a first optical slit of the laser beam sensor to generate a first electrical pulse, picking up the scan laser beam, at a second position, using a second optical slit of the laser beam sensor to generate a second electrical pulse, picking up the scan laser beam, at a third position, using a third optical slit of the laser beam sensor to generate a third electrical pulse, and determining a spot size and a position of the laser beam based on the first to third electrical pulses.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Russell Budd, Robert Polastre, Paul Andry
  • Patent number: 10170484
    Abstract: In a method of forming a structure with field effect transistors (FETs) having different drive currents, a stack is formed on a substrate. The substrate is a first semiconductor material and the stack includes alternating layers of a second and the first semiconductor material. Recess(es) filled with sacrificial material are formed in certain area(s) of the stack. The stack is patterned into fins and gate-all-around (GAA) FET processing is performed. GAAFET processing includes removing sacrificial gates to form gate openings for GAAFETs and removing the second semiconductor material and any sacrificial material (if present) from the gate openings such that, within each gate opening, nanoshape(s) that extend laterally between source/drain regions remain. Gate openings for GAAFETs where sacrificial material was removed will have fewer nanoshapes than other gate openings. Thus, in the structure, some GAAFETs will have fewer channel regions and, thereby lower drive currents than others.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Min Gyu Sung, Ruilong Xie, Bipul C. Paul
  • Patent number: 10153810
    Abstract: A wireless IC device includes a resin member including first and second surfaces, a substrate including first and second principal surfaces, a coil antenna provided in the resin member, and an RFIC element mounted on the substrate and connected to the coil antenna. The substrate is embedded in the resin member so that the second principal surface is at a second surface side. The coil antenna is defined by first linear conductor patterns on the second surface, first metal posts extending between the first and second surfaces, second metal posts extending between the first and second surfaces, and second linear conductor patterns on the first surface. The RFIC element is disposed in the coil antenna.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: December 11, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Noboru Kato, Makoto Yasutake, Shinichiro Banba
  • Patent number: 10151849
    Abstract: Desirable completion zones can be identified using closure stress in combination with one or more other attributes such as porosity. One computer-based well placement method includes using the computer to: process a seismic data volume to map the spatial distribution of a seismic-based CSS attribute; acquire logs from one or more boreholes in the subsurface region; derive from the logs a relationship between CSS and a minimum in-situ stress; apply the relationship to the CSS attribute map to produce a landing map that highlights desirable completion zones; and place one or more wells in the desirable completion zones. The borehole logs may include direct measurements of minimum in-situ stress (acquired via microfracture testing), sonic tool measurements of P-wave and S-wave velocity, and density tool measurements of bulk formation density.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: December 11, 2018
    Assignee: Chevron U.S.A. Inc.
    Inventors: Mayank Malik, John DeSantis, Fuju Chen, Li Jiang, Saijin Huang, John A. Best
  • Patent number: 10148263
    Abstract: A combined isolator and power switch is disclosed. Such devices are useful in isolating low voltage components such as control compilers from motors or generators working at high voltages. The combined isolator and power switch includes circuits to transfer internal power from its low voltage side to the switch driver circuits on the high voltage side. The combined isolator and switch is compact and easy to use.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: December 4, 2018
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Edward John Coyne, Patrick Martin McGuinness, William Allan Lane, Laurence O'Sullivan
  • Patent number: 10147656
    Abstract: A sizing device in a polishing apparatus for measuring a thickness of a wafer in course of polishing by laser beam interference, includes: a light-source for irradiating the wafer in course of polishing with a laser beam, a light-receiving portion for receiving reflected light from the wafer in course of polishing irradiated with the laser beam from the light-source, a calculating part for calculating a measured value of the thickness of the wafer in course of polishing irradiated with the laser beam based on the reflected light received through the light-receiving portion. The calculating part can calculate the wafer thickness in course of polishing by calculating a measuring error value of the wafer thickness in course of polishing from resistivity of the wafer in course of polishing based on a previously determined correlation between wafer resistivity and measuring error value of wafer thickness, and by compensating the measuring error value.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: December 4, 2018
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Shigeru Oba, Shiro Amagai
  • Patent number: 10146210
    Abstract: What is disclosed is a system for controlling a process, where the process is implemented by a machine system. The system includes a user interface device and a first transceiver coupled to the user interface device. The first transceiver is configured to receive communications from the user interface device and transfer the communications. The system also includes a second transceiver in communication with the first transceiver and configured to transfer power to the first transceiver, receive the communications from the first transceiver, and transfer the communications to control the process implemented by the machine system.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: December 4, 2018
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Wayne H. Wielebski, Michael L. Gasperi, David L. Jensen, David D. Brandt
  • Patent number: 10147640
    Abstract: A method for preparing a porous dielectric is described. In particular, the method includes removing pore-filling agent from pores in a cured porous dielectric layer, wherein the pore-filling agent was back-filled within the pores following the removal of a pore-forming agent during a curing process. The removal of the pore-filling agent includes heating a substrate holder upon which the substrate rests to a holder temperature greater than 100 degrees C. and less than 400 degrees C., and while heating the substrate holder, exposing the substrate to electromagnetic (EM) radiation, wherein the EM radiation includes emission at a wavelengths within the ultraviolet (UV) spectrum, visible spectrum, infrared (IR) spectrum, or microwave spectrum, or combination thereof.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: December 4, 2018
    Assignee: Tokyo Electron Limited
    Inventor: Junjun Liu
  • Patent number: 10141054
    Abstract: A semiconductor device that has a long data retention time during stop of supply of power supply voltage by reducing leakage current due to miniaturization of a semiconductor element. In a structure where charge corresponding to data is held with the use of low off-state current of a transistor containing an oxide semiconductor in its channel formation region, a transistor for reading data and a transistor for storing charge are separately provided, thereby decreasing leakage current flowing through a gate insulating film.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: November 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Munehiro Kozuma, Yoshiyuki Kurokawa
  • Patent number: 10134747
    Abstract: A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and an opening. The pad structure may include a first stepped structure and a second stepped structure located between the first cell structure and the second cell structure. The first stepped structure may include first pads electrically connected to the first and second cell structures and stacked on top of each other, and the second stepped structure may include second pads electrically connected to the first and second cell structures and stacked on top of each other. The circuit may be located under the pad structure. The opening may pass through the pad structure to expose the circuit, and may be located between the first stepped structure and the second stepped structure to insulate the first pads and the second pads from each other.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: November 20, 2018
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10134642
    Abstract: A method of forming a semiconductor device, includes forming a first work function metal and sacrificial layer on an n-type field effect transistor (nFET) and on a p-type field effect transistor (pFET), removing the sacrificial layer and the first work function metal from one of the nFET and the pFET, forming a second work function metal on the one of the nFET and the pFET, a thickness of the second work function metal being substantially the same as a thickness of the first work function metal, and removing the sacrificial layer from the other of the nFET and the pFET.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Alan Anderson, Ruqiang Bao, Paul Charles Jamison, ChoongHyun Lee
  • Patent number: 10134760
    Abstract: A device and method of forming a semiconductor circuit having FinFET devices that have fins of different height is provided. There is a shallow trench isolation layer (STI) on top of a semiconductor substrate. A first Fin Field Effect Transistor (FinFET) comprises a first semiconductor fin including a first layer that extends from a common substrate level through the STI layer to a first height above a top surface of the STI layer. There is a second FinFET comprising a second semiconductor fin including the first layer that extends from the common substrate level through the STI layer to the first height above the top surface of the STI layer, plus a second layer having a second height, plus a third layer having a third height. The second semiconductor fin is taller than the first semiconductor fin.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Terence B. Hook, Xin Miao, Balasubramanian Pranatharthiharan
  • Patent number: 10134849
    Abstract: The present disclosure relates to the technical field of semiconductor technologies and discloses a semiconductor device and a manufacturing method therefor. The method includes forming a growth substrate by providing a substrate structure containing a sacrificial substrate, a first dielectric layer on the sacrificial substrate, and a plurality of recesses formed through the first dielectric layer and into the sacrificial substrate, by forming a buffer layer covering exposes surfaces of the plurality of recesses, by selectively growing a graphene layer on the buffer layer, and by filling the plurality of recesses with a second dielectric layer. The method further includes attaching the growth substrate to a bonding substrate such that the second dielectric layer attaches to the bonding substrate; removing the sacrificial substrate; and removing the buffer layer so as to expose the graphene layer.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: November 20, 2018
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Ming Zhou
  • Patent number: 10134717
    Abstract: According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes at least one chip, and at least one component adjacent to the at least one chip, wherein the at least one chip and the at least one component are molded in a same molding body.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Tsai-Tsung Tsai, Wei-Hung Lin, Ming-Da Cheng