Abstract: A method of forming a semiconductor device, includes forming a first work function metal and sacrificial layer on an n-type field effect transistor (nFET) and on a p-type field effect transistor (pFET), removing the sacrificial layer and the first work function metal from one of the nFET and the pFET, forming a second work function metal on the one of the nFET and the pFET, a thickness of the second work function metal being substantially the same as a thickness of the first work function metal, and removing the sacrificial layer from the other of the nFET and the pFET.

Abstract: Methods for forming fin structures with desired profile and dimensions for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. The methods include a structure reshaping process to reshape a shaped structure, such as a diamond like structure formed on a fin structure. In one embodiment, a method for forming a structure on a substrate includes performing an epitaxial deposition process to form a shaped structure on a fin structure disposed on a substrate, performing a mask layer deposition process to form a mask layer having a first width on the shaped structure, and performing a mask trimming process to trim the mask layer from the first width from a second width.

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

Abstract: A method includes epitaxially depositing source/drains on parallel semiconductor fins having parallel polysilicon gate precursor structures disposed thereon orthogonally to the fins, where two adjacent polysilicon gate precursor structures are joined together and connected at ends thereof by a polysilicon loop portion. The method further includes oxidizing the ends of the polysilicon precursor gate structures, the connecting polysilicon loop portion and any semiconductor nodules that formed on the connecting polysilicon loop portion during the step of epitaxially depositing the source/drains. A structure includes a substrate; a plurality of parallel semiconductor fins disposed on the substrate; a plurality of parallel metal gate structures overlying the plurality of fins and orthogonal to the plurality of fins; and a plurality of source/drain structures disposed on the fins.

Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor includes a device isolation layer provided in a trench of a substrate, the device isolation layer defining a pixel; and a photoelectric conversion device provided in the pixel. The device isolation layer includes a conductive layer, a tunneling layer interposed between the conductive layer and the substrate, and a trap layer interposed between the tunneling layer and the conductive layer.

Abstract: Apparatus and method for use of solid dopant phosphorus and arsenic sources and higher order phosphorus or arsenic implant source material are described. In various implementations, solid phosphorus-comprising or arsenic-comprising materials are provided in the ion source chamber for generation of dimer or tetramer implant species. In other implementations, the ion implantation is augmented by use of a reactor for decomposing gaseous phosphorus-comprising or arsenic-comprising materials to form gas phase dimers and tetramers for ion implantation.

Abstract: LED module chips are assembled by preparing red, green and blue LED substrates in regions partitioned at predetermined intervals. A module substrate has on its upper face a plurality of module chips each having an accommodation region for accommodating the red, green and blue LEDs therein. The front face of the LED substrate on which the LEDs are formed is opposed to the upper face of the module substrate. One of the LEDs is positioned to a predetermined one of the accommodation regions of the module chip, and a laser beam is irradiated from a rear face of the LED substrate to a buffer layer of LED with a condensing point of the laser beam positioned to the buffer layer to peel off the LED from an epitaxy substrate and accommodate the LED into the predetermined accommodation region of the module chip.

Abstract: A semiconductor device includes semiconductor elements and a multilayer substrate including an insulating plate and a circuit board on which the semiconductor elements are arranged that is arranged on the front surface of the insulating plate. The semiconductor device also includes a printed circuit board that is arranged facing a principal surface of the multilayer substrate and in which through holes are formed, as well as conductive posts that are inserted through the through holes and are electrically connected to the semiconductor elements via bonding materials. Furthermore, the semiconductor device includes fuses that are formed between the interior walls of the through holes and the outer peripheral surfaces of the conductive posts, are electrically connected to the printed circuit board via the conductive posts, and melt at a first temperature.

Abstract: A display substrate and a display device are provided. The display substrate includes: plural gate lines each having at least one end provided with plural first electrostatic discharge (ESD) units configured to discharge static electricity in the gate lines. The plural first ESD units have curvatures different from each other. By discharging the static electricity through the plural ESD units, in case one of the ESD units is broken down by electrostatic current, the other ones can continue working.

Abstract: Photodetector including: a waveguide of a waveguide material extending over a substrate; an insulating layer formed over the waveguide and having an opening exposing the waveguide; a photodetector layer formed over the insulating layer and into the opening so as to make contact with the waveguide, the photodetector layer having a first end at the opening and a second end distal from the opening, the photodetector layer being a gradient material of the waveguide material and germanium wherein a waveguide material portion of the gradient material varies from a maximum at the first end to a minimum at the second end and wherein a germanium portion of the gradient material varies from a minimum at the first end to a maximum at the second end; a photodetector region at the second end; and a photodetector layer extension extending at an angle from the photodetector layer at the second end.

Abstract: There is provided an image capturing apparatus including a pixel circuit that generates a pixel signal based on an electric charge generated by photoelectric conversion and a logic circuit that outputs a signal based on the pixel signal. The image capturing apparatus includes a first contact plug connected to a source or a drain of a first transistor constituting the pixel circuit and a second contact plug connected to a source or a drain of a second transistor constituting the logic circuit. A diameter of the first contact plug is smaller than a diameter of the second contact plug.

Abstract: Methods of processing a substrate are provided herein. In some embodiments, a method of processing a substrate disposed in a processing chamber includes: (a) depositing a layer of material on a substrate by exposing the substrate to a first reactive species generated from a remote plasma source and to a first precursor, wherein the first reactive species reacts with the first precursor; and (b) treating all, or substantially all, of the deposited layer of material by exposing the substrate to a plasma generated within the processing chamber from a second plasma source; wherein at least one of the remote plasma source or the second plasma source is pulsed to control periods of depositing and periods of treating.

Abstract: A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.

Abstract: According to one embodiment, a display device includes a first subpixel and a second subpixel. An area, in a plan view, surrounded by a first signal line, a second signal line, a first scanning line, and a second scanning line and including a first pixel electrode is a first area. An area, in a plan view, surrounded by the first signal line, the second signal line, the second scanning line, and a third scanning line and including a second pixel electrode is a second area. The first area has a first distance in the first direction and the second area has a second distance in the first direction. The first distance is greater than the second distance.

Abstract: The present invention for imaging sensor rejuvenation may include a rejuvenation illumination system configured to selectably illuminate a portion of an imaging sensor of an imaging system with illumination suitable for at least partially rejuvenating the imaging sensor degraded by exposure to at least one of extreme ultraviolet light or deep ultraviolet light; and a controller communicatively coupled to the rejuvenation illumination system and configured to direct the rejuvenation illumination system to illuminate the imaging sensor for one or more illumination cycles during a non-imaging state of the imaging sensor.

Abstract: The present disclosure relates to a method of forming an integrated chip having middle-of-the-line (MOL) structures arranged at an irregular pitch, and an associated method of formation. In some embodiments, the integrated chip has a well region with a plurality of source/drain regions. A plurality of gate structures are arranged over the well region at a regular pitch. A plurality of middle-of-the-line (MOL) structures are laterally interleaved between some of the plurality of gate structures and are arranged over the well region at an irregular pitch having a first pitch that is larger than the regular pitch. Since the MOL structures have an irregular pitch with a first pitch that is larger than the regular pitch, one or more of the plurality of gate structures are spaced apart from a closest gate or MOL structure by a space that reduces parasitic capacitance.

Abstract: Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin portions. The fin portions are located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions are oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.

Abstract: To provide a semiconductor device having improved performance. The semiconductor device has a first insulating film formed on the main surface of a semiconductor substrate and a second insulating film formed on the first insulating film. The semiconductor device further has a first opening portion penetrating through the second insulating film and reaching the first insulating film, a second opening portion penetrating through the first insulating film and reaching the semiconductor substrate, and a trench portion formed in the semiconductor substrate. A first opening width of the first opening portion and a second opening width of the second opening portion are greater than a trench width of the trench portion. The trench portion is closed by a third insulating film while leaving a space in the trench portion.

Abstract: An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is delimited within the semiconductive film. A MOS transistor supported within the active zone includes a gate region situated above the active zone. The gate region includes a rectilinear part situated between source and drain regions. The gate region further includes a forked part extending from the rectilinear part. A raised semiconductive region situated above the active zone is positioned at least partly between portions of the forked part. A substrate contact for the transistor is electrically coupled to the raised semiconductive region.

Abstract: A method for manufacturing a light absorption layer of a thin film solar cell in in a method for manufacturing a solar cell transparent electrode may be provided that includes: manufacturing a Ib group element-VIa group element binary system nano particle (s100); manufacturing a binary system nano particle slurry of the Ib group element-VIa group element by adding a solvent, binder and a solution precursor including Va group element to the Ib group element-VIa group element binary system nano particle (s200); distributing and mixing the binary system nano particle slurry of the Ib group element-VIa group element (s300); coating the binary system nano particle slurry of the Ib group element-VIa group element on the rear electrode layer 200 (s400); and performing a heat treatment process on the coated nano particle slurry by supplying the VIa group element (s500).