Abstract: A method and sensor system are disclosed for automatically determining object sensor position and alignment on a host vehicle. A radar sensor detects objects surrounding the host vehicle in normal operation. Static objects are identified as those objects with ground speed approximately equal to zero. Vehicle dynamics sensors provide vehicle longitudinal and lateral velocity and yaw rate data. Measurement data for the static objects—including azimuth angle, range and range rate relative to the sensor—along with the vehicle dynamics data, are used in a recursive geometric calculation which converges on actual values of the radar sensor's two-dimensional position and azimuth alignment angle on the host vehicle.

Abstract: A method of forming a semiconductor device structure comprises forming a mold template comprising trenches within a mold material. Structures are formed within the trenches of the mold template. A wet removal process is performed to remove the mold template, a liquid material of the wet removal process remaining at least in spaces between adjacent pairs of the structures following the wet removal process. A polymer material is formed at least in the spaces between the adjacent pairs of the structures. At least one dry removal process is performed to remove the polymer material from at least the spaces between the adjacent pairs of the structures. Additional methods of forming a semiconductor device structure, and methods of forming capacitor structures are also described.

Abstract: A method for fabricating a LDMOS device, including: forming a semiconductor substrate; forming a dielectric layer atop the semiconductor substrate and an electric conducting layer on the dielectric layer; forming a first photoresist layer on the electric conducting layer; patterning the first photoresist layer through a first mask to form a first opening; etching the electric conducting layer through the first opening; implanting dopants of a first doping type into the semiconductor substrate through the first opening to form a first body region adjacent to the surface of the semiconductor substrate, and a second body region located beneath the first body region; removing the first photoresist layer; etching the electric conducting layer using a second photoresist layer and a second mask.

Abstract: A light receiving device includes: a photoelectric converter including a photodiode and a first pixel electrode disposed on a lower surface of the photodiode; a scanning circuit connected to the first pixel electrode; an electrode pad disposed on a periphery of the scanning circuit; a transparent conductive film extending from an upper surface of the photodiode to the electrode pad, the transparent conductive film having an inclination relative to the upper surface of the photodiode, between the photodiode and the electrode pad; and a sealing resin filled in a space between the photoelectric converter and the scanning circuit, and in a space under the transparent conductive film around the photoelectric converter.

Abstract: A photodiode pixel structure for imaging short wave infrared (SWIR) and visible light built in a planar structure and may be used for one dimensional and two dimensional photodiode arrays. The photodiode arrays may be hybridized to a read out integrated circuit (ROIC), for example, a silicon complementary metal-oxide-semiconductor (CMOS) circuit. The photodiode in each pixel is buried under the surface and does not directly contact the ROIC amplification circuit. Disconnecting the photodiode from the ROIC amplification circuit enables low dark current as well as double correlated sampling in the pixel.

Abstract: A method of embedding SiGe when fabricating a PMOS device is provided. Multiple layers of SiGe layers with different Ge contents may be formed such that the Ge content increases to from bottom layer(s) to middle layer(s), and decreases from the middle layer(s) to top layer(s). In some embodiments, the embedded SiGe can have a SiGe seed layer over a substrate, a first SiGe transition layer over the SiGe seed layer, a SiGe milled layer over the first SiGe transition layer, and a second SiGe transition layer over the SiGe middle layer. The first SiGe transition layer can have a Ge content increasing from a bottom of the first SiGe transition layer to a top of the first SiGe transition layer. The second SiGe transition layer can have a Ge content decreasing from a bottom of the second SiGe transition layer to a top of the second SiGe transition layer.

Abstract: A method of forming a semiconductor device, includes forming first and second SiGe fins on a substrate, forming a protective layer on the first SiGe fin, forming a germanium-containing layer on the second SiGe fin and on the protective layer on the first SiGe fin, and performing an anneal to react the germanium-containing layer with a surface of the second SiGe fin.

Abstract: A compact three-dimensional mask-programmed read-only memory (3D-MPROMC) is disclosed. Its memory array and a decoding stage thereof are formed on a same memory level above the substrate. The memory layers of the memory devices in the memory array have at least two different thicknesses, while the middle layer of the decoding device in the decoding stage has the same thickness as the thinnest memory layer.

Abstract: An object of the present invention is to provide an organic semiconductor composition, which makes it possible to obtain an organic semiconductor film having high mobility and being excellent in film uniformity and heat resistance, and a method for manufacturing an organic semiconductor element. The organic semiconductor composition of the present invention contains an organic semiconductor as Component A and an organic solvent, which is represented by Formula B-1 and has a melting point of equal to or lower than 25° C. and a boiling point of equal to or higher than 150° C. and equal to or lower than 280° C., as Component B, in which an ionization potential of Component A is equal to or higher than 5.1 eV. In the formula, X represents O, S, S?O, O?S?O, or NR, Y1 to Y4 each independently represent NR1 or CR10R11, R, R1, R10, and R11 each independently represent a hydrogen atom or a substituent, and n represents 1 or 2.

Abstract: A molded nanoparticle phosphor for light emitting applications is fabricated by converting a suspension of nanoparticles in a matrix material precursor into a molded nanoparticle phosphor. The matrix material can be any material in which the nanoparticles are dispersible and which is moldable. The molded nanoparticle phosphor can be formed from the matrix material precursor/nanoparticle suspension using any molding technique, such as polymerization molding, contact molding, extrusion molding, injection molding, for example. Once molded, the molded nanoparticle phosphor can be coated with a gas barrier material, for example, a polymer, metal oxide, metal nitride or a glass. The barrier-coated molded nanoparticle phosphor can be utilized in a light-emitting device, such as an LED. For example, the phosphor can be incorporated into the packaging of a standard solid state LED and used to down-convert a portion of the emission of the solid state LED emitter.

Abstract: A power meter includes a voltage sensor input port configured to receive one of single phase AC voltage and three phase AC voltage values. The power meter further includes a current sensor input port configured to receive one of single phase AC current and three phase AC current values. The power meter further includes a bus connector adapted to be coupled to a data bus. The power meter further includes a module connector adapted to be coupled to a module bus. The power meter further includes a timer for producing a digitizing clock. The power meter further includes a microprocessor.

Abstract: Systems and methods for calibrating a volume dimensioner are provided. In one embodiment, a calibrating system comprises a dimensioner and a reference object. The dimensioner is configured to remotely sense characteristics of an object and calculate physical dimensions of the object from the sensed characteristics. The reference object has predefined physical dimensions and an outside surface that exhibits a pattern of reference markings. The dimensioner is configured to be calibrated using the reference object as a basis for comparison.

Abstract: Embodiments include a manufacturing method of making a semiconductor device via multiple stages of alignment bonding and substrate removal. One example is an integrated full-color LED display panel, in which multiple wafers with different arrays of LEDs are integrated onto a host wafer with driver circuitry. The driver circuitry typically is an array of pixel drivers that drive individual LEDs on the display panel.

Abstract: A semiconductor package device includes an electronic device. The electronic device includes a first carrier, a first electronic component, a second carrier, a second electronic component, an encapsulant, and a lens. The first electronic component is disposed on the first carrier. The second carrier defines an aperture and is disposed on the first carrier. The aperture is positioned over the first electronic component and exposes the first electronic component. The second electronic component is disposed on the second carrier. The encapsulant covers the second electronic component. The lens defines a cavity and is disposed on the aperture of the first carrier.

Abstract: A power-module substrate unit having at least one power-module substrate including one ceramic substrate, a circuit layer formed on one surface of the ceramic substrate, and a metal layer formed on another surface of the ceramic substrate, and a heat sink on which the metal layer of the power-module substrate is bonded, in which the metal layer is made of an aluminum plate having purity of 99.99 mass % or higher; the heat sink is made of an aluminum plate having purity of 99.90 mass % or lower; and the circuit layer has a stacking structure of a first layer made of an aluminum plate having the purity of 99.99 mass % or higher and being bonded to the ceramic substrate and a second layer made of the aluminum plate having the purity lower than 99.90 mass % and being bonded on a surface of the first layer.

Abstract: The invention relates to method for manufacturing an electronic device comprising an organic layer (120). According to this method, a stack with a metal layer (130) and an organic layer (120) as first and second outer layers is structured by etching both these outer layers. In one particular embodiment, an additional metal layer (140) may be generated on the outermost metal layer (130) by galvanic growth through a structured isolation 10 layer (150). After removal of said isolation layer (150), the metal (130) may be etched in the openings of the additional metal layer (140). In a further etching step, the organic material (120) may be removed in said openings, too.

Abstract: A method of forming a semiconductor device includes providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, providing at least one N-type metal-oxide semiconductor gate structure being an NZG gate structure having a gate insulation layer over the semiconductor layer and at least one P-type metal-oxide semiconductor gate structure being a PZG gate structure having a gate insulation layer over the semiconductor layer, the NZG and PZG gate structures being electrically separated from each other.

Abstract: A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.

Abstract: Provided is an adhesive composition for multilayer semiconductors. The adhesive composition gives, when applied and dried by heating, an adhesive layer that has approximately no adhesiveness at a temperature lower than 50° C., but, when heated at such a temperature as to less cause damage to semiconductor chips, offers adhesiveness and is rapidly cured thereafter. This adhesive composition for multilayer semiconductors includes a polymerizable compound (A), at least one of a cationic-polymerization initiator (B1) and an anionic-polymerization initiator (B2), and a solvent (C). The polymerizable compound (A) contains 80% by weight or more of an epoxide having a softening point or melting point of 50° C. or higher. The cationic-polymerization initiator (B1) gives a composition having a thermal curing time of 3.5 minutes or longer at 130° C.

Abstract: A method of manufacturing a semiconductor device is provided. The device includes a substrate including a first type region and a second type region, first and second fins protruding from the substrate and separated by a trench. The first fin includes first and second portions of the first type on the first region and a third portion of the second type on the second region. A first gate structure surrounds the second portion and the third portion. A first work function adjusting layer is on the gate insulator layer on the first and second portions. A second work function adjusting layer is on the first work function adjusting layer, the gate insulator layer on the third portion, and the first insulator layer. The device also includes a gate on the second work function adjusting layer, a hardmask layer on the gate, and an interlayer dielectric layer surrounding the gate structure.