Abstract: A circuit protection device is provided and includes a first insulation layer, a second insulation layer, a thermal fuse, a diode, a first exterior electrode pad, a second exterior electrode pad, and a third exterior electrode pad. The second insulation layer is positioned above a top surface of the first insulation layer. The thermal fuse is packaged in the first insulation layer and having a first electrode end and a second electrode end positioned opposite to the first electrode end. The diode is packaged in the second insulation layer and having a first electrode surface and a second electrode surface positioned opposite to the first electrode surface. The first exterior electrode pad is positioned on a bottom surface of the first insulation layer and electrically connected to the first electrode surface and the first electrode end.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a lower substrate including a display area and a non-display area surrounding the display area, wherein a plurality of pixels are formed in the display area. The OLED display also includes an embedded circuit formed in the configured to apply a plurality of signals to the pixels, and an initialization wiring formed in the non-display area and configured to apply an initialization voltage to each of the pixels. The initialization circuit is formed in a layer so as to at least partially overlap with the area of the embedded circuit.

Abstract: A method for fabrication of a device (206) from a wafer (170) of semiconductor material includes locally thinning the wafer in an area of the device to a predefined thickness by removing the semiconductor material from at least a first side of the wafer using a wet etching process, and etching through the thinned wafer in the area of the device so as to release a moving part (202) of the device. Other methods and systems for fabrication are also described.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are disclosed. The method includes forming a trench, in a vertical direction of a semiconductor substrate having a plurality of photoelectric converting elements arranged on the semiconductor device, at positions between the photoelectric converting elements that are next to each other, forming a first conductive-material layer in and above the trench by implanting a first conductive material into the trench after an oxide film is formed on an inner wall of the trench, forming a first conductor by removing the first conductive-material layer excluding a first conductive portion of the first conductive-material layer implanted into the trench, and forming an upper gate electrode above the first conductor, the upper gate electrode configured to be conductive with the first conductor. The semiconductor device includes a semiconductor substrate, an image sensor, a trench, a first conductor, and an upper gate electrode.

Abstract: A semiconductor device comprises a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further comprises a first isolation layer on the first surface of the semiconductor body, and an electrostatic discharge protection structure on the first isolation layer. The electrostatic discharge protection structure has a first terminal and a second terminal. The semiconductor device further comprises a heat dissipation structure, which has a first end in contact with the electrostatic discharge protection structure and a second end which is in direct contact to an electrically isolating region.

Abstract: A recess is formed by partially etching a silicon carbide substrate. A mask layer is formed on the silicon carbide substrate by means of photolithography using the recess as an alignment mark. An impurity is implanted into the silicon carbide substrate using the mask layer. The silicon carbide substrate is annealed. After the annealing, a first electrode layer is deposited on the silicon carbide substrate. The first electrode layer is patterned by means of photolithography using the recess in the silicon carbide substrate as an alignment mark.

Abstract: Methods for depositing metal layers, and more specifically TaN layers, using CVD and ALD techniques are provided. In one or more embodiments, the method includes sequentially exposing a substrate to a metal precursor, or more specifically a tantalum precursor, followed by a high frequency plasma.

Abstract: An OLED device is disclosed. The device includes a substrate defined to have a first active area and a dummy area. First electrodes are formed on the substrate, and a first bank pattern is formed to overlap with edges of each first electrode and to expose a part of an upper surface of each first electrode. A second bank pattern is formed on the first bank pattern within the first active area, and a third bank pattern is formed on the first bank pattern within the dummy area in the same layer as the second bank pattern. The second bank pattern is formed to have a larger width than that of the third bank pattern. As such, an organic emission layer can be evenly formed in the active area.

Abstract: Provided is a method of manufacturing a semiconductor device, which is capable of increasing the controllability of the concentration of carbon in a film by increasing the yield when a boron carbonitride film or a boron nitride film is formed. The method includes forming a film containing boron, carbon and nitrogen or a film containing boron and nitrogen on the substrate by performing, a predetermined number of times, a cycle including supplying a source gas consisting of boron and a halogen element to a substrate and supplying a reactive gas consisting of carbon, nitrogen and hydrogen to the substrate.

Abstract: A method for the fabrication of thin-film transistors together with micromechanical components, other active electrical components or both on an amorphous or polycrystalline substrate includes disposing the thin-film transistors and the other components on different areas of the substrate.

Abstract: A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface.

Abstract: Provided are methods of forming field effect transistors. The method includes preparing a substrate with a first region and a second region, forming fin portions on the first and second regions, each of the fin portions protruding from the substrate and having a first width, forming a first mask pattern to expose the fin portions on the first region and cover the fin portions on the second region, and changing widths of the fin portions provided on the first region.

Abstract: Provided is a wireless module whose size can be made smaller. The wireless module includes: a first substrate on which an antenna is mounted; a second substrate which opposes the first substrate and on which an electronic component is mounted; and a plurality of electric conductors which connect the first substrate and the second substrate and which transmit a signal between the antenna and the electronic components, wherein the plurality of electric conductors are disposed between the first substrate and the second substrate in series in a substantially vertical direction with respect to mounting surfaces of the first substrate and the second substrate.

Abstract: A first sacrificial gate structure is formed over a first fin stack and a second sacrificial gate structure is formed over a second fin stack. The first and second fin stacks include alternating layers of a III-V compound semiconductor material portion and a germanium material portion. Source/drain structures are formed adjacent the first and second sacrificial gate structures. The first sacrificial structure is removed to provide a first gate cavity. Exposed III-V compound semiconductor portions in the first gate cavity are removed to suspend a portion of each germanium material portion. A first functional gate structure is formed in the first gate cavity. The second sacrificial structure is removed to provide a second gate cavity. Exposed germanium material portions are removed to suspend a portion of each III-V compound semiconductor material portion of the second fin stack. A second functional gate structure is formed in the second gate cavity.

Abstract: According to one embodiment, in a pattern inspection method, a guide pattern is formed on a substrate. A block copolymer is applied on the guide pattern. Thereafter, the substrate is heated according to a predetermined heating condition to promote directed self assembly corresponding to a shape of the guide pattern with respect to the block copolymer. Further, the substrate is observed by a fluorescence microscope during heating or after heating the substrate.

Abstract: Embodiments of the invention are directed to a transparent up-conversion device having two transparent electrodes. In embodiments of the invention, the up-conversion device comprises a stack of layers proceeding from a transparent substrate including an anode, a hole blocking layer, an IR sensitizing layer, a hole transport layer, a light emitting layer, an electron transport layer, a cathode, and an antireflective layer. In an embodiment of the invention, the up-conversion device includes an IR pass visible blocking layer.

Abstract: To provide a method for manufacturing a semiconductor device including an oxide semiconductor film having conductivity, or a method for manufacturing a semiconductor device including an oxide semiconductor film having a light-transmitting property and conductivity. The method for manufacturing a semiconductor device includes the steps of forming an oxide semiconductor film over a first insulating film, performing first heat treatment in an atmosphere where oxygen contained in the oxide semiconductor film is released, and performing second heat treatment in a hydrogen-containing atmosphere, so that an oxide semiconductor film having conductivity is formed.

Abstract: A method includes forming a plurality of trenches to define a fin, forming a first layer of insulating material in the trenches, forming a sidewall spacer on opposite sides of the fin above an upper surface of the first layer, removing the first layer and performing a fin-trimming etching process to define a plurality of increased-size trenches. The method also includes forming a first oxidation-blocking layer of insulating material in the increased-size trenches, forming a second layer of insulating material above the oxidation-blocking layer, and performing a thermal anneal process to convert at least a part of the portion of the fin that is in contact with the second layer of insulating material into an oxide fin isolation region.

Abstract: A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively.

Abstract: Provided is a semiconductor wafer evaluation method of performing an evaluation of electrical characteristics of a semiconductor wafer by bringing mercury into contact with a surface of the semiconductor wafer, the method including using a probe constituted of a fixed electrode having a tip end portion and a transparent covering portion that covers a portion other than the tip end portion of the fixed electrode, the fixed electrode being made of a metal having stronger wettability with respect to the mercury than the semiconductor wafer and the covering portion, and measuring the electrical characteristics by attaching the mercury to the tip end portion of the fixed electrode and then bringing the mercury into contact with the surface of the semiconductor wafer.