Patents Examined by Charles Garber
-
Patent number: 9664966Abstract: A method of manufacturing a display device, the method including: forming, on a first surface of a substrate, a gate line and a gate electrode; forming a first dielectric layer on the gate line and the gate electrode; forming a data line, a source electrode and a drain electrode on the first dielectric layer; forming a black matrix layer on the first dielectric layer, the data line, the source electrode, and the drain electrode; radiating ultraviolet light on a second surface of the substrate opposing the first surface, the ultraviolet light developing exposed parts of the black matrix layer to form a black matrix pattern; and etching the first dielectric layer using the black matrix pattern as an etching mask to respectively form a first dielectric pattern on the gate line and a gate dielectric pattern on the gate electrode.Type: GrantFiled: April 10, 2015Date of Patent: May 30, 2017Assignee: Samsung Display Co., Ltd.Inventors: SeungBo Shim, Jeong Won Kim, Kwangwoo Park, Jinho Ju
-
Patent number: 9666677Abstract: A method for manufacturing a laser diode device includes providing a substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The epitaxial material is patterned to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. Each of the plurality of dice are transferred to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch.Type: GrantFiled: December 23, 2014Date of Patent: May 30, 2017Assignee: Soraa Laser Diode, Inc.Inventors: James W. Raring, Melvin McLaurin, Alexander Sztein, Po Shan Hsu
-
Patent number: 9666473Abstract: A semiconductor device and a manufacturing method thereof are disclosed. The semiconductor device includes a silicon substrate, a spacer, a doped region, and a deep trench isolation (DTI). The silicon substrate has a deep trench. The spacer is formed on an upper portion of the sidewall of the deep trench. The doped region is formed on a lower portion of the sidewall of the deep trench. The deep trench isolation is formed in the deep trench.Type: GrantFiled: May 20, 2016Date of Patent: May 30, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventor: Ching-Hung Kao
-
Patent number: 9659774Abstract: A method for introducing impurity into a semiconductor substrate includes bringing a solution containing a compound of an impurity element into contact with a primary surface of a semiconductor substrate; and irradiating the primary surface of the semiconductor substrate with a laser beam through the solution to raise a temperature of the primary surface of the semiconductor substrate at a position irradiated by the laser beam so as to dope the impurity element into the semiconductor substrate. The laser beam irradiation is performed such that the raised temperature does not return to room temperature until a prescribed dose of the impurity element is caused to be doped into the semiconductor substrate.Type: GrantFiled: June 3, 2015Date of Patent: May 23, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Haruo Nakazawa, Kenichi Iguchi, Masaaki Ogino
-
Patent number: 9659996Abstract: According to one embodiment, a magnetic memory element comprises a first magnetic unit, a second magnetic unit, a first insulating unit, a first electrode, a second electrode, and a third electrode. The first magnetic unit includes a plurality of magnetic domains. The second magnetic unit includes a first region and a second region. The first region includes a conductive material. The second region includes an insulating material. At least one of the first region or the second region is magnetic. The first insulating unit is provided between the first magnetic unit and the second magnetic unit. The first electrode and the second electrode are connected to the first magnetic unit. A part of the second magnetic unit and a part of the first insulating unit are provided between the third electrode and a part of the first magnetic unit.Type: GrantFiled: October 23, 2015Date of Patent: May 23, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Takuya Shimada, Hirofumi Morise, Shiho Nakamura, Tsuyoshi Kondo, Yasuaki Ootera, Michael Arnaud Quinsat
-
Patent number: 9653336Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices made thereby, that utilize a film assist mold process.Type: GrantFiled: March 17, 2016Date of Patent: May 16, 2017Inventors: Yi Seul Han, Jae Beum Shim, Byong Jin Kim, In Bae Park
-
Patent number: 9653642Abstract: A method for manufacturing a display panel comprising light emitting device including micro LEDs includes providing multiple donor wafers having a surface region and forming an epitaxial material overlying the surface region. The epitaxial material includes an n-type region, an active region comprising at least one light emitting layer overlying the n-type region, and a p-type region overlying the active layer region. The multiple donor wafers are configured to emit different color emissions. The epitaxial material on the multiple donor wafers is patterned to form a plurality of dice, characterized by a first pitch between a pair of dice less than a design width. At least some of the dice are selectively transferred from the multiple donor wafers to a common carrier wafer such that the carrier wafer is configured with different color emitting LEDs. The different color LEDs could comprise red-green-blue LEDs to form a RGB display panel.Type: GrantFiled: July 13, 2016Date of Patent: May 16, 2017Assignee: SORAA LASER DIODE, INC.Inventors: James W. Raring, Melvin McLaurin, Alexander Sztein, Po Shan Hsu
-
Patent number: 9653462Abstract: A semiconductor device includes a fin type active pattern extended in a first direction and disposed on a substrate. A first gate electrode and a second gate electrode are disposed on the fin type active pattern. The first gate electrode and the second gate electrode are extended in a second direction crossing the first direction. A trench region is disposed in the fin type active pattern and between the first gate electrode and the second gate electrode. A source/drain region is disposed on a surface of the trench region. A source/drain contact is disposed on the source/drain region. The source/drain contact includes a first insulating layer disposed on the source/drain region and a metal oxide layer disposed on the first insulating layer.Type: GrantFiled: December 26, 2014Date of Patent: May 16, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Dae Suk, Kang-Ill Seo
-
Patent number: 9646911Abstract: A composite substrate configured for epitaxial growth of a semiconductor layer thereon is provided. The composite substrate includes multiple substrate layers formed of different materials having different thermal expansion coefficients. The thermal expansion coefficient of the material of the semiconductor layer can be between the thermal coefficients of the substrate layer materials. The composite substrate can have a composite thermal expansion coefficient configured to reduce an amount of tensile stress within the semiconductor layer at room temperature and/or an operating temperature for a device fabricated using the heterostructure.Type: GrantFiled: April 10, 2015Date of Patent: May 9, 2017Assignee: Sensor Electronic Technology, Inc.Inventors: Michael Shur, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska
-
Patent number: 9647088Abstract: The invention provides a manufacturing method of a low temperature polysilicon thin film transistor, including: providing a substrate; forming a buffer layer on the substrate; simultaneously forming a polysilicon layer and a photoresist layer on the buffer layer; implanting ions into a source region and a drain region; removing the photoresist layer; forming an insulating layer on the polysilicon layer; forming a gate electrode on the insulating layer; and forming a passivation layer on the insulating layer. The passivation layer covers the gate electrode. The invention can only use one time of mask process and one time of ion implantation process to complete the manufacturing processing of the polysilicon layer, the manufacturing process can be simplified and therefore the cost of process is reduced and the productivity is improved.Type: GrantFiled: January 16, 2015Date of Patent: May 9, 2017Assignee: Shenzhen China Star Optoelectronics Technology Co., LtdInventors: Gui Chen, Jingfeng Xue, Xin Zhang
-
Patent number: 9647033Abstract: Methods of manufacturing a magnetic memory device including forming a lower magnetic layer, a tunnel barrier layer, and an upper magnetic layer on a substrate, forming a magnetic tunnel junction (MTJ) pattern by patterning the lower magnetic layer, the tunnel barrier layer, and the upper magnetic layer, forming a first insulating layer exposing an upper surface of the MTJ pattern, forming a polymer pattern on the exposed upper surface of the MTJ pattern, forming a second insulating layer exposing an upper surface of the polymer pattern, removing the polymer pattern to form a cavity in the second insulating layer, the cavity exposing the upper surface of the MTJ pattern, and forming a metal line by filling the cavity with a conductive metal.Type: GrantFiled: December 10, 2015Date of Patent: May 9, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hye Min Shin, Jun Ho Park, Dae Eun Jeong
-
Patent number: 9646860Abstract: Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes means for monitoring an alignment of a first wafer and a second wafer, and means for adjusting a position of the second wafer. The alignment system includes means for feeding back a relative position of the first wafer and the second wafer to the means for adjusting the position of the second wafer before and during a bonding process for the first wafer and the second wafer.Type: GrantFiled: August 9, 2013Date of Patent: May 9, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Xin-Hua Huang, Xiaomeng Chen, Ping-Yin Liu, Lan-Lin Chao
-
Patent number: 9646829Abstract: A method for manufacturing a highly reliable semiconductor device with less change in threshold voltage is provided. An insulating film from which oxygen can be released by heating is formed in contact with an oxide semiconductor layer, and light irradiation treatment is performed on a gate electrode or a metal layer formed in a region which overlaps with the gate electrode, so that oxygen is added into the oxide semiconductor layer in a region which overlaps with the gate electrode. Accordingly, oxygen vacancies or interface states in the oxide semiconductor layer in a region which overlaps with the gate electrode can be reduced.Type: GrantFiled: February 23, 2012Date of Patent: May 9, 2017Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shinji Ohno, Yuichi Sato, Junichi Koezuka
-
Patent number: 9640574Abstract: A process of forming optical sensors includes sealing an imaging portion of each of a plurality of optical sensors on a sensor wafer with a transparent material. The operation of sealing leaves a bonding portion of each of the optical sensors exposed. The process further includes cutting the wafer into a plurality of image sensor dies after sealing the optical sensors such that each image sensor die includes one of the optical sensors sealed with a corresponding portion of the transparent material.Type: GrantFiled: February 17, 2011Date of Patent: May 2, 2017Assignee: STMICROELECTRONICS PTE. LTD.Inventors: Jing-En Luan, Junyong Chen
-
Patent number: 9634145Abstract: A transistor includes a substrate and an electrically conductive gate over the substrate. The gate has a gate length. A source electrode and a drain electrode are over the substrate, and are separated by a gap defining a channel region. The channel region has a channel length that is less than the gate length. A semiconductor layer is in contact with the source electrode and drain electrode. A dielectric stack is in contact with the gate, and has first, second, and third regions. The first region is in contact with the semiconductor layer in the channel region, and has a first thickness. The second region is adjacent to the first region that has the first thickness. The third region is adjacent to the second region, and has a thickness that is greater than the first thickness.Type: GrantFiled: October 29, 2014Date of Patent: April 25, 2017Assignee: EASTMAN KODAK COMPANYInventors: Carolyn Rae Ellinger, Shelby Forrester Nelson
-
Patent number: 9633908Abstract: A method of forming a semiconductor structure is provided. The method includes providing a substrate comprising, from bottom to top, a handle substrate, an insulator layer and a germanium-containing layer. Next, hard mask material portions having an opening that exposes a portion of the germanium-containing layer are formed on the substrate. An etch is then performed through the opening to provide an undercut region in the germanium-containing layer. A III-V compound semiconductor material is grown within the undercut region by utilizing an aspect ratio trapping growth process. Next, portions of the III-V compound semiconductor material are removed to provide III-V compound semiconductor material portions located between remaining portions of the germanium-containing layer.Type: GrantFiled: June 16, 2015Date of Patent: April 25, 2017Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
-
Patent number: 9634181Abstract: In a method according to embodiments of the invention, a III-nitride layer is grown on a growth substrate. The III-nitride layer is connected to a host substrate. The growth substrate is removed. The growth substrate is a non-III-nitride material. The growth substrate has an in-plane lattice constant a substrate. The III-nitride layer has a bulk lattice constant a layer. In some embodiments, [(|a substrate?a layer|)/asubstrate]*100% is no more than 1%.Type: GrantFiled: October 26, 2011Date of Patent: April 25, 2017Assignee: KONINKLIJKE PHILIPS N.V.Inventors: Nathan Frederick Gardner, Melvin Barker McLaurin, Michael Jason Grundmann, Werner Goetz, John Edward Epler, Qi Ye
-
Patent number: 9634015Abstract: An antifuse-type one time programming memory cell has following structures. A first doped region, a second doped region, a third doped region and a fourth doped region are formed in a well region. A gate oxide layer covers a surface of the well region. A first gate is formed on the gate oxide layer and spanned over the first doped region and the second doped region. The first gate is connected with a word line. A second gate is formed on the gate oxide layer and spanned over the third doped region and the fourth doped region. The second gate is connected with the word line. A third gate is formed on the gate oxide layer and spanned over the second doped region and the third doped region. The third gate is connected with an antifuse control line.Type: GrantFiled: December 28, 2015Date of Patent: April 25, 2017Assignee: EMEMORY TECHNOLOGY INC.Inventors: Wei-Zhe Wong, Meng-Yi Wu, Ping-Lung Ho
-
Patent number: 9630835Abstract: A MEMS device is formed by applying a lower polymer film to top surfaces of a common substrate containing a plurality of MEMS devices, and patterning the lower polymer film to form a headspace wall surrounding components of each MEMS device. Subsequently an upper polymer dry film is applied to top surfaces of the headspace walls and patterned to form headspace caps which isolate the components of each MEMS device. Subsequently, the MEMS devices are singulated to provide separate MEMS devices.Type: GrantFiled: August 25, 2014Date of Patent: April 25, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Stuart M. Jacobsen, Wei-Yan Shih
-
Patent number: 9633874Abstract: A warpage reshaping apparatus to reshape a warpage profile of a package substrate is disclosed. The warpage reshaping apparatus includes a metal boat, a plurality of planar boards and a plurality of spring-loaded clips. The metal boat includes a plurality of cavities. Package substrates are placed into each of the cavities. Each of the plurality of planar boards is disposed on a respective one of the package substrates. The spring-loaded clips have a first portion coupled to the metal boat and having a second portion biased against a respective one of the planar boards such that each planar board is biased against its respective package substrate. In addition to that, a method to operate the warpage reshaping apparatus is also disclosed and the manner in which the warpage reshaping apparatus changes the warpage profile of the package substrate is also disclosed.Type: GrantFiled: July 17, 2014Date of Patent: April 25, 2017Assignee: Altera CorporationInventors: Chew Ching Lim, Ken Beng Lim