Abstract: Embodiments of the invention are directed to a method of separating a wafer of light emitting devices. The method includes scribing a first groove on a dicing street on the wafer and checking the alignment of the wafer using a location of the first groove relative to a feature on the wafer. After checking the alignment, a second groove is scribed on the dicing street.

Abstract: A radiation-emitting semiconductor chip having a semiconductor body including a semi-conductor layer sequence having an active region that generates radiation, a first semiconductor layer of a first conductor, and a second semiconductor layer of a second conductor different from the first conductor, and having a carrier on which the semiconductor body is arranged, wherein a pn junction is formed in the carrier, the carrier has a first contact and a second contact on a rear side facing away from the semiconductor body, and the active area and the pn junction connect to one another in antiparallel in relation to the forward-bias direction by the first contact and the second contact.

Abstract: The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.

Abstract: An integrated circuit and method has an isolated well with an improved isolated well contact. The well contact diffusion is isolated from a device diffusion of opposite conductivity type within the isolated well by an isolation transistor gate.

Abstract: In some aspects, methods of forming a metal chalcogenide thin film are provided. According to some methods, a metal chalcogenide thin film is deposited on a substrate in a reaction space in a cyclical deposition process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase chalcogen reactant. In some aspects, methods of forming three-dimensional structure on a substrate surface are provided. In some embodiments, the method includes forming a metal chalcogenide dielectric layer between a substrate and a conductive layer. In some embodiments the method includes forming an MIS-type contact structure including a metal chalcogenide dielectric layer.

Abstract: A method for manufacturing a thin-film transistor includes: forming a first metal layer of a pattern including a gate on a substrate through pattern formation operations; forming a gate insulation layer on the substrate and the first metal layer and forming an oxide semiconductor layer, of which an orthogonal projection is cast on the gate, on the gate insulation layer within a thin-film transistor area and an etch stop layer on the oxide semiconductor layer, in which two etching operations are applied to the patternized oxide semiconductor layer and etch stop layer; forming a patternized second metal layer on the thin-film transistor area and an exposed portion of the gate insulation layer, forming a patternized insulation protection layer on the substrate and the patternized second metal layer, and forming a patternized pixel electrode on the insulation protection layer.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a film containing a predetermined element and carbon on a substrate by performing a cycle a predetermined number of times. The cycle includes supplying a first process gas containing the predetermined element and a halogen element to the substrate; supplying a second process gas containing carbon and nitrogen to the substrate; supplying a third process gas containing carbon to the substrate; and supplying a fourth process gas to the substrate, the fourth process gas being different from each of the first to the third process gases.

Abstract: A microstructure body according to an embodiment includes a stacked body. The stacked body includes a plurality of unit structure bodies stacked periodically along a first direction. A configuration of an end portion of the stacked body in a second direction is a stairstep configuration including terraces formed every unit structure body. The second direction intersects the first direction. A first distance in a third direction between end edges of two of the unit structure bodies facing the third direction is shorter than a second distance in the second direction between end edges of the two of the unit structure bodies facing the second direction. The third direction intersects both the first direction and the second direction.

Abstract: A structured substrate configured for epitaxial growth of a semiconductor layer thereon is provided. Structures can be formed on a side of the structured substrate opposite that of the growth surface for the semiconductor layer. The structures can include cavities and/or pillars, which can be patterned, randomly distributed, and/or the like. The structures can be configured to modify one or more properties of the substrate material such that growth of a higher quality semiconductor layer can be obtained.

Abstract: An image sensing device may include an interconnect layer and grid array contacts carried by the interconnect layer, and an image sensor IC carried by the interconnect layer and coupled to the grid array contacts, the image sensor IC having an image sensing surface. The image sensing device may include a transparent plate carried by the image sensor IC and aligned with the image sensing surface, and a cap carried by the interconnect layer and having an opening aligned with the image sensing surface. The cap may have an upper wall spaced above the interconnect layer and the image sensor IC to define an internal cavity, and the cap may define an air vent coupled to the internal cavity.

Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

Abstract: A method for forming chamferless vias comprises receiving a substrate stack comprising a hard mask layer, a porous dielectric layer underlying the hard mask layer, a cap layer underlying the dielectric layer, and a conductive layer underlying the cap layer. The hard mask layer is opened to reveal a portion of the dielectric layer. A plurality of vias are opened to extend through the dielectric layer and the cap layer. A pore filling material comprising a thermally decomposable polymer is deposited into the vias. The pore filling material in the vias is hardened and driven into the pores of the dielectric layer adjacent to the vias by an annealing process. The hard mask layer is removed. A trench is patterned and etched coincident with the vias. A dissipation process is conducted to remove the pore filling material.

Abstract: A thin film transistor and a preparation method therefor, an array substrate and a display apparatus. The thin film transistor comprises an active layer (4), an etched barrier layer (5) disposed on the active layer (4), and a source and drain (6) disposed on the etched barrier layer (5). The source and drain (6) are disposed on a same layer in a spaced manner. First via holes (7) are formed in the etched barrier layer (5), second via holes (8) are formed in positions in the active layer (4) corresponding to the first via holes (7). The source and drain (6) are connected to the active layer (4) through the first via holes (7) formed in the etched barrier layer (5) and the second via holes (8) formed in the active layer (4).

Abstract: The present invention provides a low temperature polysilicon thin film transistor and a fabricating method thereof. According to the method, a laser annealing process is performed to a remained portion of a a-Si layer on a substrate to form a first lightly doped drain (LDD) terminal, a second LDD terminal, a first phosphor material structure and a second phosphor material structure. A gate metal layer is then formed on the remained portion of the a-Si layer. A source metal layer and a drain metal layer are formed on the first doped layer and the second doped layer located at opposite sides of the gate metal layer, respectively. The present invention use the high temperature of the laser annealing process to perform a heat diffusion of phosphor material to form the LDD terminal and the phosphor material structure, the times of photomasks are used is reduced, and the process is simplified.

Abstract: An image sensor may include a device isolation structure defining a plurality of pixel regions in a substrate and a photoelectric conversion element formed in each of the pixel regions. The device isolation structure may include an insulating gapfill layer extending from an upper portion to a lower portion of the device isolation structure, a spacer provided at the upper portion of the device isolation structure and interposed between the insulating gapfill layer and the substrate, and a lower impurity region provided at the lower portion of the device isolation structure and interposed between the insulating gapfill layer and the substrate.

Abstract: A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an adjacent singulation site. The carrier has a top surface configured to receive a semiconductor substrate thereon. Each of the plurality of singulation sites includes a deformable portion and at least one vacuum hole. The at least one vacuum hole and the deformable portion is configured to form a seal around the at least one vacuum holes when a force is applied. The present disclosure further includes a method of manufacturing semiconductor devices, especially for a singulation process.

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.

Abstract: A method is provided for producing an electrically conductive contact on a rear face and/or front face of a solar cell. The method interconnects solar cells in a cost-effective manner and ensures that cell damage, which leads to a reduction in power, is avoided. The rear face and/or front face of the solar cell is treated in the region of the contact and, after the treatment in the region, a pasty adhesive or an adhesive tape is applied in strips.

Abstract: Decrease of the output voltage of the logic circuit is inhibited by raising the gate voltage using a capacitor. In a first transistor, a drain and a gate are electrically connected to a first wiring, and a source is electrically connected to a first node. In a second transistor, a drain is electrically connected to the first node, a source is electrically connected to a second wiring, and a gate is electrically connected to a second node. In a third transistor, a drain is electrically connected to a third wiring, and a source is electrically connected to a third node, and a gate is electrically connected to the first node. In a fourth transistor, a drain is electrically connected to the third node, a source is electrically connected to a fourth wiring, and a gate is electrically connected to the second node. In a capacitor, one electrode is electrically connected to the first node, and the other electrode is electrically connected to the third node. OS transistors are preferably used as the transistors above.

Abstract: An integrated circuit includes a first replacement gate structure. The first replacement gate structure includes a layer of a first barrier material that is less than 20 ? in thickness and a layer of a p-type workfunction material. The replacement gate structure is less than about 50 nm in width.