Abstract: According to an embodiment, a memory system includes a controller which includes an interface connectable with a host with cache coherency kept. The controller is configured to: before the host writes a command to an I/O submission queue, read the I/O submission queue; after the reading, detect via the interface an invalidation request, the invalidation request being based on writing of the command by the host to the I/O submission queue; and in response to the invalidation request, acquire the command in the I/O submission queue.

Abstract: Embodiments include a system for facilitating data storage. During operation, the system receives a request to write data associated with a logical block address (LBA), wherein the LBA indicates a die to which to write the data and includes a sub-LBA which is used as an index for a mapping table stored on the die. The system assigns, based on the LBA, a physical block address (PBA) which indicates the die and includes a sub-PBA which indicates a first physical location in a block of the die at which the data is to be stored. The system stores, in the mapping table based on the sub-LBA, the PBA. The system writes the PBA and the data to the block based on the PBA.

Abstract: Dynamic random access memory (DRAM) data may be accessed by a memory controller using a broadcast mode or a non-broadcast mode. In the broadcast mode, a first portion of data that is the subject of an access request and a second portion of the data that is the subject of the access request may be accessed concurrently via first and second pseudo-channels, respectively. In the non-broadcast mode, data that is the subject of the access request may be accessed via a selected one of the first and second pseudo-channels.

Abstract: A system includes a memory component and a processing device to determine an amount of data stored at a region of a memory component and determine, based on the amount of data stored in the region of the memory component. The processing device determines a frequency to perform an operation on one or more memory cells of the region of the memory component. The processing device performs the operation on the one or more memory cells at the frequency to maintain the one or more memory cells of the region of the memory component in a first state associated with a first error rate for data stored at the one or more memory cells. The first error rate is less than a second error rate associated with a second state of the one or more memory cells.

Abstract: An apparatus and method of providing direct access to a non-volatile memory of a non-volatile memory device and detecting potential security violations are provided. A method for providing access to a non-volatile memory of a non-volatile memory device may include tracking a parameter related to a plurality of direct access transactions of the non-volatile memory. A threshold behavior pattern of the host activity may be determined based upon the tracked parameters. The direct access transactions may be reviewed to determine whether the threshold behavior pattern is exceeded.

Abstract: Embodiments are directed to a file system engine that provides a file system that includes a plurality of blocks on a file storage tier with portion of the blocks associated with a cache storage tier. A cache engine provides heat extents that include a heat score and a run length value such that the heat extents are represent activities associated with the blocks. Heat extents associated with file system activities are determined based on a position of the blocks that corresponds with the run length values of the heat extents and sectors on the file storage tier. Heat scores associated with the heat extents may be modified based on the activities and distribution models to conform the heat extents with the distribution models. Blocks associated with heat scores that are less than a threshold value provided by the distribution models may be disassociated from the cache storage tier.

Abstract: In a data processing environment, a communication interface of a second host data processing system receives, from a first host data processing system, a host command in a first command set. The host command specifies a memory access to a memory coupled to the second host data processing system. The communication interface translates the host command into a command in a different second command set emulating coupling of an attached functional unit to the communication interface. The communication interface presents the second command to a host bus protocol interface of the second host data processing system. Based on receipt of the second command, the host bus protocol interface initiates, on a system fabric of the second host data processing system, a host bus protocol memory access request specifying the memory access.

Abstract: Embodiments of the present disclosure relate to a method, an electronic device, and a computer program product for storage management. According to an example implementation of the present disclosure, a method for storage management includes: determining a state of cached data stored in an initial cache space of a storage system including a plurality of cache disks, the state indicating that a size of the cached data does not match a size of the initial cache space; determining, based on the state, a target cache space of the storage system; and storing at least a part of the cached data into the target cache space to change the size of the initial cache space. Therefore, the management performance can be improved, and the storage costs can be reduced.

Abstract: A first plurality of block identifiers is sorted based, at least in part, on a measure of spatial locality. A second plurality of block identifiers is sorted based, at least in part, on the measure of spatial locality. At least the first plurality of block identifiers and the second plurality of block identifiers are incrementally merged into a third plurality of block identifiers based, at least in part, on the measure of spatial locality. A block of data corresponding to metadata associated with a plurality of block identifiers of the third plurality of block identifiers is updated.

Abstract: Techniques for caching data are provided that include receiving, by a caching system, a write memory command for a memory address, the write memory command associated with a first color tag, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing first data associated with the first write memory command in a cache line of the second sub-cache, storing the first color tag in the second sub-cache, receiving a second write memory command for the cache line, the write memory command associated with a second color tag, merging the second color tag with the first color tag, storing the merged color tag, and evicting the cache line based on the merged color tag.

Abstract: An apparatus (2) comprises one or more bounded pointer storage element (60s) each to store a pointer (62) having associated range information (64) indicating an allowable range of addresses for the pointer (62). Processing circuitry (4) performs, in response to a first type of instruction (70) identifying a given bounded pointer storage element, a predetermined operation for a target range of addresses determined at least in part on the basis of the range information (64) associated with the pointer stored in the given bounded pointer storage element (60).

Abstract: Efficient space trimming of data storage device is shown, which uses a controller to program a trimming tag that corresponds to a trimming command issued by a host into a cache area of a temporary storage device. The trimming tag, therefore, can be flushed from the cache area to the non-volatile memory for non-volatile storage. The update of the host-to-device mapping table based on the trimming tag can be postponed to the moment that the controller is free.

Abstract: The present disclosure includes apparatuses and methods related to a command bus in memory. A memory module may be equipped with multiple memory media types that are responsive to perform various operations in response to a common command. The operations may be carried out during the same clock cycle in response to the command. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices each coupled to the first number of memory devices via a second number of ports, wherein the second number of memory devices each include a controller, and wherein the first number of memory devices and the second number of memory devices can receive a command from the host to perform the various (e.g., the same or different) operations, sometime concurrently.

Abstract: A storage array uses paged metadata. Each storage director has access to a plurality of object storage systems which describe locations of paged metadata in backing storage. Each object storage system includes different types of inodes which describe objects in backing storage. The object storage systems are used to locate and relocate metadata for loading into global memory, and creation and deletion of objects. An object storage system may be selected based on factors including ratio of different inode types, locality of object usage and anticipated object activity level.

Abstract: Methods, systems, and devices related to balancing data are described. Data may be communicated using an original set of bits that may be partitioned into segments. Each of the original set of bits may have a first value or a second value, where a weight of the original set of bits may be based on a quantity of the set of bits that have the first value. If the weight of the original set of bits is outside of a target weight range, a different, encoded set of bits may be used to represent the data, the encoded set of bits having a weight within the target weight range. The encoded set of bits may be identified based an inversion of the original set of bits in a one-at-a-time and cumulative fashion. The encoded set of bits may be stored in place of the original set of bits.

Abstract: A data storage apparatus includes storage divided into unit physical regions and having data stored therein, a buffer memory having buffer memory regions loaded with a map table comprising map data respectively indicating connection information between logical addresses of a host and start physical addresses for the unit physical regions, and a controller configured to: control data input and output to and from the storage according to a request of a host, to read, based on a map table address corresponding to a logical address included in the request, the map data for the logical address from the buffer memory, and to remap the map data by merging source map data of a buffer memory region having a number of errors equal to or greater than a threshold value with victim map data of a buffer memory region having a number of errors less than the threshold value.

Abstract: Apparatuses and methods for address detection are disclosed herein. An example apparatus it an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.

Abstract: An apparatus, method, and computer-readable storage medium for allowing a block-addressable storage device to provide a sparse address space to a host computer. The storage device exports an address space to a host computing device which is larger than the storage capacity of the storage device. The storage device translates received file system object addresses in the larger address space to physical locations in the smaller address space of the storage device. This allows the host computing device more flexibility in selecting addresses for file system objects which are stored on the storage device.

Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a data migration component, such as a driver, for facilitating the transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may indicate the data migration operation to a second component (e.g., a controller) of the memory system. The second component may initiate the transfer of data between the first memory device and the second memory device based on the receiving the indication of the data migration operation. In some cases, the transfer of data between the first memory device and the second memory device may occur within the memory system without being transferred through a host device.

Abstract: The invention relates to a tiered storage system comprising tiers of data storage. The tiered storage system further comprises a processor; and a memory coupled to the processor. The memory comprises instructions which, when executed by the processor, cause the processor to: receive usage data descriptive of usage of memory extents stored by the tiered storage system; identify periodic usage patterns of the memory extents at least partially by calculating a correlation coefficient between the usage data and a predetermined list of conditions; determine a projected data usage for each of the memory extents using the periodic usage patterns, wherein the projected data usage is temporally dependent; sort the memory extents into usage bins according to the projected data usage; and control the tiers of data storage to migrate the at memory extents between the tiers of data storage using temporal changes of the sorting into the usage bins.