Patents Examined by Charles J Choi
  • Patent number: 10838642
    Abstract: A first plurality of block identifiers is sorted based, at least in part, on a measure of spatial locality. A second plurality of block identifiers is sorted based, at least in part, on the measure of spatial locality. At least the first plurality of block identifiers and the second plurality of block identifiers are incrementally merged into a third plurality of block identifiers based, at least in part, on the measure of spatial locality. A block of data corresponding to metadata associated with a plurality of block identifiers of the third plurality of block identifiers is updated.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: November 17, 2020
    Assignee: NETAPP, INC.
    Inventors: Jayalakshmi Pattabiraman, Nikhil Mattankot, Deekshith Belchapada, Blake H. Lewis, Subramaniam Periyagaram, Satya Suresh Chouta Naga Veera, Rohit Singh, Rajesh Khandelwal, James Robert Morefield
  • Patent number: 10838637
    Abstract: Devices and techniques for status management in storage backed memory are disclosed herein. An encoded message can be received at a first interface of the memory package. Here, the memory package also includes a second interface to a host. The message can be decoded to obtain a decoded message that includes an attribute. The attribute can be compared a set of attributes that correspond to an advertised status of the memory package. The comparison enables a determination that the attribute is in the set of attributes. The advertised status of the memory package can then be modified in response to the determination that the attribute is in the set of attributes.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Michael Burns, Gary R. Van Sickle, Jeffery J. Leyda
  • Patent number: 10831613
    Abstract: Provided are a computer program product, system, and method for replicating a source data set to a target data store. A point-in-time copy of the source data set is generated having a data structure identifying the data in the source data set as of a point-in-time. A restore operation is initiated to copy the source data set represented by the point-in-time copy to a restored copy of the source data set consistent with the source data set. The source data set records are transferred from the restored copy to the target data store in the target storage.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Cadarette, Robert S. Gensler, Jr., Joseph L. Kidd, Robert D. Love, Terri A. Menendez, Austin J. Willoughby
  • Patent number: 10810123
    Abstract: A method, computer program product, and computer system for receiving, by a computing device, an I/O request. The I/O request may be processed as a write miss I/O. One or more dirty pages associated with the write miss I/O may be placed into a tree according to a key. It may be determined whether one of a first event and a second event occurs. A data flush may be triggered for the tree when the first event occurs, and the data flush may be triggered for the data flush for the tree when the second event occurs.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: October 20, 2020
    Assignee: EMC IP Holding Company, LLC
    Inventors: Xinlei Xu, Jian Gao, Lifeng Yang, Michael P. Wahl
  • Patent number: 10789010
    Abstract: A memory subsystem includes a command address bus capable to be operated at double data rate. A memory circuit includes N command signal lines that operate at a data rate of 2R to receive command information from a memory controller. The memory circuit includes 2N command signal lines that operate at a data rate of R to transfer the commands to one or more memory devices. While ratios of 1:2 are specified, similar techniques can be used to send command signals at higher data rates over fewer signal lines from a host to a logic circuit, which then transfers the command signals at lower data rates over more signal lines.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: George Vergis, Kuljit S. Bains
  • Patent number: 10782917
    Abstract: High reliability and high performance of a storage device formed of a Dual port NVMe SSD are achieved while preventing the risk of destruction of data. The storage device includes a main memory that belongs to each of two or more clusters and that stores data related to an IO request; and a processor belonging to each of the clusters controlling accesses to the main memory. The main memory includes a first region where writing from the memory drive is permitted and a second region where the writing is prohibited. The processor selects the first region as a transfer destination related to the IO request from the memory drive when the IO request is a first request, and selects the second region as the transfer destination related to the IO request from the memory drive while permitting writing to the second region when the IO request is a second request.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: September 22, 2020
    Assignee: HITACHI, LTD.
    Inventors: Naoya Okada, Masanori Takada, Mitsuo Date, Sadahiro Sugimoto, Norio Simozono
  • Patent number: 10783022
    Abstract: The systems and methods disclosed herein relate to immediate replication for protected dedicated chunk. In one embodiment, a method comprises generating an encoded portion of data of a dedicated chunk in a node device of a first group of node devices in a first zone of a distributed storage system. The method further comprises, in immediate response to the generating, transferring the encoded portion of data of the dedicated chunk from the node device of the first group of node devices in the first zone of the distributed storage system to a second zone of the distributed storage system. The method further comprises dividing, by the system, the encoded portion of data in the second zone across second node devices.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: September 22, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Mikhail Danilov, Lu Lei
  • Patent number: 10776308
    Abstract: Apparatuses, methods and storage medium associated with smart memory data store/load technology, are disclosed herein. In embodiments, an apparatus may include a processor; a plurality of memory units; a memory controller coupled with the processor and the plurality of memory units to control access of the plurality of memory units, that includes hardware physical memory interleaving support; and one or more hardware data processing logic blocks coupled to the plurality of memory units to provide near data processing of data received by the plurality of memory units. The apparatus may further include a driver to support applications operated by the processor to perform location-aware memory-mapped device accesses to selectively store or load data into selected ones or aggregation of selected ones of the plurality of memory units contiguously. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Soo Keong Ong, Jayson Strayer
  • Patent number: 10769073
    Abstract: Systems, methods, and computer programs are disclosed for managing memory channel connectivity. One embodiment of a system comprises a high-bandwidth memory client, a low-bandwidth memory client, and an address translator. The high-bandwidth memory client is electrically coupled to each of a plurality of memory channels via an interconnect. The low-bandwidth memory client is electrically coupled to only a portion of the plurality of memory channels via the interconnect. The address translator is in communication with the high-bandwidth memory client and configured to perform physical address manipulation when a memory page to be accessed by the high-bandwidth memory client is shared with the low-bandwidth memory client.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: September 8, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Kunal Desai, Satyaki Mukherjee, Siddharth Kamdar, Abhinav Mittal, Vinayak Shrivastava
  • Patent number: 10761727
    Abstract: A region of a memory component is determined to include a type of memory. A frequency to perform an operation on the region of the memory component is determined based on the type of memory. The operation is performed on a memory cell at the region of the memory component at the determined frequency to transition the memory cell from a state associated with an increased error rate for data stored at the memory cell to another state associated with a decreased error rate for the data stored at the memory cell.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: September 1, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Harish R. Singidi, Ashutosh Malshe, Kishore Kumar Muchherla
  • Patent number: 10754587
    Abstract: A method of operating a storage controller is provided. The method includes receiving a request from a partition creator, for a first partition within a storage system, the first partition comprising one or more sequentially numbered data blocks, and receiving first partition parameters from the partition creator, the first partition parameters comprising a size of the one or more sequentially numbered data blocks. The method also includes creating the first partition within the storage system, through a storage interface, based on the first partition parameters, receiving first host data from a host, configuring the first host data as first storage data for storage within the first partition within the storage system, and sequentially storing the first storage data in the one or more sequentially numbered data blocks in the first partition, through the storage interface.
    Type: Grant
    Filed: March 20, 2016
    Date of Patent: August 25, 2020
    Assignee: Burlywood, Inc.
    Inventor: Tod R. Earhart
  • Patent number: 10747469
    Abstract: A memory system includes: a memory device that includes a plurality of memory dies each of which includes a plurality of planes, each of which includes a plurality of memory blocks that store data; and a controller including a first memory, and configured to: receive a plurality of commands from a host; perform command operations corresponding to the received commands in the memory blocks; detect patterns of the commands, the command operations, and user data corresponding to the command operations; dynamically allocate as pattern zones the first memory based on the patterns; and load map segments of map data corresponding to the commands, the command operations, and the user data into the pattern zones.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: August 18, 2020
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 10733105
    Abstract: According to some embodiments, a backup storage system receives a request from a client at a storage system for accessing data segments. For each of a first groups of the data segments requested that are stored in a solid state device (SSD) cache, the system requests a first batch job for each of the first groups to retrieve the first groups of the data segments from the SSD cache via a first set of input/output (IO) threads. For each of a second groups of the data segments requested that are not stored in the SSD cache, the system requests a second batch job for each of the second groups to retrieve the second groups of the data segments from storage units of the storage system via a second set of input/output (IO) threads. The system assembles received segments and returns them to the client altogether.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: August 4, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Satish Visvanathan, Rahul B. Ugale
  • Patent number: 10698773
    Abstract: Provided are a computer program product, system, and method for replicating a source data set to a target data store. A point-in-time copy of the source data set is generated having a data structure identifying the data in the source data set as of a point-in-time. A restore operation is initiated to copy the source data set represented by the point-in-time copy to a restored copy of the source data set consistent with the source data set. The source data set records are transferred from the restored copy to the target data store in the target storage.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Cadarette, Robert S. Gensler, Jr., Joseph L. Kidd, Robert D. Love, Terri A. Menendez, Austin J. Willoughby
  • Patent number: 10691595
    Abstract: A first request to perform an operation at an address associated with a media is obtained. The operation is issued to a plurality of cache divisions, wherein each cache division comprises a cache controller and a cache memory. A location in another memory associated with the first request is updated, the location in the other memory including a plurality of indicators corresponding to a status of the operation with each of the plurality of cache divisions. Based on one or more responses from the cache division(s), a response to the first request is sent.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 23, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Robert M. Walker, Ashay Narsale
  • Patent number: 10691349
    Abstract: A method, executed by a computer, includes writing, to a storage device, a first instance of a data sequence and a corresponding first reference count, in response to determining that a subsequent data sequence is identical to the first instance of the data sequence, writing, to the storage device, a metadata reference referencing the subsequent data sequence and incrementing the first reference count, and writing, to a storage device, a second instance of the data sequence and a corresponding second reference count in response to determining that the first reference count is equal to a selected threshold. A computer system and computer program product corresponding to the above method are also disclosed herein.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Joseph W. Dain, Itzhack Goldberg, Gregory T. Kishi
  • Patent number: 10671297
    Abstract: A memory system may include: a nonvolatile memory device comprising K memory blocks; and a controller suitable for controlling an operation of the nonvolatile memory device. The controller may include: a counting management unit suitable for using K count codes capable of counting a preset range from a base value to a limit value in order to manage K counting values corresponding to predetermined operations of the K memory blocks, respectively, and adjusting the absolute values of the base value and the limit value using the count code in the form of a 1/N-chain depending on a distribution of the K counting values; and a wear-leveling operation unit suitable for performing a wear-leveling operation on the K memory blocks such that the K counting values are distributed in a section of values corresponding to 1/N of the preset range, the count code may be a J-based number, each of J and K may be a natural number larger than 2, and N may be any one of powers of J larger than 1.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: June 2, 2020
    Assignee: SK hynix Inc.
    Inventor: Chang-Hyun Park
  • Patent number: 10671431
    Abstract: Forecasting workload activity for data stored on a data storage device includes selecting at least one metric for measuring workload activity, providing at least one grouping of portions of the data according to a workload affinity determination provided for each of the portions at a subset of a plurality of time steps, where the workload affinity determination is based on each of the data portions in the group experiencing above-average workload activity during same ones of the subset of the plurality of time steps, the subset corresponding to at least one business cycle for accessing the data, and forecasting workload activity for all of the portions of data in the group based on forecasting workload activity for a subset of the data portions that is less than all of the data portions.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: June 2, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Sean C. Dolan, Dana Naamad, Marik Marshak, Hui Wang, Xiaomei Liu
  • Patent number: 10656832
    Abstract: A memory system comprises a memory device including a plurality of memory blocks, a write operation check unit configured to count the number of write operations performed on the respective memory blocks, a write count distribution management module configured to manage a distribution of the memory blocks based on the counted number of the write operations, and a wear leveling module configured to detect hot and cold memory blocks from the plurality of memory blocks based on the counted number of the write operation and the distribution, wherein the wear leveling module manages a history of the hot memory block and swaps the hot memory block with the cold memory block according to the managed history.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: May 19, 2020
    Assignee: SK hynix Inc.
    Inventors: Jung-Hyun Kwon, Sung-Eun Lee, Sang-Gu Jo
  • Patent number: 10635587
    Abstract: According to one embodiment, a memory controller includes a nonvolatile cache memory and a controller. The nonvolatile cache memory is configured to store a piece of data stored in a nonvolatile main memory connected to the memory controller. The controller is configured to control writing of data to the nonvolatile cache memory. The memory controller is connected to a processor via an interconnect that ensures a protocol indicating a procedure for preventing data inconsistency in a plurality of cache memories. The controller causes, after detecting that the processor has updated data corresponding to any area of the nonvolatile main memory using the protocol, the updated data to be transmitted to the memory controller and writes the updated data to the nonvolatile cache memory.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: April 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Shirota, Tatsunori Kanai, Masaya Tarui