Abstract: A method of doping a compound semiconductor layer n-type during epitaxial growth of the compound semiconductor layer includes supplying source materials including respective elements of a compound semiconductor material to a heated monocrystalline substrate, epitaxially growing a layer of the compound semiconductor material on the heated substrate and, simultaneously, supplying SiI.sub.4 as a dopant source material including silicon to the heated substrate, incorporating silicon as a dopant impurity producing n-type conductivity into the compound semiconductor layer during the epitaxial growth.

Abstract: The invention is carried out in a plasma reactor for processing a semiconductor wafer, the plasma reactor having a chamber for containing a processing gas and having a conductor connected to an RF power source for coupling RF power into the reactor chamber to generate from the processing gas a plasma inside the chamber, the chamber containing at least one surface exposed toward the plasma and susceptible to contamination by particles produced during processing of the wafer, the invention being carried out by promoting, during processing of the wafer, bombarding of particles from the plasma onto the one surface to remove therefrom contaminants deposited during processing of the wafer. Such promoting of bombarding is carried out by providing an RF power supply and coupling, during processing of the wafer, RF power from the supply to the one surface. The coupling may be performed by a capacitive cleaning electrode adjacent the one surface, the capacitive cleaning electrode connected to the RF power supply.

Abstract: A method for eliminating the antenna effect in the manufacture of an integrated circuit in a silicon substrate, wherein there are contact pad areas at the periphery of the integrated circuit and interconnection lines connecting the contact pad areas with the integrated circuit. This is achieved by grounding the contact pad areas to the silicon substrate; processing in a plasma environment that would normally produce electrical charge build-up at the gate oxide of the integrated circuit, but wherein the grounded contact pad areas eliminates the charge build-up; and disabling the grounding of the contact pad areas to retrieve the functioning of the integrated circuit.

Abstract: A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics.

Abstract: Disclosed is a reproducible process for making an SiO.sub.2 layer by thermal oxidation which assures an extremely uniform thickness of the SiO.sub.2 layer of approximately 1%. The process of the invention comprises the steps growing an initial layer of SiO.sub.2 to a defined minimal thickness by dry oxidation and increasing the thickness of the initial layer by simultaneous wet and dry oxidation until the desired final thickness is reached.

Abstract: A Bragg grating is produced in a semiconductor component by wet etching through a resin mask developed after holographic exposure. This causes the regions of the grating at the boundary of other parts of the component to be etched more deeply. To compensate this, the method includes further irradiation through a second mask disposed at a distance from the part of the resin mask that defines the location of the grating. Applications include opto-electronic components.

Abstract: For each storage cell, the DRAM cell arrangement has a vertical MOS transistor, the first source/drain region of which is connected to a memory node of a storage capacitor, the channel region of which is annularly enclosed by a gate electrode and the second source/drain region of which is connected to a buried bit line. The DRAM cell arrangement can be produced with a storage-cell area of 4F.sup.2 by using only two masks, F being the minimum producible structure size in the respective technology.

Abstract: Plugging of the effluent line of an apparatus comprising CVD chamber is prevented or substantially reduced by injecting a hot gas into the effluent line during processing. In CVD tungsten processing, including preconditioning the reaction chamber, deposition, and cleaning, a hot gas, such as dried air or nitrogen, is injected into the effluent line downstream of the vacuum pump to maintain the temperature of the internal walls of the effluent line below that at which condensation of WOF.sub.4 occurs. In another embodiment, periodic high bursts of a hot gas into the effluent line removes WO.sub.3 deposits proximate the inlet of the downstream wet scrubber.

Abstract: A method for crystallizing a portion of a semiconductor thin film while forming a semiconductor device comprises providing a transparent substrate supporting a metallic gate electrode and an amorphous semiconductor thin film which are separated from each other by a gate insulating film, heating the gate electrode by subjecting it to light rays, and applying a laser beam to the amorphous semiconductor thin film so that the portion of the semiconductor thin film adjacent the metallic gate electrode is heated by both the laser beam and the heat of the gate electrode to cause a crystallization of a portion of the amorphous thin film and then processing the remaining amorphous portions of the thin film to form the transistor structure.

Abstract: Fabricating a semiconductor memory device with a capacitor includes forming a first insulating layer on a substrate, covering a transfer transistor, and forming a first conducting layer that penetrates the first insulating layer and is electrically coupled to one of a drain or source region of the transfer transistor. Thereafter, a pillar layer is formed at the periphery of and above the first conducting layer, and a second conducting layer is also formed on sidewalls of the pillar layer. Next, alternately a first and a second film layer are formed at least once over the first conducting layer and the second conducting layer. Then, a second insulating layer is formed above the second film layer. After that, a third conducting layer is formed and then defined such that the first, the second, and the third conducting layers, in combination with the second film layer, form a storage electrode of a charge storage capacitor.

Abstract: A method is provided for forming metal interconnect structures which resists the formation of pile-ups caused by electromigration. Each metal interconnect structure includes an aluminum interconnect sandwiched between two refractory metal layers. The method of the present invention involves forming a layer of aluminum intermetallic alloy on the sidewalls of the aluminum interconnects. The layer of aluminum intermetallic alloy provides reinforcement for the sidewalls. The layer of aluminum intermetallic alloy comprises aluminum-refractory metal alloy. The aluminum-refractory metal alloy is formed by reacting the exposed aluminum on the sidewalls with refractory metal-containing precursor material. After the formation of the layer of aluminum intermetallic alloy the sidewalls of the aluminum interconnects, the formation of pile-ups will be suppressed. Thus, the lifetime of the aluminum interconnects is extended.

Abstract: A method of fabricating high step alignment marks on a twin-well integrated circuit. An alignment mark photoresist pattern is formed overlaying the nitride layer using lithography technique. The nitride layer is partially etched to form a nitride alignment pattern using the alignment mark photoresist pattern as a mask. After the formation of N-well and P-well regions using lithography technique, the N-doped and P-doped impurities are subject to a thermally drive in process to activate and form N-well and P-well regions, respectively. At the same time, the pad oxide layer overlaying the N-well and P-well regions and the region not covered by the nitride alignment pattern is converted to a thermal oxide layer. The thermal oxide layer can be removed to reveal a recessed portion on the surface of the P-type silicon substrate, whereby the thickness of the nitride layer plus the depth of the recessed portion causes high step alignment marks to be formed.

Abstract: A reduced permittivity interlevel dielectric in a semiconductor device arranged between two levels of interconnect. The dielectric comprises a first dielectric layer preferably from a silane source deposited on a first level interconnect to form air gaps at midpoints between adjacent first interconnect structures, a second dielectric containing air gap trenches at spaced intervals across the second dielectric, and a third dielectric formed upon said second dielectric. A second interconnect level is formed on the third dielectric.

Abstract: A structure for chemical vapor deposition processing includes a substrate carrier (10) having a streamlined shape. When placed in a mainstream flow (21), the substrate carrier (10) maintains a laminar boundary layer over a substrate (17) under high gas flow rate conditions. In a further embodiment, the substrate carrier (10) includes a device (27) for directly injecting a reactant gas stream (33) into the boundary layer.

Abstract: The formation of contact holes and a capacitor is performed in a semiconductor integrated circuit such as an active matrix circuit. An interlayer insulator having a multilayer (a lower layer is silicon oxide; an upper layer is silicon nitride) each having different dry etching characteristic is formed. Using a first mask, the silicon nitride corresponding to the upper layer in the interlayer insulator is etched by dry etching. This etching is completed by using the silicon oxide corresponding to the lower layer as an etching stopper. A pattern is formed using a second mask to form selectively the silicon oxide corresponding to the lower layer. Thus a first portion that the silicon oxide and the silicon nitride are etched and a second portion that only silicon nitride is etched are obtained. The first portion is used as a contact hole. A capacitor is formed in the second portion.

Abstract: A method for forming a metal layer of an ultra-thin film according to metal deposition conditions and a method for forming metal wiring by filling a high aspect-ratio contact hole using cooling step prior to depositing the metal layer. In particular, the additional cooling process is performed before the process of depositing the metal layer and then the deposition process is performed in a state where the temperature of the wafer has been cooled down to a temperature in the range between -25.degree. C. and room temperature. The surface morphology of the deposited metal layer is improved and a continuous ultra-thin film can be obtained. Also, the aluminum filling characteristics in the contact hole having a high aspect-ratio are improved.

Abstract: A manufacturing method of semiconductor light emitting element including the steps of: (a) laminating a gallium nitride compound semiconductor layer for forming a luminous part on a substrate including at least an n-type layer and a p-type layer, by organic metal compound vapor phase growth method, (b) forming the gallium nitride compound semiconductor layer in a nitrogen gas atmosphere after laminating, and lowering the ambient temperature to the temperature for growing a GaAs compound in vapor phase and annealing the p-type layer of the gallium nitride compound semiconductor, (c) forming a film of at least one type selected from the group consisting of GaAs, GaP, InAs, InP, all doped with Mg, and part of these group III elements replaces by Al.

Abstract: A method for manufacturing a liquid crystal display which reduces the number of photolithography processes is provided.

Abstract: The present invention relates to forming a narrow gate MOSFET having a local ion implantation to reduce the junction capacitance. A polysilicon layer is formed over a semiconductor substrate. An opening is formed in the polysilicon layer by using patterning and etching. Subsequently, a thermal oxidation is performed to oxidize the polysilicon layer into a polysilicon-oxide layer that is expanded in volume relative to the polysilicon layer thereby narrowing said opening. Then an ion implantation is performed by using said polysilicon-oxide layer as a mask.

Abstract: A method for forming a contact opening is described and which includes providing a node location to which electrical connection is to be made; forming a conductive line adjacent the node location, the conductive line having a conductive top and sidewall surfaces; forming electrically insulative oxide in covering relation relative to the top surface of the conductive line; forming electrically insulative nitride sidewall spacers over the conductive sidewall surfaces, the nitride sidewall spacers projecting outwardly of the conductive line top conductive surface, the electrically insulative oxide positioned between the nitride sidewall spacers; forming an electrically insulative layer outwardly of the conductive line, and the node location; and etching a contact opening to the node location or the top surface through the electrically insulative layer substantially selective relative to the nitride sidewall spacers.