Abstract: The present invention discloses a method of fabricating flash memory cell for use in semiconductor memories. A nitrogen implantation step is added in the process to increase the performance of the device. The nitrogen implanted tunnel oxide exhibits a much higher electron conduction efficiency than the prior art tunnel oxides in both injection polarities. The value of charge-to-breakdown voltage of the nitrogen implanted tunnel oxide is also much larger than the narrow tunnel oxide. In addition, the electron trapping rate of the nitrogen implantation tunnel oxide is very small even under a very large electron fluence stressing (100 C/cm.sup.2).

Abstract: A vertical PNP transistor and method for making it provide a transistor in a surface layer (12), which may be an epitaxial layer, of P- type conductivity at a surface of a substrate (11) of P+ type conductivity. An isolation region (14) of N- type conductivity in the P- surface layer (12) contains a collector region (25) of P- type conductivity. A base region (30) of N type conductivity is contained in the collector region (25), and an emitter region (40) of P+ type conductivity is contained in the base region (30). The base region (30) may be provided with a higher N type impurity concentration than a P type impurity concentration of the collector region (25). At least the collector region (25) and the base region (30) may be self aligned. The collector region (25) may be of thickness of about 2.2 .mu.m, the base region (30) of thickness of about 0.1 .mu.m, and the emitter region (40) of thickness of about 0.4 .mu.m.

Abstract: In order to obtain a semiconductor device having an internal wire of low resistance, a conductive layer whose surface is silicified is provided in a surface of a semiconductor substrate. A conductor whose surface is silicified is provided on the semiconductor substrate in proximity to the conductive layer. This semiconductor device is provided with an internal wiring layer, which is formed by a titanium film and a titanium silicide layer for electrically connecting the surface of the conductive layer and a surface of an end of the conductor with each other, to cover a side wall surface and a bottom surface of a contact hole.

Abstract: The method for making a charge coupled device includes: forming a semiconductor region 24 of a first conductivity type; forming gate regions 28 and 30 overlying and separated from the semiconductor region 24; forming clocked barrier implants 36 and 38 of a second conductivity type in the semiconductor region 24 and aligned to the gate regions 36 and 38; depositing a semiconductor layer 70 overlying and separated from the semiconductor region 24 and the gate regions 28 and 30; removing a portion of the semiconductor layer 70 leaving semiconductor side walls 40 and 42 coupled to the gate regions 28 and 30.

Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposition of the nonconformal source material is stopped and a flowable insulating material, such as spin on glass, is coated on nonconformal insulating material to fill the remaining gaps. After etching the surfaces of the nonconformal and flowable insulating materials, another insulating layer is deposited and planarized to the desired overall thickness of the insulation. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines.

Abstract: A method for forming thin films and controlling the tensile and compressive stresses and mechanical properties of the thin film. The method includes forming an alloy on a substrate having a solvent metal and a solute, then annealing the substrate and the alloy in one of an oxidizing, nitriding and carborizing ambient so that the ambient reacts with the solute to form respectively one of an oxide, nitride and carbide precipitates of the solute in the solvent. The solute is selected so that the precipitates formed may be used to control the mechanical properties of the solvent.

Abstract: A method for substantially improving the photo luminescent performance of a porous semiconductor, involving the steps of providing a bulk semiconductor substrate wafer of a given conductivity, wherein the substrate wafer has a porous semiconductor layer of the same conductivity as the bulk semiconductor substrate wafer, and the porous semiconductor layer is made up of a plurality of pores interspersed within a plurality of nanocrystallites, wherein each of the pores its defined by a pore wall and each of the nanocrystallites has a given thickness. Next, in the method, at least one monolayer layer of passivating material is generated on the pore wall of each of the pores, to passivate the porous semiconductor layer. The one layer of passivating material substantially eliminates dangling bonds and surface states which are associated with the porous semiconductor layer. The resulting passivated porous semiconductor layer exhibits a quantum efficiency of approximately 5 percent.

Abstract: In a method of forming a II-VI compound semiconductor thin film on an InP substrate, a layer of III-V compound semiconductor mixed crystal is first formed on the InP substrate. The desorption rate of a group V element constituting the III-V compound semiconductor mixed crystal at a decomposition temperature of a native oxide layer formed on a surface of the III-V compound semiconductor mixed crystal layer is lower than a desorption rate of P of the InP substrate at a decomposition temperature of a native oxide layer formed on a surface of the InP substrate. A II-VI compound semiconductor thin film layer is formed on the first III-V compound semiconductor mixed crystal layer.

Abstract: The method of this invention for heat treatment of a Si single crystal grown by the Czochralski method at a speed of pull of not less than 0.8 mm/min., characterized by heat-treating at a temperature in the range of from 1,150.degree. C. to 1,280.degree. C. a wafer cut out of the Si single crystal thereby producing a Si wafer excellent in oxide film dielectric breakdown voltage characteristic due to elimination of crystal defects. Consequently, this invention ensures production of LSI in a high yield.

Abstract: A process for synthesizing wide band gap materials, specifically, GaN, employs plasma-assisted and thermal nitridation with NH.sub.3 to convert GaAs to GaN. Thermal assisted nitridation with NH.sub.3 can be employed for forming layers of substantial thickness (on the order of 1 micron) of cubic and hexagonal GaN on a GaAs substrate. Plasma-assisted nitridation of NH.sub.3 results in formation of predominantly cubic GaN, a form particularly useful in optoelectronic devices. Preferably, very thin GaAs membranes are employed to permit formation thereon of GaN layers of any desired thickness without concern for critical thickness constraints. The thin membranes are preferably formed either with an epitaxial bonding technique, or by undercut etching.

Abstract: A method for pretreating a semiconductor surface, comprising the steps of: placing a titanium nitride substrate in a reaction chamber and subjecting the reaction chamber to vacuum; purging the reaction chamber with an inert gas selected from the group consisting of N.sub.2, Ar and He and evacuating the reaction chamber into 1 mTorr or lower; treating the surface of the titanium nitride substrate with a reaction gas comprising WF; charging a reducing gas and a source gas for deposition material to form a thin film on the titanium nitride substrate, by which the nucleation rate of deposition material and the number of nucleation sites on the substrate can be increased and a thin film with a uniform thickness and high density can be formed on the substrate.

Abstract: A ridge wavegide laser diode, with an inverse mesa structure, resistant to heat and improved in the adhesion of a contact metal to a contact layer, which can be obtained by forming a polyimide spacer in such a way that polyimide remains only at the lower part of the corner of the inverse mesa structure. In the diode, the contact metal is minimally broken off at the opposite sides of the mesa structure.

Abstract: A capacitor includes a first electrode in which a first material layer composed of a conductive oxide and a second material layer formed of a conductive material are alternately stacked. The side surface of the second material layer is recessed to form a fin-shaped structure and the second material layer is etched to have a width shorter than that of the first material layer. The capacitor also includes a second electrode and a dielectric material formed between the first electrode and the second electrode.

Abstract: In a semiconductor device having a ferroelectric capacitor and manufacturing method thereof, a spacer comprising a low dielectric constant material is formed on the side surfaces of a plurality of lower electrodes separated into each cell unit, and a ferroelectric film is formed on the lower electrodes whereon the low dielectric constant material spacer is formed, and an upper electrode is formed on the ferroelectric film, to thereby prevent an error which may be caused between the adjacent lower electrodes.

Abstract: A process for fabricating an electronic circuit by oxidizing the surroundings of a metallic interconnection such as of aluminum, tantalum, and titanium, wherein anodic oxidation is effected at a temperature not higher than room temperature, preferably, at 10.degree. C. or lower, and more preferably, at 0.degree. C. or lower. The surface oxidation rate of a metallic interconnection can be maintained constant to provide a surface free of irregularities.

Abstract: The method produces liquid contacts in contact holes on a top side of a semiconductor component. The top side is not wettable by material provided for the liquid contacts. The walls and edges of the contact holes are wettable by the material. The contact holes are filled as follows. The material provided for the liquid contacts is applied to the top side by a doctor blade. There is situated on a longitudinal edge of the doctor blade an adhesion strip which is made of a material which is wettable by the material provided for the liquid contacts. The longitudinal edge of the doctor blade is guided at a distance over the top side. The material provided for the liquid contacts is moved in the form of a cylinder between the adhesion stip and the surface of the component.

Abstract: An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of field dielectric having an upper surface substantially coplanar with each other and with adjacent silicon mesa upper surfaces. The isolation process is thereby a planarization process used with the shallow trench technique, wherein etch-enhancing ions are forwarded into the fill dielectric at upper elevational regions of that dielectric. When subjected to a subsequent etchant, the dopants cause the higher elevational regions to be removed at a faster rate than the lower elevational regions. Thus, selective placement of dopants and etch removal pre-conditions the fill dielectric upper surface to a more planar surface globally across the entire wafer.

Abstract: A process for reducing halogen concentration in a material layer (56) includes the deposition of a dielectric layer (58) overlying the material layer (56). An annealing process is carried out to diffuse halogen atoms from the material layer (56) into the overlying dielectric layer (58). Once the diffusion process is complete, the dielectric layer (58) is removed.

Abstract: A method for producing a relatively thin titanium nitride barrier layer in an integrated circuit is presented. The titanium nitride layer may be utilized in a tungsten plug interconnection by providing a semiconductor wafer with a conducting layer covered by an insulating layer. The insulating layer is patterned and etched to form contact holes or vias. A layer of titanium is deposited on the surface of the wafer including the sidewalls and bottom of the via. A relatively thin titanium nitride layer is then formed on the titanium layer. The formation of the titanium nitride layer includes growing titanium nitride by a reaction of a nitrogen-bearing species with the titanium layer. The titanium nitride layer prevents the underlying titanium layer from reacting with the subsequent tungsten layer which is deposited on the wafer to fill the via. The tungsten layer is then etched so that the tungsten remaining forms a plug interconnection between conducting layers.

Abstract: A method is provided of fabricating a thin film transistor semiconductor film of polycrystalline silicon on a transparent substrate suitable for the manufacture of a liquid crystal display. A film of substantially amorphous silicon is placed on the transparent substrate. Suspended in the amorphous silicon are small silicon seed crystals. As the amorphous silicon is annealed, crystal grains, begun from the seed crystals, are formed in the resulting polycrystalline silicon. The seed crystals help regulate the annealment process, and reduce process dependence on precision deposition and heating methods. The use of seed crystals also helps ensure that crystal grains are both large and consistent in size. Large grains promote to production of TFTs with high electron mobility and uniform performance across the entire LCD.