Abstract: Disclosed is a controller for a disaggregated memory device. The controller may receive a request to allocate memory of a specific size from the disaggregated memory device to a computing device, and may generate a memory block device in the specific size from a memory pool formed from physical memory modules configured on the disaggregated memory device. The controller may expose the memory block device to the computing device as a Non-Volatile Memory Express (“NVMe”) target device, and may control access to the memory block device by converting NVMe access requests in a first format from the computing device to access requests in a different second format supported by the memory block device.

Abstract: Memory allocation circuitry allocate a memory region in memory, and bounded pointer generation circuitry generates bounded pointers including a revocable bounded pointer that provides a pointer value and range information identifying an address range of the memory region. The memory allocation circuitry provides, at a header location in the memory, a header for the memory region with a first token field which is initialized to a first token value associated with the memory region. The memory allocation circuitry is responsive to the deallocation of the memory region to modify the stored value in the first token field of the header. In response to a request to generate a memory address using the revocable bounded pointer, a use authentication check prevents generation of the memory address when it is determined that the stored value in the first token field has been changed.

Abstract: According to one embodiment, a memory system is connectable to a host as a type 3 compute express link (CXL) device. A controller of the memory system packs, at a CXL link layer, a response command with data (DRS) and/or a response command without data (NDR), received from an upper CXL transaction layer, into a flit including four slots, and transmits the response command to a lower CXL ARB/MUX layer, and selects, based on a remaining number of data slots of DRS packed in a first flit that has been transmitted to the CXL ARB/MUX layer, a remaining number of DRS, a remaining number of NDR, and a number of empty slots in a second flit to be transmitted subsequently to the CXL ARB/MUX layer, a format to be used in slots in a second flit.

Abstract: Memory management circuitry and processes operate to improve reliability of a group of memory stacks, providing that if a memory stack or a portion thereof fails during the product's lifetime, the system may still recover with no errors or data loss. A front-end controller receives a block of data requested to be written to memory, divides the block into sub-blocks, and creates a new redundant reliability sub-block. The sub-blocks are then written to different memory stacks. When reading data from the memory stacks, the front-end controller detects errors indicating a failure within one of the memory stacks, and recovers corrected data using the reliability sub-block. The front-end controller may monitor errors for signs of a stack failure and disable the failed stack.

Abstract: A storage usage management system includes a storage usage management subsystem coupled to first and second storage devices. The storage usage management subsystem collects first write usage data from use of the first storage device by a host mapped to the first storage device, determines that second write usage data from use of the first storage device by the host exceeds first metric(s) associated with the first write usage data by a first threshold, and collects the second write usage data and third write usage data from immediately subsequent use of the first storage device by the host. If the storage usage management subsystem determines that the second and third write usage data exceed second metric(s) associated with the first write usage data by a second threshold, it uses the second and third write usage data to determine whether to remap the host to the second storage device.

Abstract: Described are methods and systems for improved cardinality estimation. A method may include obtaining a data-query, obtaining a row, generating a hash value, determining a cardinality of leading zeros in the hash value, identifying a bucket with respect to the hash value, including a bucket identifier and the cardinality of leading zeros in a representation, determining the approximate unique count, and outputting the approximate unique count as results data responsive to the portion of the data-query.

Abstract: A memory system includes a storage medium having a plurality of memory regions. A controller is configured to allocate each of a plurality of open memory regions among the memory regions to one or more levels and store, in response to a write request received from a host device that includes data and a level of the data, the data in an open memory region allocated to the level. A level may be a level of a file in a predetermined unit in which the data is included, such as in a log-structured merge (LSM) tree structure.

Abstract: A memory device includes a plurality of memory blocks, a read count storage, and a read reclaim processor. The read count storage stores read count information including a read count of each of the plurality of memory blocks. The read reclaim processor provides a memory controller with a status read response including a status code representing a priority order of a read reclaim operation on a target block, in response to a status read command received from the memory controller.

Abstract: A method of translating a virtual address into a physical memory address in an ARM System Memory Management Unit version 3 (SMMUv3) system includes searching a Configuration Cache memory for a matching tag that matches an associated tag upon receiving the virtual address and the associated tag, and extracting, in a single memory lookup cycle, a matching data field associated with the matching tag when the matching tag is found in the Configuration Cache memory. A matching data field of the Configuration Cache memory includes a matching Stream Table Entry (STE) and a matching Context Descriptor (CD), both associated with the matching tag. The Configuration Cache memory may be configured as a content-addressable memory. The method further includes storing entries associated with a multiple memory lookup cycle virtual address-to-physical address translation into the Configuration Cache memory, each of the entries including a tag, an associated STE and an associated CD.

Abstract: In one aspect, a device may include at least one processor and storage accessible to the at least one processor. The storage may include instructions executable by the at least one processor to allocate, in memory, a read-once memory container to store data from a first computer program. The instructions may also be executable to write the data from the first computer program to the read-once memory container and to permit a second computer program to use the data as stored in the read-once memory container. The data, upon being accessed from the read-once memory container, may not be readable again from the read-once memory container without being written again.

Abstract: An accelerator and a system for accelerating operations are disclosed. A respective apparatus comprises an interface configured to couple the apparatus to an interconnect, a plurality of processing modules, each processing module configured to process data, a control module configured to control processing of each of the plurality of processing modules, and a cache module configured to store at least a portion of data processed by at least one of the plurality of processing modules. Each processing module includes a processing core configured to process data by performing an operation on the data using a plurality of processing elements, an input control unit configured to retrieve data via the interface and data stored in the cache module and to provide the retrieved data to the processing core, and an output control unit configured to provide data processed by the processing core to the interface and the cache module.

Abstract: A control apparatus includes a processor configured to execute a procedure including: receiving, from a processing device, a reading request to read a first data piece among a plurality of data pieces included in a data set, the processing device executing a given process on each of the data pieces; reading the first data piece from a first storage tier among a plurality of hierarchical storage tiers having respective different reading capabilities; transmitting the read first data piece to the processing device in response to the reading request; measuring a processing time that the processing device takes to execute the given process; determine a storage tier that is to store the first data piece among the hierarchical storage tiers based on the reading capabilities and the measured processing time; and migrating the first data piece from the first storage tier to the determined storage tier.

Abstract: Method for reducing memory fragmentation characterized in that it the steps of: for each image in a source set of images (601) determining image size (602) in pixels and obtaining (603) a minimal total number of pixels for an aggregated surface by obtaining a sum of image sizes; factorizing (604) the sum of image sizes into a surface's width and height; allocating memory (702) for the surface (701); creating (703) a mapping between an image identifier and its location, width, height for each image associated with the surface; for each image, according to its offset in the surface, the two-dimensional space of the image is cast (704) to one dimension; knowing the casting formula between the one and two-dimensional spaces, copying each image to the surface (705).

Abstract: A memory controller for controlling a plurality of memory chips of a non-volatile memory includes a first core configured to identify a size of a remaining space of a page to be written in a memory chip on which a write operation is to be performed among the plurality of memory chips and fetch a first write command from a first submission queue among a plurality of submission queues included in a host, the first write command being related to data having a size corresponding to that of the remaining space of the page to be written, and a second core configured to control the non-volatile memory to store data related to the fetched first write command in the remaining space of the page to be written.

Abstract: An apparatus including a plurality of set arbitration circuits and a die arbitration circuit. The set arbitration circuits may each be configured to receive first commands and second commands and comprise a bank circuit configured to queue bank data in response to client requests and a set arbitration logic configured to queue the second commands in response to the bank data. The die arbitration circuit may be configured to receive the commands from the set arbitration circuits and comprise a die-bank circuit configured to queue die data in response to the client requests and a die arbitration logic configured to queue the second commands in response to the die data. Queuing the bank data and the die data for the second commands may maintain an order of the client requests and prioritize the first commands corresponding to a current controller over the first commands corresponding to a non-current controller.

Abstract: An information handling system may have a long short term memory (LSTM) that receives Input/Output (I/O) parameters, and produces a prediction output by operation of a recursive neural network (RNN). An I/O optimizer provides the I/O parameters to the LSTM and receives the prediction output from the LSTM. The I/O optimizer may include a manager module configured to provide control signals to control gates for controlling application of the I/O parameters and the prediction output, and a collector module configured to collect the I/O parameters.

Abstract: Systems for high performance restore of data to storage devices. A method embodiment commences upon identifying a plurality of virtual disks to be grouped together into one or more consistency sets. Storage I/O commands for the plurality of virtual disks of the consistency sets are captured into multiple levels of backup data. On a time schedule, multiple levels of backup data for the virtual disks are cascaded by processing data from one or more higher granularity levels of backup data to one or more lower granularity levels of backup data. A restore operation can access the multiple levels of backup data to construct a restore set that is consistent to a designated point in time or to a designated state. Multiple staging areas can be maintained using lightweight snapshot data structures that each comprise a series of captured I/Os to be replayed over other datasets to generate a restore set.

Abstract: A service management device includes a memory, and a processor coupled to the memory and configured to acquire respective execution times of programs that implement a service, identify a first volume having a largest influence on a response time of the service based on the respective execution times of the programs, where the first volume being any one of volumes of a storage device, and at least one of the programs writing and reading data to and from the storage device, and set a priority of writing and reading of data to and from the first volume higher than priorities of writing and reading of data to and from a remaining volume of the volumes.

Abstract: Dynamic caching policies and/or dynamic purging policies are provided for modifying the entry and eviction of content to the cache (e.g., storage and/or memory) of a caching server based on the current and past cache performance and/or demand. The caching server may modify or replace a configured policy when cache performance is below one or more thresholds. Modifying the caching policy may change caching behavior of the caching server by changing the conditions that control the content that is entered into cache or the content that is deferred and not entered into cache after a request. This may include assigning different probabilities for entering the same content into cache based on different caching policies. Modifying the purging policy may change eviction behavior of the caching server by changing the conditions that control the cached content that is selected and removed from cache.

Abstract: Storage management techniques involve: obtaining a historical usage of storage capacity for a storage device, and a historical feature characterizing the historical usage of storage capacity; generating a predicted usage of storage capacity for the storage device based on the historical feature and a predictor for predicting a usage of storage capacity; and updating the predictor by comparing the historical usage of storage capacity with the predicted usage of storage capacity. Therefore, such techniques can accurately predict the usage of storage capacity for the storage device.