Abstract: Methods, systems, and devices for dynamic channel mapping for a memory system are described. In one example, the memory system may include a memory device having a first set of pins that are associated with a channel, and a host device, coupled with the memory device, having a second set of pins that are associated with the channel. The host device may include a controller configured to receive signaling from the memory device for a channel mapping operation, determine a channel mapping (e.g., a mapping of pins, a mapping between pins of the channel and information positions of the channel) based at least in part on the received signaling, and communicate information with the memory device via the channel based at least in part on the determined channel mapping.

Abstract: A method for resource allocation in a storage system, the method may include determining to reduce a load imposed on a compute core of the storage system, wherein the compute core is responsible for executing (a) one or more background task shards, and (b) at least one non-sharded task for responding to an input/output (I/O) request sent to the storage system; and reducing the load imposed on the compute core by reallocating at least one background task shard of the one or more background task shards to another compute core of the storage system.

Abstract: A distributed storage system including memory hosts and at least one curator in communication with the memory hosts. Each memory host has memory, and the curator manages striping of data across the memory hosts. In response to a memory access request by a client in communication with the memory hosts and the curator, the curator provides the client a file descriptor mapping data stripes and data stripe replications of a file on the memory hosts for remote direct memory access of the file on the memory hosts.

Abstract: An operating method of a memory system that includes a memory device including a plurality of planes and a plurality of page buffers for the plurality of planes, respectively, and a controller suitable for controlling the memory device, the operating method includes: providing, by the controller, the memory device with page read commands for respective target planes among the plurality of planes; simultaneously reading, by the memory device, data from the target planes and buffering the data in target page buffers corresponding to the respective target planes in response to the page read commands; selectively providing, by the controller, the memory device with an all-plane data output command or respective-plane data output commands from which target page addresses are omitted; and sequentially outputting, by the memory device, the data buffered in the target page buffers, in response to the all-plane data output command or the respective-plane data output commands.

Abstract: A computing device including a processing module configured to receive a read request for a read threshold number of encoded data slices of the set of encoded data slices, determine whether a read threshold number of encoded data slices of the set of encoded data slices is available in a set of storage units associated with a first storage site and when a read threshold number of encoded data slices of the set of encoded data slices is not available in the set of storage units associated with a first storage site, transmit a read request for a read threshold number of encoded data slices to the set of storage units associated with a second storage site.

Abstract: A data storage device includes a memory device including multiple memory blocks corresponding to multiple sub-regions and a memory controller. The memory controller updates content of a read count table in response to a read command with a transfer length greater than 1 for designating more than one logical address to be read. The read count table includes multiple fields recording a read count associated with one sub-region and content of the read count table is updated by increasing the read count(s) associated with the sub-region(s) that logical addresses designated in the read command belong to. The memory controller selects at least one sub-region according to the content of the read count table and performs a data rearrangement procedure to move data of the logical addresses belonging to the selected at least one sub-region to a first memory space of the memory device having continuous physical addresses.

Abstract: An apparatus including a plurality of set arbitration circuits and a die arbitration circuit. The set arbitration circuits may each be configured to receive first commands and second commands and comprise a bank circuit configured to queue bank data in response to client requests and a set arbitration logic configured to queue the second commands in response to the bank data. The die arbitration circuit may be configured to receive the commands from the set arbitration circuits and comprise a die-bank circuit configured to queue die data in response to the client requests and a die arbitration logic configured to queue the second commands in response to the die data. Queuing the bank data and the die data for the second commands may maintain an order of the client requests and prioritize the first commands corresponding to a current controller over the first commands corresponding to a non-current controller.

Abstract: A method is used in host-based caching. A host receives a request for data, and identifies a host in a plurality of hosts that owns the data.

Abstract: An apparatus and/or system is described including a memory device or a controller for the memory device to perform heating of the memory device. In embodiments, a controller is to receive a temperature of the memory device and determine that the temperature is below a threshold temperature. In embodiments, the controller activates a heater for one or more memory die to assist the memory device in moving the temperature towards the threshold temperature, to assist the memory device when reading data. In embodiments, the heater comprises a plurality of conductive channels included in the one or more memory die or other on-board heater. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a semiconductor apparatus may include technology to determine if a threshold is met based on runtime memory usage, and enable foreground memory deduplication if the threshold is determined to be met. Other embodiments are disclosed and claimed.

Abstract: A technique involves determining, in redundant array of independent disks (RAID) stripes, source slices for restriping, and allocating, from a reserved capacity for file system check (FSCK), destination slices for restriping. The technique further involves performing restriping for the RAID stripes by copying data in the source slices into the destination slices. Accordingly, using the reserved capacity for FSCK as the destination slices for restriping may mitigate the influence on an available capacity of a mapper during restriping, thereby improving the performance of a storage system.

Abstract: This document describes techniques for storing virtual disk payload data. In an exemplary configuration, each virtual disk extent can be associated with state information that indicates whether the virtual disk extent is described by a virtual disk file. Under certain conditions the space used to describe a virtual disk extent can be reclaimed and state information can be used to determine how read and/or write operations directed to the virtual disk extent are handled. In addition to the foregoing, other techniques are described in the claims, figures, and detailed description of this document.

Abstract: An apparatus comprises capability checking circuitry 86 to perform a capability validity checking operation to determine whether use of a capability satisfies one or more use-limiting conditions. The capability comprises a pointer and pointer-use-limiting information specifying the one or more use-limiting conditions. The one or more use-limiting conditions comprise at least an allowable range of addresses for the pointer. In response to a capability write request requesting that a capability is written to a memory location associated with a capability write target address, when capability write address tracking is enabled, capability write address tracking circuitry 200 updates a capability write address tracking structure 100 based on the capability write target address.

Abstract: A system for estimating one or more data storage parameters and/or statistics in a data storage system is presented. The data storage system includes a plurality of storage containers. The system includes a snapshot module, a container stats aggregator, a synchronization module, a global stats aggregator, and storage stats estimator.

Abstract: A memory system includes a first memory that is nonvolatile, a second memory that is volatile, and a memory controller. The memory controller is configured to store first information in the second memory. The first information includes management information. The memory controller is further configured to compress the first information. The compressed first information is second information. The memory controller is configured to store the second information in the first memory.

Abstract: Systems and methods for performing backup operations and other secondary copy operations for mail servers, such as Exchange servers, are described. In some cases, the systems and methods perform multi-streaming backup and other copy operations using a single mailbox agent, which launches backup streams via a coordinator that determines when to launch streams, at what mailboxes (or folders) to launch the streams, and so on. The coordinator communicates with controllers at different machines (e.g., servers) to be backed up, and may assign streams, mailboxes, and so on, to the different controllers, which perform the backup operations for their assigned mailboxes and/or clients.

Abstract: A hybrid addressing scheme in which a maximum of three codeword groups are utilized across pairs of memory dice and/or access rows of the memory sub-system or memory device is provided. By controlling the arrangement of such codewords, it can be possible to group codewords such that disturb effects can be reduced. For example, codewords can be grouped in a symmetrical manner with respect to the memory dice of a memory device, which can allow for simplified codeword addressing.

Abstract: Features are disclosed for forecasting a usage of a block storage volume with a first configuration by a user. A computing device can forecast the usage of the block storage volume based on the historical usage of the block storage volume by the user. The computing device can determine additional potential configurations of the block storage volume. The computing device can further simulate the additional potential configurations of the block storage volume based on the forecasted usage of the block storage volume. The additional potential configurations may include a volume type, a volume size, or other volume characteristics. Based on the simulations of the additional potential configurations, the computing device may determine a recommended configuration. The computing device can dynamically modify the block storage volume based on the recommended configuration of the block storage volume.

Abstract: Techniques performed by a computing device of storing data in a data storage system are provided. A method includes (a) storing references to write commands within entries of a first chained hash table (CHT), the first CHT being pointed to by a first data structure representative of a logical disk; (b) keeping track of a load factor of the first CHT during operation; and (c) in response to determining that the load factor of the first CHT has transitioned outside of predetermined bounds: (1) creating a second CHT and a second data structure representative of the logical disk, the second CHT being pointed to by the second data structure; (2) linking the second data structure to the first data structure via a linked list; and (3) storing references to new write commands directed at the logical disk within entries of the second CHT rather than the first CHT.

Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.