Patents Examined by Charles Rones
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Patent number: 11625191Abstract: An apparatus and/or system is described including a memory device or a controller for the memory device to perform heating of the memory device. In embodiments, a controller is to receive a temperature of the memory device and determine that the temperature is below a threshold temperature. In embodiments, the controller activates a heater for one or more memory die to assist the memory device in moving the temperature towards the threshold temperature, to assist the memory device when reading data. In embodiments, the heater comprises a plurality of conductive channels included in the one or more memory die or other on-board heater. Other embodiments are disclosed and claimed.Type: GrantFiled: January 31, 2020Date of Patent: April 11, 2023Assignee: Intel CorporationInventors: Arash Hazeghi, Pranav Kalavade, Rohit Shenoy, Krishna Parat
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Patent number: 11625167Abstract: An embodiment of a semiconductor apparatus may include technology to determine if a threshold is met based on runtime memory usage, and enable foreground memory deduplication if the threshold is determined to be met. Other embodiments are disclosed and claimed.Type: GrantFiled: November 16, 2018Date of Patent: April 11, 2023Assignee: Intel CorporationInventors: Dujian Wu, Yuping Yang, Donggui Yin
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Patent number: 11620080Abstract: A technique involves determining, in redundant array of independent disks (RAID) stripes, source slices for restriping, and allocating, from a reserved capacity for file system check (FSCK), destination slices for restriping. The technique further involves performing restriping for the RAID stripes by copying data in the source slices into the destination slices. Accordingly, using the reserved capacity for FSCK as the destination slices for restriping may mitigate the influence on an available capacity of a mapper during restriping, thereby improving the performance of a storage system.Type: GrantFiled: August 17, 2020Date of Patent: April 4, 2023Assignee: EMC IP Holding Company LLCInventors: Jian Gao, Yousheng Liu, Xinlei Xu
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Patent number: 11614873Abstract: This document describes techniques for storing virtual disk payload data. In an exemplary configuration, each virtual disk extent can be associated with state information that indicates whether the virtual disk extent is described by a virtual disk file. Under certain conditions the space used to describe a virtual disk extent can be reclaimed and state information can be used to determine how read and/or write operations directed to the virtual disk extent are handled. In addition to the foregoing, other techniques are described in the claims, figures, and detailed description of this document.Type: GrantFiled: July 28, 2016Date of Patent: March 28, 2023Assignee: Microsoft Technology Licensing, LLCInventors: John A. Starks, Dustin L. Green, Todd William Harris, Mathew John, Senthil Rajaram, Karan Mehra, Neal R. Christiansen, Chung Lang Dai
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Patent number: 11609863Abstract: An apparatus comprises capability checking circuitry 86 to perform a capability validity checking operation to determine whether use of a capability satisfies one or more use-limiting conditions. The capability comprises a pointer and pointer-use-limiting information specifying the one or more use-limiting conditions. The one or more use-limiting conditions comprise at least an allowable range of addresses for the pointer. In response to a capability write request requesting that a capability is written to a memory location associated with a capability write target address, when capability write address tracking is enabled, capability write address tracking circuitry 200 updates a capability write address tracking structure 100 based on the capability write target address.Type: GrantFiled: June 24, 2020Date of Patent: March 21, 2023Assignee: Arm LimitedInventors: Matthias Lothar Boettcher, François Christopher Jacques Botman
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Patent number: 11609834Abstract: A system for estimating one or more data storage parameters and/or statistics in a data storage system is presented. The data storage system includes a plurality of storage containers. The system includes a snapshot module, a container stats aggregator, a synchronization module, a global stats aggregator, and storage stats estimator.Type: GrantFiled: December 14, 2020Date of Patent: March 21, 2023Assignee: Druva Inc.Inventors: Anand Apte, Milind Vithal Borate, Pinkesh Bardiya, Prahlad Nishal, Yogendra Acharya
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Patent number: 11609844Abstract: A memory system includes a first memory that is nonvolatile, a second memory that is volatile, and a memory controller. The memory controller is configured to store first information in the second memory. The first information includes management information. The memory controller is further configured to compress the first information. The compressed first information is second information. The memory controller is configured to store the second information in the first memory.Type: GrantFiled: March 2, 2020Date of Patent: March 21, 2023Assignee: KIOXIA CORPORATIONInventors: Keiri Nakanishi, Konosuke Watanabe, Kohei Oikawa, Daisuke Iwai
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Patent number: 11609826Abstract: Systems and methods for performing backup operations and other secondary copy operations for mail servers, such as Exchange servers, are described. In some cases, the systems and methods perform multi-streaming backup and other copy operations using a single mailbox agent, which launches backup streams via a coordinator that determines when to launch streams, at what mailboxes (or folders) to launch the streams, and so on. The coordinator communicates with controllers at different machines (e.g., servers) to be backed up, and may assign streams, mailboxes, and so on, to the different controllers, which perform the backup operations for their assigned mailboxes and/or clients.Type: GrantFiled: June 15, 2021Date of Patent: March 21, 2023Assignee: Commvault Systems, Inc.Inventors: Christopher A. Alonzo, Jun H. Ahn, Manas Bhikchand Mutha, Vipul Pawale
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Patent number: 11604725Abstract: A hybrid addressing scheme in which a maximum of three codeword groups are utilized across pairs of memory dice and/or access rows of the memory sub-system or memory device is provided. By controlling the arrangement of such codewords, it can be possible to group codewords such that disturb effects can be reduced. For example, codewords can be grouped in a symmetrical manner with respect to the memory dice of a memory device, which can allow for simplified codeword addressing.Type: GrantFiled: August 31, 2020Date of Patent: March 14, 2023Assignee: Micron Technology, INC.Inventor: Reshmi Basu
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Patent number: 11592989Abstract: Features are disclosed for forecasting a usage of a block storage volume with a first configuration by a user. A computing device can forecast the usage of the block storage volume based on the historical usage of the block storage volume by the user. The computing device can determine additional potential configurations of the block storage volume. The computing device can further simulate the additional potential configurations of the block storage volume based on the forecasted usage of the block storage volume. The additional potential configurations may include a volume type, a volume size, or other volume characteristics. Based on the simulations of the additional potential configurations, the computing device may determine a recommended configuration. The computing device can dynamically modify the block storage volume based on the recommended configuration of the block storage volume.Type: GrantFiled: November 25, 2020Date of Patent: February 28, 2023Assignee: Amazon Technologies, Inc.Inventors: Mohit Gupta, Letian Feng, Leslie Johann Lamprecht
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Patent number: 11593266Abstract: Techniques performed by a computing device of storing data in a data storage system are provided. A method includes (a) storing references to write commands within entries of a first chained hash table (CHT), the first CHT being pointed to by a first data structure representative of a logical disk; (b) keeping track of a load factor of the first CHT during operation; and (c) in response to determining that the load factor of the first CHT has transitioned outside of predetermined bounds: (1) creating a second CHT and a second data structure representative of the logical disk, the second CHT being pointed to by the second data structure; (2) linking the second data structure to the first data structure via a linked list; and (3) storing references to new write commands directed at the logical disk within entries of the second CHT rather than the first CHT.Type: GrantFiled: July 27, 2021Date of Patent: February 28, 2023Assignee: EMC IP Holding Company LLCInventors: Vladimir Shveidel, Geng Han, Xinlei Xu
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Patent number: 11586357Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.Type: GrantFiled: May 27, 2021Date of Patent: February 21, 2023Assignee: Micron Technology, Inc.Inventors: Kishore K. Muchherla, Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Sampath K. Ratnam, Renato C. Padilla, Peter Feeley
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Patent number: 11588498Abstract: According to one embodiment, a buffer stores first hash values and first complementary data. A first conversion unit converts consecutive characters in a second character string into second hash values and second complementary data. A search unit searches for consecutive first hash values from the buffer, and output a pointer. A selection unit selects consecutive first hash values and pieces of first complementary data from the buffer. A second conversion unit converts the consecutive first hash values into a third character string using the pieces of first complementary data. A comparison unit compares the second character string with the third character string to acquire a matching length. An output unit output the matching length with the pointer.Type: GrantFiled: September 10, 2021Date of Patent: February 21, 2023Assignee: Kioxia CorporationInventors: Daisuke Yashima, Kohei Oikawa, Sho Kodama, Keiri Nakanishi, Masato Sumiyoshi, Youhei Fukazawa, Zheye Wang, Takashi Miura
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Patent number: 11586393Abstract: A control method for a flash memory, a flash memory die and the flash memory are provided. The control method includes: in a setup stage, under an operation mode of a command input, issuing by a host a setup command to map each port of an external data bus of each flash memory die respectively to a status index of each flash memory die; and in a request stage, under the operation mode of the command input, issuing by the host a request command to each flash memory die, and under the operation mode of a data output, a status of the status index of each flash memory die is transmitted to the host through the ports of the external data bus respectively.Type: GrantFiled: December 30, 2020Date of Patent: February 21, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Shih Chou Juan, Min Zhi Ji
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Patent number: 11579810Abstract: The present application relates to a semiconductor memory training method and related devices, belonging to the technical field of semiconductors. The method comprises: obtaining a stored historical training result of a semiconductor memory, the historical training result comprising a historical expected delay value and a historical expected voltage; setting a delay threshold and a current training voltage range, the delay threshold being less than or equal to the historical expected delay value, the current training voltage range comprising the historical expected voltage; obtaining a current minimum delay value for the semiconductor memory under the historical expected voltage; and using the stored historical training result as a current training result of the semiconductor memory, if the current minimum delay value for the semiconductor memory under the historical expected voltage is no less than the delay threshold.Type: GrantFiled: March 9, 2021Date of Patent: February 14, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Guangteng Long, Xiaofeng Xu, Yang Wang, Peng Wang
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Patent number: 11579979Abstract: Devices and techniques for a storage backed memory package save trigger are disclosed herein. Data can be received via a first interface. The data is stored in a volatile portion of the memory package. Here, the memory package includes a second interface arranged to connect a host to a controller in the memory package. A reset signal can be received at the memory package via the first interface. The data stored in the volatile portion of the memory package can be saved to a non-volatile portion of the memory package in response to the reset signal.Type: GrantFiled: July 22, 2021Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventors: James E. Dunn, Nathan A. Eckel
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Patent number: 11579195Abstract: A method for performing verification and testing of a device under test (DUT) is described. The method includes receiving, by a processing device, inputs from a user regarding a hardware design for the DUT. The processing device presents cover group attribute suggestions to the user based on the hardware design and receives cover group information from the user corresponding to one or more cover group attributes of one or more cover groups based on the cover group attribute suggestions. Based on the cover group information, the processing device automatically generates verification code, including one or more cover group definitions.Type: GrantFiled: August 7, 2019Date of Patent: February 14, 2023Assignee: MICRON TECHNOLOGY, INC.Inventors: Benjamin Ting, Alon Shtepel, Isaac Kim
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Patent number: 11573909Abstract: An apparatus, system, and method are disclosed for efficiently managing commands in a solid-state storage device that includes a solid-state storage arranged in two or more banks. Each bank is separately accessible and includes two or more solid-state storage elements accessed in parallel by a storage input/output bus. The solid-state storage includes solid-state, non-volatile memory. The solid-state storage device includes a bank interleave that directs one or more commands to two or more queues, where the one or more commands are separated by command type into the queues. Each bank includes a set of queues in the bank interleave controller. Each set of queues includes a queue for each command type. The bank interleave controller coordinates among the banks execution of the commands stored in the queues, where a command of a first type executes on one bank while a command of a second type executes on a second bank.Type: GrantFiled: June 9, 2021Date of Patent: February 7, 2023Assignee: Unification Technologies LLCInventors: David Flynn, Bert Lagerstedt, John Strasser, Jonathan Thatcher, Michael Zappe
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Patent number: 11573714Abstract: Compressibility instrumented dynamic volume provisioning is disclosed. For example, a plurality of storage pools includes first and second storage pools, and is managed by a storage controller that receives a request to provision a first persistent storage volume associated with a first container, where the first storage pool has a first storage configuration including a deduplication setting, a compression setting, and/or an encryption setting. The first persistent storage volume is created in the first storage pool based on a first storage mode stored in metadata associated with the first container, where the storage mode includes a deduplication mode, a compression mode, and/or an encryption mode. A second persistent storage volume is in the second storage pool with a second storage configuration different from the first storage configuration based on a second storage mode associated with a second container.Type: GrantFiled: March 29, 2021Date of Patent: February 7, 2023Assignee: Red Hat, Inc.Inventor: Huamin Chen
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Patent number: 11573732Abstract: A memory system includes a storage device including a turbo write buffer and a user storage area implemented with a nonvolatile memory, and a host configured to transfer a read request to the storage device. In response to the read request, the storage device transfers read data and read data information including attributes of the read data to the host.Type: GrantFiled: June 15, 2020Date of Patent: February 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Woo Kim, Songho Yoon, Jeong-Woo Park, Dong-Min Kim, Kyoung Back Lee