Patents Examined by Cheng-Yuan Tseng
  • Patent number: 11226921
    Abstract: An adaptive interface high availability storage device. In some embodiments, the adaptive interface high availability storage device includes: a rear storage interface connector; a rear multiplexer, connected to the rear storage interface connector; an adaptable circuit connected to the rear multiplexer; a front multiplexer, connected to the adaptable circuit; and a front storage interface connector, connected to the front multiplexer. The adaptive interface high availability storage device may be configured to operate in a single-port state or in a dual-port state. The adaptive interface high availability storage device may be configured: in the single-port state, to present a single-port host side storage interface according to a first storage protocol at the rear storage interface connector, and in the dual-port state, to present a dual-port host side storage interface according to the first storage protocol at the rear storage interface connector.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: January 18, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sompong Paul Olarig
  • Patent number: 11226818
    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to operational units for use as operands. A promotion unit optionally increases date element data size by an integral power of 2 either zero filing or sign filling the additional bits. A decimation unit optionally decimates data elements by an integral factor of 2. For ease of implementation the promotion factor must be greater than or equal to the decimation factor.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: January 18, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Joseph Zbiciak
  • Patent number: 11221849
    Abstract: Disclosed embodiments relate to executing a vector multiplication instruction. In one example, a processor includes fetch circuitry to fetch the vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier, decode circuitry to decode the fetched instruction, execution circuitry to, on each of a plurality of corresponding pairs of fixed-sized elements of the identified first and second sources, execute the decoded instruction to generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size, and generate an unsigned fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Venkateswara R. Madduri, Carl Murray, Elmoustapha Ould-Ahmed-Vall, Mark J. Charney, Robert Valentine, Jesus Corbal
  • Patent number: 11221850
    Abstract: A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: January 11, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce C. Giamei, Martin Recktenwald, Donald W. Schmidt, Timothy Siegel, Aditya N. Puranik, Mark S. Farrell, Christian Jacobi, Jonathan D. Bradbury, Christian Zoellin
  • Patent number: 11216274
    Abstract: A computer comprising one or more processors and memory may implement an atomic compare and swap (CAS) operation on multiple data elements. Each data element has a corresponding descriptor which includes a new value and a reference to a controlling descriptor for the CAS operation. The controlling descriptor includes a status value which indicates whether the CAS operation is in progress or has completed. The operation first allocates memory locations of the data elements by writing addresses of respective descriptors to the memory locations using CAS instructions. The operation then writes successful status to the status value of the controlling descriptor to indicate that the respective memory locations are no longer allocated. The operation then returns an indicator of successful completion without atomically updating the memory locations with the new values. Extensions are further described to implement CAS operations in non-volatile random access memories.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: January 4, 2022
    Assignee: Oracle International Corporation
    Inventors: Virendra J. Marathe, Alex Kogan, Mihail-Igor Zablotchi
  • Patent number: 11210240
    Abstract: System and method for improved transferring of data involving memory device systems. A memory appliance (MA) comprising a plurality of memory modules is configured to store data within the plurality of memory modules and further configured to receive data commands from the first server and a second server coupled to the MA. The data commands may include direction memory access commands such that the MA can service the data commands while bypassing a host controller of the MA.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: December 28, 2021
    Assignee: Rambus Inc.
    Inventors: Vlad Fruchter, Keith Lowery, George Michael Uhler, Steven Woo, Chi-Ming (Philip) Yeung, Ronald Lee
  • Patent number: 11205118
    Abstract: A deep neural network (DNN) module utilizes parallel kernel and parallel input processing to decrease bandwidth utilization, reduce power consumption, improve neuron multiplier stability, and provide other technical benefits. Parallel kernel processing enables the DNN module to load input data only once for processing by multiple kernels. Parallel input processing enables the DNN module to load kernel data only once for processing with multiple input data. The DNN module can implement other power-saving techniques like clock-gating (i.e. removing the clock from) and power-gating (i.e. removing the power from) banks of accumulators based upon usage of the accumulators. For example, individual banks of accumulators can be power-gated when all accumulators in a bank are not in use, and do not store data for a future calculation. Banks of accumulators can also be clock-gated when all accumulators in a bank are not in use, but store data for a future calculation.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: December 21, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Amol Ashok Ambardekar, Chad Balling McBRIDE, George Petre, Larry Marvin Wall, Kent D. Cedola, Boris Bobrov
  • Patent number: 11205109
    Abstract: The present disclosure provides an on-chip communication system for neural network processors, a processing device, and a method for operating on an on-chip communication system. The system can include a cluster manager configured to generate a global signal, and a plurality of tile units in a tile array coupled with the cluster manager, each including two connectors and a node connected between the two connectors.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: December 21, 2021
    Assignee: Alibaba Group Holding Limited
    Inventor: Jian Chen
  • Patent number: 11200064
    Abstract: Methods and parallel processing units for avoiding inter-pipeline data hazards wherein inter-pipeline data hazards are identified at compile time. For each identified inter-pipeline data hazard the primary instruction and secondary instruction(s) thereof are identified as such and are linked by a counter which is used to track that inter-pipeline data hazard. Then when a primary instruction is output by the instruction decoder for execution the value of the counter associated therewith is adjusted (e.g. incremented) to indicate that there is hazard related to the primary instruction, and when primary instruction has been resolved by one of multiple parallel processing pipelines the value of the counter associated therewith is adjusted (e.g. decremented) to indicate that the hazard related to the primary instruction has been resolved.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: December 14, 2021
    Assignee: Imagination Technologies Limited
    Inventors: Luca Iuliano, Simon Nield, Yoong-Chert Foo, Ollie Mower
  • Patent number: 11194743
    Abstract: A method of accessing a dual line solid-state drive (SSD) device through a network interface and a PCIe EP simultaneously. The method includes: (1) establishing, by the dual line SSD device, a connection with a remote server through the network interface, (2) establishing, by the remote server, an administrative queue with the dual line SSD device, (3) establishing, by the remote server, an input/output queue with the dual line SSD device by posting a command in the administrative queue over the network interface to initiate transfer of data, (4) establishing, by the dual line SSD device, a connection with a local server over the PCIe EP, (5) establishing, by the local server, the administrative queue over the PCIe EP, and (6) establishing, by the local server, the input/output queue by posting the command in the administrative queue over the PCIe EP to initiate transfer of the data.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: December 7, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Anil Desmal Solanki, Venkataratnam Nimmagadda, Prashant Vishwanath Mahendrakar
  • Patent number: 11194576
    Abstract: The present disclosure relates to A method of automating a process to process a task or an object comprising: defining elements of the process in one or more human-intelligible and editable and machine interpretable workflow program documents, the workflow program documents each including a plurality of actors who perform actions or take decision, a sequence of action steps each associated with an actor and having at least one expected outcome and a corresponding next step for each expected outcome, and wherein the action steps may include a first type of action further defined within the workflow program documents and a second type of action implemented by a computer according to code defined other than in said workflow program documents; and executing the process by a processor running the code defined by the workflow program documents, wherein if an exception is detected in the processing of a task or object according to the code, the exception is passed to a supervisory function to perform a remedial acti
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: December 7, 2021
    Inventors: Tielman Francois Botha, Dawid Eduard Botha, Philip Viljoen
  • Patent number: 11194575
    Abstract: Provided is a method, computer program product, and system for performing data address prediction. The method comprises receiving a first instruction for execution by a processor. A load address predictor (LAP) accesses a LAP table entry for a section of an instruction cache. The section is associated with a plurality of instructions that includes the first instruction. The LAP predicts a set of data addresses that will be loaded using the LAP table entry. The method further comprises sending a recommendation to prefetch the set of data addresses to a load-store unit (LSU).
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: December 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Mohit Karve, Naga P. Gorti, Edmund Joseph Gieske
  • Patent number: 11188329
    Abstract: Systems, apparatuses, and methods related to dynamic precision bit string accumulation are described. Dynamic bit string accumulation can be performed using an edge computing device. In an example method, dynamic precision bit string accumulation can include performing an iteration of a recursive operation using a first bit string and a second bit string and determining that a result of the iteration of the recursive operation contains a quantity of bits in a particular bit sub-set of the result that is greater than a threshold quantity of bits associated with the particular bit sub-set. The method can further include writing a result of the iteration of the recursive operation to a first register and writing at least a portion of the bits associated with the particular bit sub-set of the result to a second register.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: November 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Vijay S. Ramesh, Richard C. Murphy
  • Patent number: 11182320
    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: November 23, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta, Robert Michael Johnson, Mark Bradley Davis, Christopher Joseph Pettey, Nafea Bshara, Erez Izenberg
  • Patent number: 11175957
    Abstract: The present disclosure relates to a hardware accelerator for executing a computation task composed of a set of operations. The hardware accelerator comprises a controller and a set of computation units. Each computation unit of the set of computation units is configured to receive input data of an operation of the set of operations and to perform the operation, wherein the input data is represented with a distinct bit length associated with each computation unit. The controller is configured to receive the input data represented with a certain bit length of the bit lengths and to select one of the set of computation units that can deliver a valid result and that is associated with a bit length smaller than or equal to the certain bit length.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dionysios Diamantopoulos, Florian Michael Scheidegger, Adelmo Cristiano Innocenza Malossi, Christoph Hagleitner, Konstantinos Bekas
  • Patent number: 11169801
    Abstract: A hybrid quantum classical (HQC) computer, which includes both a classical computer component and a quantum computer component, solves linear systems. The HQC decomposes the linear system to be solved into subsystems that are small enough to be solved by the quantum computer component, under control of the classical computer component. The classical computer component synthesizes the outputs of the quantum computer component to generate the complete solution to the linear system.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 9, 2021
    Assignee: Zapata Computing, Inc.
    Inventor: Yudong Cao
  • Patent number: 11157283
    Abstract: A graphics processing device comprises a set of compute units to execute multiple threads of a workload, a cache coupled with the set of compute units, and a prefetcher to prefetch instructions associated with the workload. The prefetcher is configured to use a thread dispatch command that is used to dispatch threads to execute a kernel to prefetch instructions, parameters, and/or constants that will be used during execution of the kernel. Prefetch operations for the kernel can then occur concurrently with thread dispatch operations.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: James Valerio, Vasanth Ranganathan, Joydeep Ray, Pradeep Ramani
  • Patent number: 11157285
    Abstract: A system and method including a processor configured to, based on encountering an instruction that does not modify the architectural state of the processor, preferably a prefetch instruction, that is being executed by the processor, determine whether utilization of a first queue used in processing the instruction is over a first queue utilization limit; in response to the first queue utilization being over the first queue utilization limit, do not execute the prefetch instruction; and in response to the first queue utilization being under the first queue utilization limit, at least partially process the prefetch instruction.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: October 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Bryant Cockcroft, John A. Schumann, Karen Yokum, Vivek Britto, Debapriya Chatterjee
  • Patent number: 11151064
    Abstract: A computing device includes a memory and a processor connected to the memory and configured to: create, in a first memory space of the memory, a first I/O submission queue associated with a first application running in user space; create, in a second memory space of the memory, a second I/O submission queue associated with a second application running in user space; in response to a first I/O request from the first application, store the first I/O request in the first I/O submission queue for access by the semiconductor storage device; and in response to a second I/O request from the second application, store the second I/O request in the second I/O submission queue for access by the semiconductor storage device.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: October 19, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Hideki Yoshida
  • Patent number: 11126438
    Abstract: In one embodiment, a reservation station of a processor includes: a plurality of first lanes having a plurality of entries to store information for instructions having in-order dependencies; a variable latency tracking table including a second plurality of entries to store information for instructions having a variable latency; and a scheduler circuit to access a head entry of the plurality of first lanes to schedule, for execution on at least one execution unit, at least one instruction from the head entry of at least one of the plurality of first lanes. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation
    Inventors: Srikanth Srinivasan, Thomas Mullins, Ammon Christiansen, James Hadley, Robert S. Chappell, Sean Mirkes