Patents Examined by Cheng-Yuan Tseng
  • Patent number: 10853605
    Abstract: A barcode reader system includes a barcode reader, a docking station, and a magnet. The barcode reader includes a housing and a first mating structure connected to the housing. The docking station includes a second mating structure to mate with the first mating structure. The second mating structure and the first mating structure are capable of forming a coupling between the barcode reader and the docking station. The magnet produces magnetic forces that strengthen the coupling between the barcode reader and the docking station. The docking station may include the magnet. The barcode reader may include a magnetic field detector and may enter a presentation mode in response to the magnetic field detector detecting a magnetic field.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: December 1, 2020
    Assignee: The Code Corporation
    Inventors: Isaac Atkinson, Phil Utykanski
  • Patent number: 10853075
    Abstract: An electronic device handles accesses of a branch prediction functional block when executing instructions in program code. The electronic device includes a processor having the branch prediction functional block that provides branch prediction information for control transfer instructions (CTIs) in the program code and a minimum predictor use (MPU) functional block. The MPU functional block determines, based on a record associated with a given fetch group of instructions, that a specified number of subsequent fetch groups of instructions that were previously determined to include no CTIs or conditional CTIs that were not taken are to be fetched for execution in sequence following the given fetch group. The MPU functional block then, when each of the specified number of the subsequent fetch groups is fetched and prepared for execution, prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that subsequent fetch group.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: December 1, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Varun Agrawal, John Kalamatianos, Adithya Yalavarti, Jingjie Qian
  • Patent number: 10845868
    Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: November 24, 2020
    Assignee: Apple Inc.
    Inventors: Karan Sanghi, Saurabh Garg, Haining Zhang
  • Patent number: 10838897
    Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Richard C. Murphy, Elliott C. Cooper-Balis
  • Patent number: 10831503
    Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce C. Giamei, Martin Recktenwald, Donald W. Schmidt, Timothy Slegel, Aditya N. Puranik, Mark S. Farrell, Christian Jacobi, Jonathan D. Bradbury, Christian Zoellin
  • Patent number: 10831478
    Abstract: A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce C. Giamei, Martin Recktenwald, Donald W. Schmidt, Timothy Slegel, Aditya N. Puranik, Mark S. Farrell, Christian Jacobi, Jonathan D. Bradbury, Christian Zoellin
  • Patent number: 10824424
    Abstract: A computer comprising one or more processors and memory may implement an atomic compare and swap (CAS) operation on multiple data elements. Each data element has a corresponding descriptor which includes a new value and a reference to a controlling descriptor for the CAS operation. The controlling descriptor includes a status value which indicates whether the CAS operation is in progress or has completed. The operation first allocates memory locations of the data elements by writing addresses of respective descriptors to the memory locations using CAS instructions. The operation then writes successful status to the status value of the controlling descriptor to indicate that the respective memory locations are no longer allocated. The operation then returns an indicator of successful completion without atomically updating the memory locations with the new values. Extensions are further described to implement CAS operations in non-volatile random access memories.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: November 3, 2020
    Assignee: Oracle International Corporation
    Inventors: Virendra J. Marathe, Alex Kogan, Mihail-Igor Zablotchi
  • Patent number: 10817301
    Abstract: Methods and parallel processing units for avoiding inter-pipeline data hazards wherein inter-pipeline data hazards are identified at compile time. For each identified inter-pipeline data hazard the primary instruction and secondary instruction(s) thereof are identified as such and are linked by a counter which is used to track that inter-pipeline data hazard. Then when a primary instruction is output by the instruction decoder for execution the value of the counter associated therewith is adjusted (e.g. incremented) to indicate that there is hazard related to the primary instruction, and when primary instruction has been resolved by one of multiple parallel processing pipelines the value of the counter associated therewith is adjusted (e.g. decremented) to indicate that the hazard related to the primary instruction has been resolved.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: October 27, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Luca Iuliano, Simon Nield, Yoong-Chert Foo, Ollie Mower
  • Patent number: 10802574
    Abstract: A semiconductor device is provided. The semiconductor device includes a receptacle which comprises a plurality of pins according to a universal serial bus (USB) type-C receptacle interface and a power delivery integrated circuit (PD IC) which transmits a toggle voltage signal that toggles between a first voltage level and a second voltage level to a first pin among the pins and detects a voltage level of a signal output from the first pin.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: October 13, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je Kook Kim, Sung Ha Park
  • Patent number: 10795836
    Abstract: The performance of a neural network (NN) and/or deep neural network (DNN) can limited by the number of operations being performed as well as management of data among the various memory components of the NN/DNN. Using virtualized hardware iterators, data for processing by the NN/DNN can be traversed and configured to optimize the number of operations as well as memory utilization to enhance the overall performance of a NN/DNN. Operatively, an iterator controller can generate instructions for execution by the NN/DNN representative of one more desired iterator operation types and to perform one or more iterator operations. Data can be iterated according to a selected iterator operation and communicated to one or more neuron processors of the NN/DD for processing and output to a destination memory. The iterator operations can be applied to various volumes of data (e.g., blobs) in parallel or multiple slices of the same volume.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: October 6, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chad Balling McBride, George Petre, Amol Ashok Ambardekar, Kent D. Cedola, Larry Marvin Wall, Boris Bobrov
  • Patent number: 10795843
    Abstract: A system includes a fabric switch including a motherboard, a baseboard management controller (BMC), a network switch configured to transport network signals, and a PCIe switch configured to transport PCIe signals; a midplane; and a plurality of device ports. Each of the plurality of device ports is configured to connect a storage device to the motherboard of the fabric switch over the midplane and carry the network signals and the PCIe signals over the midplane. The storage device is configurable in multiple modes based a protocol established over a fabric connection between the system and the storage device.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: October 6, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sompong Paul Olarig, Fred Worley, Son Pham
  • Patent number: 10789182
    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
  • Patent number: 10783104
    Abstract: A memory request management system may include a memory device and a memory controller. The memory controller may include a read queue, a write queue, an arbitration circuit, a read credit allocation circuit, and a write credit allocation circuit. The read queue and write queue may store corresponding requests from request streams. The arbitration circuit may send requests from the read queue and write queue to the memory device based on locations of addresses indicated by the requests. The read credit allocation circuit may send an indication of an available read credit to a request stream in response to a read request from the request stream being sent from the read queue to the memory device. The write credit allocation circuit may send an indication of an available write credit to a request stream in response to a write request from the request stream being stored at the write queue.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: September 22, 2020
    Assignee: Apple Inc.
    Inventors: Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Sukulpa Biswas
  • Patent number: 10776116
    Abstract: An instruction translation circuit, a processor circuit, and an executing method thereof are provided. The instruction translation circuit is adapted for being disposed in the processor circuit. The instruction translation circuit includes a formatted instruction queue, a first instruction translator, an instruction detection circuit, and a second instruction translator. The formatted instruction queue stores a plurality of formatted macro instructions. The first instruction translator translates a first formatted macro instruction of the formatted macro instructions and outputs a first micro instruction. When the instruction detection circuit determines that a trap bit in the first formatted macro instruction is set and a part of the first formatted macro instruction can be translated in advance, the instruction detection circuit outputs first trap information.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 15, 2020
    Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Chenchen Song, Xiaolong Fei, Aimin Ling, Yingbing Guan
  • Patent number: 10768938
    Abstract: A data processing system provides a branch forward instruction (BF) which has programmable parameters specifying a branch target address to be branched to and a branch point identifying a program instruction following the branch forward instruction which, when reached, is followed by a branch to the branch target address.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: September 8, 2020
    Assignee: ARM Limited
    Inventors: Thomas Christopher Grocutt, Richard Roy Grisenthwaite, Simon John Craske, François Christopher Jacques Botman, Bradley John Smith
  • Patent number: 10761848
    Abstract: Systems and methods for implementing an integrated circuit with core-level predication includes: a plurality of processing cores of an integrated circuit, wherein each of the plurality of cores includes: a predicate stack defined by a plurality of single-bit registers that operate together based on one or more of logical connections and physical connections of the plurality of single-bit registers, wherein: the predicate stack of each of the plurality of processing cores includes a top of stack single-bit register of the plurality of single-bit registers having a bit entry value that controls whether select instructions to the given processing core of the plurality of processing cores is executed.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: September 1, 2020
    Assignee: quadric.io, Inc.
    Inventors: Nigel Drego, Ananth Durbha, Aman Sikka, Mrinalini Ravichandran, Daniel Firu, Veerbhan Kheterpal
  • Patent number: 10762009
    Abstract: A data processing system includes: a first memory system coupled to a host through a first external channel, a second memory system coupled to the host through a second external channel, and an internal channel suitable for coupling the first and second memory systems with each other, the host, when read-requesting first and second data to the first memory system, transfers a first external channel control information for selecting sole use of the first external channel or simultaneous use of the first and second external channels, to the first and second memory systems, the first memory system, when the first external channel control information indicates simultaneous use, the first memory system outputs the first data through the first external channel and outputs the second data through the internal channel, and the second memory system outputs the second data inputted through the internal channel, through the second external channel.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: September 1, 2020
    Assignee: SK hynix Inc.
    Inventor: Hae-Gi Choi
  • Patent number: 10762032
    Abstract: An adaptive interface high availability storage device. In some embodiments, the adaptive interface high availability storage device includes: a rear storage interface connector; a rear multiplexer, connected to the rear storage interface connector; an adaptable circuit connected to the rear multiplexer; a front multiplexer, connected to the adaptable circuit; and a front storage interface connector, connected to the front multiplexer. The adaptive interface high availability storage device may be configured to operate in a single-port state or in a dual-port state. The adaptive interface high availability storage device may be configured: in the single-port state, to present a single-port host side storage interface according to a first storage protocol at the rear storage interface connector, and in the dual-port state, to present a dual-port host side storage interface according to the first storage protocol at the rear storage interface connector.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sompong Paul Olarig
  • Patent number: 10725676
    Abstract: Apparatus and method for configuring a data storage device as a write once read many (WORM) drive. In some embodiments, the storage device has a rotatable disc with at least one data recording layer, and a data transducer that is selectively moveable with respect to the rotatable disc. The data transducer has a write element configured to write data to the data recording layer, and a read element configured to read data from the data recording layer. A control circuit is configured to physically disable the write element in response to a write element disable signal. The disabling of the write element prevents further writing of data to the data recording layer. The read element remains operative to continue reading data from the data recording layer after the write element has been disabled.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: July 28, 2020
    Assignee: Seagate Technology, LLC
    Inventor: Christopher Nicholas Allo
  • Patent number: 10725783
    Abstract: According to one or more embodiments, an example computer-implemented method for executing one or more out-of-order instructions by a processing unit, includes decoding an instruction to be executed, and based on a determination that the instruction is a store instruction, identifying a split load-hit-store (LHS) table for the store instruction, wherein a LHS table of the processing unit includes multiple split LHS tables. Identifying the split LHS table includes determining, for the store instruction, a first split LHS table by performing a mod operation using one or more operands from the store instruction, and adding one or more parameters of the store instruction in the first split LHS table by generating an ITAG for the store instruction. The method further includes dispatching the store instruction for execution to an issue queue with the ITAG.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: July 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ehsan Fatehi, Richard J. Eickemeyer, Edmund J. Gieske