Abstract: Embodiments detailed herein relate to systems and methods to store a tile register pair to memory. In one example, a processor includes: decode circuitry to decode a store matrix pair instruction having fields for an opcode and source and destination identifiers to identify source and destination matrices, respectively, each matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded store matrix pair instruction to store every element of left and right tiles of the identified source matrix to corresponding element positions of left and right tiles of the identified destination matrix, respectively, wherein the executing stores a chunk of C elements of one row of the identified source matrix at a time.

Abstract: Examples described herein relate to network layer 7 (L7) offload to an infrastructure processing unit (IPU) for a service mesh. An apparatus described herein includes an IPU comprising an IPU memory to store a routing table for a service mesh, the routing table to map shared memory address spaces of the IPU and a host device executing one or more microservices, wherein the service mesh provides an infrastructure layer for the one or more microservices executing on the host device; and one or more IPU cores communicably coupled to the IPU memory, the one or more IPU cores to: host a network L7 proxy endpoint for the service mesh, and communicate messages between the network L7 proxy endpoint and an L7 interface device of the one or more microservices by copying data between the shared memory address spaces of the IPU and the host device based on the routing table.

Abstract: A circuit and corresponding method perform resource arbitration. The circuit comprises a pending arbiter (PA) that outputs a PA selection for accessing a resource. The PA selection is based on PA input. The PA input represents respective pending-state of requesters of the resource. The circuit further comprises a valid arbiter (VA) that outputs a VA selection for accessing the resource. The VA selection is based on VA input. The VA input represents respective valid-state of the requesters. The circuit performs a validity check on the PA selection output. The circuit outputs a final selection for accessing the resource by selecting, based on the validity check performed, the PA selection output or VA selection output. The circuit addresses arbitration fairness issues that may result when multiple requesters are arbitrating to be selected for access to a shared resource and such requesters require a credit (token) to be eligible for arbitration.

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address, and execution circuitry to execute the decoded instruction to store configuration information about usage of storage for two-dimensional data structures at the memory address.

Abstract: Techniques are disclosed pertaining to utilizing a communication fabric via multiple ports. An agent circuit includes a plurality of command-and-data ports that couple the agent circuit to a communication fabric coupled to a plurality of hardware components that includes a plurality of memory controller circuits that facilitate access to a memory. The agent circuit can execute an instruction that involves issuing a command for data stored at the memory. The agent circuit may perform a hash operation on a memory address associated with the command to determine which one of the plurality of memory controller circuits to which to issue the command. The agent circuit issues the command to the determined memory controller circuit on a particular one of the plurality of command-and-data ports that is designated to the memory controller circuit. The agent circuit may issue all commands destined to that memory controller circuit on that port.

Abstract: An apparatus includes a first die connected to a second die through a die-to-die (D2D) interface. The first die includes a first interconnect configured to provide first lanes communicating with the second die to the D2D interface, the first interconnect includes a first logic circuit configured to indicate a correlation between a number of chiplet dies connected to the first lanes and connected signal pins from among a plurality of signal pins of the connected chiplet dies. The second die includes the number of connected chiplet dies each including a second interconnect configured to provide second lanes to the D2D interface from each of the connected chiplet dies. The second lanes are configured to be set according to a number of the connected signal pins of the connected chiplet dies.

Abstract: This application discloses an exception handling method, which may be applied to a processor. The method includes: The processor calls a second function according to a call instruction of a first function, where the first function is a high-level language function, and the second function is a runtime function. When an exception occurs in a process of executing the second function, the processor executes a return operation of the second function, where the return operation of the second function includes restoring a status of a first register used when the second function is executed to a status before the first function calls the second function. The processor performs exception handling based on the status of the first register. The method can improve running performance of the processor.

Abstract: A hardware/software co-compressed computing method for a static random access memory (SRAM) computing-in-memory-based (CIM-based) processing unit includes performing a data dividing step, a sparsity step, an address assigning step and a hardware decoding and calculating step. The data dividing step is performed to divide a plurality of kernels into a plurality of weight groups. The sparsity step includes performing a weight setting step. The weight setting step is performed to set each of the weight groups to one of a zero weight group and a non-zero weight group. The address assigning step is performed to assign a plurality of index codes to a plurality of the non-zero weight groups, respectively. The hardware decoding and calculating step is performed to execute an inner product to the non-zero weight groups and the input feature data group corresponding to the non-zero weight groups to generate the output feature data group.

Abstract: Provided is an apparatus for accelerating graph neural network (GNN) pre-processing, the apparatus including a set-partitioning accelerator configured to sort each edge of an original graph stored in a coordinate list (COO) format by a node number, perform radix sorting based on a vertex identification (VID) to generate a COO array of a preset length, and perform uniform random sampling on some nodes of a given node array, a merger configured to merge the COO array of the preset length to generate one sorted COO array, a re-indexer configured to assign new consecutive VIDs respectively to the nodes selected through the uniform random sampling, and a compressed sparse row (CSR) converter configured to the edges sorted by the node number into a CSR format.

Abstract: A first fingerprint corresponding to a first chunk associated with a stream of data is generated. It is determined that the first fingerprint matches a second fingerprint of a plurality of fingerprints listed in at least one entry in a deduplication map associated with a plurality of storage systems. A first storage system of the plurality of storage systems is located at a first geographic location and a second storage system of the plurality of storage systems is located at a second geographic location. The first chunk corresponding to the second fingerprint is stored by at least the second storage system. In response to a determination that the first fingerprint matches the second fingerprint, it is determined to store at the first storage system a local copy of the first chunk based in part on one or more deduplication factors.

Abstract: An integrated circuit (IC) chip includes a Universal Chiplet Interconnect express (UCIe) interface circuit for transferring UCIe signals. The UCIe interface circuit includes a mainband sub-interface for transferring mainband signals and a sideband sub-interface for transferring sideband signals along a first number of sideband signal paths. A bump interface includes a second number of sideband bumps, each of the sideband bumps for coupling to a signal link. The second number of sideband bumps is less than the first number of sideband signal paths. A converter circuit is disposed between the UCIe interface circuit and the bump interface. The converter circuit includes a receiver circuit to receive first sideband data from the sideband sub-interface. The receiver circuit includes local clock circuitry, oversampling circuitry, and majority detection circuitry to receive oversampled data and to resolve states of sideband data bits based on a majority voting process.

Abstract: A computing system includes (1) a primary processor executing executable instructions and generating first instruction data associated with the executable instructions, (2) a secondary processor executing the executable instructions one or more clock cycles behind the primary processor and generating secondary instruction data associated with the executable instructions, (3) a first first-in first-out (FIFO) buffer for the primary processor, (4) a second FIFO buffer for the secondary processor, (5) circuitry storing at least some of the first instruction data in the first FIFO buffer and at least some of the second instruction data in the second FIFO buffer, (6) compare circuitry comparing a first portion of first instruction data and a second portion of second instruction data that are associated with a given clock cycle, and (7) control circuitry halting the primary and secondary processors responsive to a mismatch between the first portion and the second portion.

Abstract: Techniques for performing BF16 FMA in response to an instruction are described. In some examples, an instruction has fields for an opcode, an identification of location of a packed data source/destination operand (a first source), an identification of a location of a second packed data source operand, an identification of a location of a third packed data source operand, and an identification of location of a packed data source/destination operand, wherein the opcode is to indicate operand ordering and that execution circuitry is to, per data element position, perform a BF16 value fused multiply-accumulate operation using the first, second, and third source operands and store a result in a corresponding data element position of the source/destination operand.

Abstract: Processing circuitry to execute load operations, each associated with an identifier. Prediction circuitry to receive a given load value associated with a given identifier, and to make, in dependence on the given load value, a prediction indicating a predicted load value for a subsequent load operation to be executed by the processing circuitry and an ID-delta value indicating a difference between the given identifier and an identifier of the subsequent load operation. The predicted load value being predicted in dependence on at least one occurrence of each of the given load value and the predicted load value during execution of a previously-executed sequence of load operations. The prediction circuitry is configured to determine the ID-delta value in dependence on a difference between identifiers associated with the at least one occurrence of each of the given load value and the predicted load value in the previously-executed sequence of load operations.

Abstract: A method of scheduling tasks in a processor comprises receiving a plurality of tasks that are ready to be executed, i.e. all their dependencies have been met and all the resources required to execute the task are available, and adding the received tasks to a task queue (or “task pool”). The number of tasks that are executing is monitored and in response to determining that an additional task can be executed by the processor, a task is selected from the task pool based at least in part on a comparison of indications of resources used by tasks being executed and indications of resources used by individual tasks in the task pool and the selected task is then sent for execution.

Abstract: Disclosed are systems and methods related to providing for the optimized software implementations of artificial intelligence (“AI”) networks. The system receives operations (“ops”) consisting of a set of instructions to be performed within an AI network. The system then receives microkernels implementing one or more instructions to be performed within the AI network for a specific hardware component. Next, the system generates a kernel for each of the operations. Generating the kernel for each of the operations includes configuring input data to be received from the AI network; detecting a specific hardware component to be used; selecting one or more microkernels to be invoked by the kernel based on the detection of the specific hardware component; and configuring output data to be sent to the AI network as a result of the invocation of the microkernel(s).

Abstract: One example of an IP KVM device includes a USB port, a display port, a communication port, a network port, and a processor communicatively coupled to the USB port, display port, communication port, and network port. The USB port may be communicatively coupled to a host device to receive first USB signals from the host device. The display port may be communicatively coupled to the host device to receive first display signals from the host device. The communication port may be communicatively coupled to a secondary IP KVM device to receive second USB signals from the host device and second display signals from the host device. The network port may be communicatively coupled to a network. The processor is to aggregate the first and second USB signals and the first and second display signals and output the aggregated USB signals and display signals via the network port.

Abstract: Systems and methods related to direct swap caching with zero line optimizations are described. A method for managing a system having a near memory and a far memory comprises receiving a request from a requestor to read a block of data that is either stored in the near memory or the far memory. The method includes analyzing a metadata portion associated with the block of data, the metadata portion comprising: both (1) information concerning whether the near memory contains the block of data or whether the far memory contains the block of data and (2) information concerning whether a data portion associated with the block of data is all zeros. The method further includes instead of retrieving the data portion from the far memory, synthesizing the data portion corresponding to the block of data to generate a synthesized data portion and transmitting the synthesized data portion to the requestor.

Abstract: Disclosed is an operation method of a storage device which includes setting a first threshold value for a first host and a second threshold value for a second host under control of a hypervisor, sequentially fetching host commands from the first and second hosts, storing the fetched host commands in an internal command queue, stopping fetching a host command from the first host when the number of first host commands fetched from the first host from among the host commands stored in the internal command queue reaches the first threshold value, and stopping fetching a host command from the second host when the number of second host commands fetched from the second host from among the host commands stored in the internal command queue reaches the second threshold value.

Abstract: An integrated circuit includes a reconfigurable stream switch and an arithmetic circuit. The stream switch, in operation, streams data. The arithmetic circuit has a plurality of inputs coupled to the reconfigurable stream switch. In operation, the arithmetic circuit generates an output according to AX+BY+C, where A, B and C are vector or scalar constants, and X and Y are data streams streamed to the arithmetic circuit through the reconfigurable stream switch.