Patents Examined by Cheng-Yuan Tseng
  • Patent number: 10474218
    Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh, Hisham Abu-Salah
  • Patent number: 10476630
    Abstract: A data bus interface may include a history buffer and a serializer. The history buffer may store bits representing a history of data recently transmitted on the data bus. The serializer may be configured to modify an input bit sequence containing original bits by interspersing padding bits with the original bits to suppress noise at one or more target frequencies. The serializer may output the modified input bit sequence on the data bus. Each padding bit of the plurality of padding bits may be generated based on values of at least two bits stored in the history buffer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Michael John Cowell
  • Patent number: 10466921
    Abstract: Compressing data of a storage device includes selecting a portion of data for data compression that is predicted to be unlikely to be accessed, selecting a particular one of a plurality of data compression algorithms to apply to the portion according to a frequency value associated with each of the data compression algorithms, and adjusting the frequency value of the particular one of a plurality of data compression algorithms according to performance of the particular one of a plurality of data compression algorithms. The performance may vary according to a ratio of amount of compression achieved to processing cycles of a processor used to compress the portion of data. The processor may perform storage device functions that are separate from data compression. The portion of data may be selected from a plurality of logical devices used in connection with a single application that accesses the storage device.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: November 5, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Owen Martin, Jeremy O'Hare, Alesia Tringale, Ken Dorman
  • Patent number: 10467013
    Abstract: A method, system, and computer program product synchronize a group of workitems executing an instruction stream on a processor. The processor is yielded by a first workitem responsive to a synchronization instruction in the instruction stream. A first one of a plurality of program counters is updated to point to a next instruction following the synchronization instruction in the instruction stream to be executed by the first workitem. A second workitem is run on the processor after the yielding.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: November 5, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lee W. Howes, Benedict R. Gaster, Michael C. Houston
  • Patent number: 10459866
    Abstract: Systems, methods, and apparatuses relating to integrated control and data processing in a configurable spatial accelerator are described.
    Type: Grant
    Filed: June 30, 2018
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Kermin E. Fleming, Jr., Mitchell Diamond, Ping Zou, Benjamin Keen
  • Patent number: 10459637
    Abstract: A storage device stores data and is used by a plurality of information processors. The storage device receives prediction data which each of the plurality of information processors has predicted and transmitted, where the prediction data includes data regarding a data flow rate of each interface port with each of the plurality of information processors. The storage device calculates an access prediction value of each interface port based on the prediction data received from the plurality of information processors, and changes a setting of a process of each interface port based on the access prediction value.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: October 29, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Yuichi Koshiyama
  • Patent number: 10459862
    Abstract: A system includes a multi-conductor bus, a master device coupled to the multi-conductor bus, and at least one slave device coupled to the multi-conductor bus. The multi-conductor bus has a clock line and a data line. The master device is arranged to transmit an address configuration sequence, and the at least one slave device is arranged to configurably determine its own address based on at least one portion of the address configuration sequence. The at least one slave device has a physical address configuration input coupled to either a fixed voltage potential or a changing voltage potential. The at least one slave device is arranged with a first address during a pre-initialization state and arranged with a second address during a post-initialization state.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: October 29, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Eugenio Miluzzi, Marco Leo, Marco Castellano
  • Patent number: 10452398
    Abstract: Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Mikhail Plotnikov, Andrey Naraikin, Robert Valentine
  • Patent number: 10437747
    Abstract: System and method for improved transferring of data involving memory device systems. A memory appliance (MA) comprising a plurality of memory modules is configured to store data within the plurality of memory modules and further configured to receive data commands from first server and a second server coupled to the MA. The data commands may include direction memory access commands such that the MA can service the data commands while bypassing a host controller of the MA.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: October 8, 2019
    Assignee: Rambus Inc.
    Inventors: Vlad Fruchter, Keith Lowery, George Michael Uhler, Steven Woo, Chi-Ming (Philip) Yeung, Ronald Lee
  • Patent number: 10437758
    Abstract: A memory request management system may include a memory device and a memory controller. The memory controller may include a read queue, a write queue, an arbitration circuit, a read credit allocation circuit, and a write credit allocation circuit. The read queue and write queue may store corresponding requests from request streams. The arbitration circuit may send requests from the read queue and write queue to the memory device based on locations of addresses indicated by the requests. The read credit allocation circuit may send an indication of an available read credit to a request stream in response to a read request from the request stream being sent from the read queue to the memory device. The write credit allocation circuit may send an indication of an available write credit to a request stream in response to a write request from the request stream being stored at the write queue.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 8, 2019
    Assignee: Apple Inc.
    Inventors: Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Sukulpa Biswas
  • Patent number: 10417161
    Abstract: In a device comprising a serial bus and a plurality of devices, register/address mappings and/or unique group identifiers are used to convey additional information in messages/datagrams over the serial bus without explicitly sending such information in the message/datagram. Such register/address mappings may be done beforehand, and in conjunction with group-specific identifiers, may reduce transmission latency by keeping the size of the messages/datagrams small. Since all devices on the serial bus have prior knowledge of such register/address mappings and/or group-specific identifiers, recipient devices are able to infer information from the group-specific identifiers and/or register/address sent in each message/datagram that is not explicitly sent within such message/datagram.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 17, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Helena Deirdre O'Shea, Lalan Jee Mishra, Amit Gil, Gary Chang, Mohit Kishore Prasad, Richard Dominic Wietfeldt, Vinay Jain
  • Patent number: 10409754
    Abstract: An interconnected memory system, and a method of operation thereof, including: a first discrete unit having a first unit processor and first unit memory module; a high-speed interconnect connected directly to the first unit memory module; and a second discrete unit having a second unit processor and a second unit memory module, the second unit memory module connected to the first unit memory module through the high-speed interconnect for utilizing the first unit memory module and the second unit memory module with the first unit processor.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: September 10, 2019
    Assignee: SMART Modular Technologies, Inc.
    Inventor: Rajesh Ananthanarayanan
  • Patent number: 10409743
    Abstract: Various implementations of a multi-chip system operable according to a predefined transport protocol are disclosed. In one embodiment, a system comprises a first IC comprising a memory controller communicatively coupled with first physical ports. The system further comprises a second IC comprising second physical ports communicatively coupled with a first set of the first physical ports via first physical links, and one or more memory devices that are communicatively coupled with the second physical ports and accessible by the memory controller via the first physical links. The first IC further comprises an identification map table describing a first level of port aggregation to be applied across the first set. The second IC comprises a first distribution function configured to provide ordering to data communicated using the second physical ports. The first distribution function is based on the first level of port aggregation.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 10, 2019
    Assignee: XILINX, INC.
    Inventors: Millind Mittal, Jaideep Dastidar
  • Patent number: 10409760
    Abstract: An adaptive interface high availability storage device. In some embodiments, the adaptive interface high availability storage device includes: a rear storage interface connector; a rear multiplexer, connected to the rear storage interface connector; an adaptable circuit connected to the rear multiplexer; a front multiplexer, connected to the adaptable circuit; and a front storage interface connector, connected to the front multiplexer. The adaptive interface high availability storage device may be configured to operate in a single-port state or in a dual-port state. The adaptive interface high availability storage device may be configured: in the single-port state, to present a single-port host side storage interface according to a first storage protocol at the rear storage interface connector, and in the dual-port state, to present a dual-port host side storage interface according to the first storage protocol at the rear storage interface connector.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: September 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sompong Paul Olarig
  • Patent number: 10394725
    Abstract: A process may involve assembling a device at a device assembler. The process may include receiving a set of components, where each component of the set of components may be associated with a respective memory storing a set of characteristics of the component. The process may include assembling the set of components into the device at the device assembler. The process may also include accessing each respective memory of the components to read the sets of characteristics stored in the respective memories, and determining from the sets of characteristics of the components the characteristics of the device.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: August 27, 2019
    Assignee: Dell Products, LP
    Inventors: Minchuan Wang, Bhyrav M. Mutnury, Stuart Allen Berke
  • Patent number: 10372662
    Abstract: A universal serial bus (USB) communication system includes a USB host that divides one data stream into first through (n)th sub-data streams and transmits the first through (n)th sub-data streams via first through (n)th USB host channels, respectively, a USB device that receives the first through (n)th sub-data streams via first through (n)th USB device channels, respectively and restores the data stream by combining the first through (n)th sub-data streams, and first through (n)th cables that are connected to the first through (n)th USB host channels via first through (n)th USB host ports and connected to the first through (n)th USB device channels via first through (n)th USB device ports. Here, the first through (n)th cables connect the first through (n)th USB host channels to the first through (n)th USB device channels, respectively.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Cheon-Su Lee, Rohitaswa Bhattacharya
  • Patent number: 10366020
    Abstract: A data transfer control device includes an acquisition section, an analysis section, a band detection section, a mask output section and a selection section. The acquisition section acquires data from a plurality of processing sections for transmitting the data with a transmission path. The analysis section analyzes additional information of the data acquired by the acquisition section. The band detection section detects a transmission band of the transmission path based on the additional information. The mask output section outputs a request mask signal for suppressing the transmission of the data based on the transmission band detected by the band detection section and a target band preset on the transmission path. The selection section selects the data transmitted by the processing section based on the request mask signal output by the mask output section.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: July 30, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA TEC KABUSHIKI KAISHA
    Inventor: Tsutomu Ueta
  • Patent number: 10353844
    Abstract: A tunable bus-mediated coupling system is provided that includes a first input port coupled to a first end of a variable inductance coupling element through a first resonator and a second input port coupled to a second end of the variable inductance coupling element through a second resonator. The first input port is configured to be coupled to a first qubit, and the second output port is configured to be coupled to a second qubit. A controller is configured to control the inductance of the variable inductance coupling element between a low inductance state to provide strong coupling between the first qubit and the second qubit and a high inductance state to provide isolation between the first qubit and the second qubit.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: July 16, 2019
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Ofer Naaman, Zachary Kyle Keane, Micah John Atman Stoutimore, David George Ferguson
  • Patent number: 10353593
    Abstract: A method and apparatus for staged execution pipelining and allocating resource to staged execution pipelines are provided. One or more execution pipelines are established, where each of the one or more execution pipelines includes one or more execution stages. Data is provided to the one or more execution pipelines for processing and resources are allocated to the execution pipeline.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 16, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Nishanth Alapati, Pradeep Vincent, David Carl Salyers
  • Patent number: 10339071
    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes