Patents Examined by Cheri Harrington
  • Patent number: 10268257
    Abstract: A memory control device that is capable of making a nonvolatile memory of an information device exhibit the performance thereof certainly. A detection unit detects whether a data writable semiconductor memory is a nonvolatile memory or a volatile memory. A setting unit performs a setting to a volatile memory and performs a different setting to a nonvolatile memory that is detected with the detection unit.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: April 23, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yoshihisa Nomura
  • Patent number: 10175893
    Abstract: Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz, Patrick J. Meaney, Craig R. Walters
  • Patent number: 10162403
    Abstract: Systems and methods for reducing the amount of power consumed by an electronic or electrical device by using collected knowledge of the operation of the device to determine when to place the device in an ultra-low power consumption mode.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: December 25, 2018
    Assignee: Entropic Communications, LLC
    Inventors: Branislav Petrovic, Abul Shams Safdar, Sagar Jogadhenu
  • Patent number: 10146293
    Abstract: Systems, methods, and firmware for power control of data storage devices are provided herein. In one example, a data storage device is presented. The data storage device includes a storage control system to identify a power threshold for the data storage device. The data storage device determines power consumption characteristics for the data storage device and enters into a power controlled mode for the data storage device that adjusts at least a storage transaction queue depth in the data storage device to establish the power consumption characteristics as below the power threshold for the data storage device.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: December 4, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mohammed Ghiath Khatib, Damien Cyril Daniel Le Moal
  • Patent number: 10146284
    Abstract: Systems and methods for providing power to a home entertainment integrated circuit chip are disclosed. The home entertainment integrated circuit chip can operate in at least two power control modes: “power on” mode and “standby” mode. In power on mode, power is supplied to IC core module from a main power supply. The power supplied to the IC core module is isolated from power supplied to a standby island. Accordingly, during the second mode power is applied only to the standby power island through a regulator internal to the integrated circuit chip. The regulator is coupled to an external peripheral input/output (I/O) power supply that is independent of the main power supply.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: December 4, 2018
    Assignee: ENTROPIC COMMUNICATIONS, LLC
    Inventor: Branislav Petrovic
  • Patent number: 10088891
    Abstract: The present disclosure provides methods and systems for managing power in a processor having multiple cores. In one implementation, a microarchitecture of a core within a general-purpose processor may include configurable lanes (horizontal slices through the pipeline) which can be powered on and off independently from each other within the core. An online optimization algorithm may determine within a reasonably small fraction of a time slice a combination of lanes within different cores of the processor to be powered on that optimizes performance under a power constraint budget for the workload running on the general-purpose processor. The online optimization algorithm may use an objective function based on response surface models constructed to fit to a set of sampled data obtained by running the workload on the general-purpose processor with multiple cores, without running the full workload. In other implementations, the power supply to lanes can be gated.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: October 2, 2018
    Assignee: Cornell University
    Inventors: Paula Petrica, Adam M. Izraelevitz, David H. Albonesi, Christine A. Shoemaker
  • Patent number: 10007319
    Abstract: A power-saving method and circuit in a data processing device comprising a data buffer. Data transfer commands associated with a data source and a data destination are received at the data processing device. The data transfer commands are accumulated until an amount of data associated with the read commands is greater than a predefined threshold. When the amount of data is less than the predefined threshold and the data buffer is empty, the data buffer is signaled to enter or to maintain a power saving mode. When the amount of data is at least the predefined threshold, the data buffer is signaled to exit the power saving mode following a predetermined delay. Processing of the commands and data in respective pipelines is monitored to time exiting of the buffer from the power saving mode for arrival of the data. Power saving mode use and thus power saving are optimized.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: June 26, 2018
    Assignee: Microsemi Solutions (U.S.), Inc.
    Inventors: Amrendra Kumar, Janardan Prasad, David Joseph Clinton
  • Patent number: 9990212
    Abstract: Techniques described herein generally include methods for the testing and repair of a hardware accelerator image in a programmable logic circuit. In a processor chip that includes multiple programmable logic circuits, a hardware accelerator image programmed into a first programmable logic circuit is tested by programming a testing circuit with a duplicate hardware accelerator image and bringing the testing circuit to the same logic state as the first programmable logic circuit. Comparing outputs from the first programmable logic circuit and the testing circuit indicates the accuracy of the hardware accelerator image programmed into the first programmable logic circuit. The testing circuit may replace the first programmable logic circuit, or the testing circuit may be reprogrammed for testing other hardware accelerator images programmed into other programmable logic circuits of the processor chip.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: June 5, 2018
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Ezekiel Kruglick
  • Patent number: 9971393
    Abstract: The embodiments described herein relate to dynamically detecting a frequency change condition for microprocessor performance. An instruction is received, and a frequency change condition associated with the received instruction is dynamically detected. A frequency modulation is performed in response to the dynamic detection. The frequency modulation includes selecting a second frequency for optimal instruction processing different from a first frequency, the first frequency being a default operating frequency of the microprocessor. Execution of the instruction is completed at the second frequency. Accordingly, incoming execution instructions are logically analyzed, and the processor frequency is selectively modified based on associated instruction conditions.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bjorn P. Christensen, Victor Zyuban
  • Patent number: 9971389
    Abstract: An information handling system (IHS) performs current calibration of a multi-phase VR using leakage current as a reference current. The IHS includes a multi-phase voltage regulator (VR) module coupled to an output port of a power supply unit (PSU). The VR module includes: a multi-phase VR having an integrated power stage that provides pulse width modulation (PWM) functionality for controlling operating phases of VR current in the multi-phase VR; and a digital controller coupled to the multi-phase VR. The controller: enables a known, high accuracy operating phase as loading calibrator for offset training; records a leakage current value as a reference current; enables a first unknown, low accuracy operating phase; determines, for the unknown operating phase, an offset value that provides a specified target current accuracy; updates an offset register for the unknown operating phase with the corresponding offset value; and disables the unknown operating phase.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: May 15, 2018
    Assignee: Dell Products, L.P.
    Inventors: Feng-Yu Wu, Tsai-Fu Hung, Shin-Chen Wang, Shiguo Luo, Kejiu Zhang
  • Patent number: 9958921
    Abstract: A method includes controlling a power limit of a computing system based on a determined skin temperature of at least one location on an outer surface of a device housing the computing system. A processor includes a processing unit and a power management controller to control a power limit of the processing unit based on a determined skin temperature of at least one location on an outer surface of a device housing the processor.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: May 1, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ashish Jain, Benjamin David Bates, Ali Akbar Merrikh, Samuel David Naffziger, Steven Frederick Liepe, Madhu Saravana Sibi Govindan
  • Patent number: 9958928
    Abstract: A method of controlling an operating mode of at least one processing module. The method comprises receiving an indication of the execution of at least one background task by the at least one processing module, aggregating an execution duration for the at least one background task on the at least one processing module, and configuring a lower power mode for the at least one processing module when the at least one background task is allocated to the at least one processing module for execution thereon if the aggregated execution duration for the at least one background task exceeds a threshold duration within an evaluation period.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: May 1, 2018
    Assignee: NXP USA, Inc.
    Inventors: Mark Maiolani, Joseph Circello, Ray Marshall
  • Patent number: 9933838
    Abstract: Computations are performed on data objects via two or more data storage sections. The data storage sections facilitate persistently storing the data objects in parallel read/write operations. The data objects are used in computations within a storage compute device. At least one of the storage sections is deactivated during the computations to reduce power usage of the storage compute device.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: April 3, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: David Scott Ebsen, Ryan James Goss, Jeffrey L. Whaley, Dana Simonson
  • Patent number: 9928079
    Abstract: The use of a sleep, or halt, instruction enables a processor to halt execution when read from a non-volatile memory. The opcode for the sleep instruction is the same value as the constant bit value of an un-programmed, nonvolatile memory. When the opcode is read by the processor, execution is halted and the processor enters a wait or sleep mode. During the sleep mode, firmware is programmed into memory with another means such as an external host processor. When a valid trigger event occurs, for instance, external or internal interrupts or reset activation, the processor then exits the sleep mode and starts instruction etching at the PC_INIT address.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: March 27, 2018
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Philip Todd
  • Patent number: 9921637
    Abstract: Multi-port power prediction for power management of data storage devices is disclosed. For certain embodiments, a host interface within a port multiplier receives host messages from a host device for a plurality of data storage devices. The port multiplier then uses a plurality of ports to forward device messages to the data storage devices based upon the host messages. A power prediction controller determines target data storage devices for access commands within the host messages and generates power commands to adjust power modes for target data storage devices to place the target data storage devices in active power modes prior to access according to the access commands from the host device. Power up latency is thereby reduced or eliminated for the target data storage devices.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: March 20, 2018
    Assignee: NXP USA, Inc.
    Inventors: Dmitriy Shurin, Ron-Michael Bar, Eran Glickman
  • Patent number: 9910484
    Abstract: Embodiments including systems, methods, and apparatuses associated with increasing the power efficiency of one or more components of a computing system. Specifically, the system may include a processor chip which may include an on-die voltage regulator (VR) configured to supply a voltage to a component of the processor chip. The processor chip may be coupled with a dynamic random access memory (DRAM). The system may further include an external VR coupled with the DRAM. A BIOS may be configured to regulate the voltage output of one or both of the on-die VR and/or the external VR. Other embodiments may be described or claimed.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: March 6, 2018
    Assignee: Intel Corporation
    Inventors: Harry Muljono, Linda K. Sun
  • Patent number: 9910470
    Abstract: In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: March 6, 2018
    Assignee: Intel Corporation
    Inventors: Vivek Garg, Alexander Gendler, Arvind Raman, Ashish V. Choubal, Krishnakanth V. Sistla, Dean Mulla, Eric J. Dehaemer, Rahul Agrawal, Guy G. Sotomayor
  • Patent number: 9898064
    Abstract: An information processing apparatus including a volatile storage unit, and is operated in any of a plurality of modes including a first power mode and a second power mode, power being supplied to the storage unit in the first power mode and the second power mode, power consumption in the first power mode being higher than power consumption in the second power mode.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: February 20, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Keigo Goda
  • Patent number: 9846560
    Abstract: An information processing apparatus capable of changing a state of power supply to respective parts of the apparatus with less user operation. When a sleep recovery button is depressed in a power saving mode, a button depression time is measured, and whether a length of the measure depression time exceeds a threshold value is determined. If the depression time exceeds the threshold value, a normal power mode is selected as power mode after transition. If the depression time does not exceed the threshold value, another power saving mode is selected as power mode after transition. According to the selected power mode, a state of power supply to respective parts of the apparatus is changed.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: December 19, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Kazuhiro Koga
  • Patent number: 9778728
    Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: October 3, 2017
    Assignee: Apple Inc.
    Inventors: Anand Dalal, Joshua P. de Cesare