Abstract: Disclosed are various embodiments providing processing circuitry that generates an output for each clock cycle of a clock signal using a logic block, the logic block being powered by a supply voltage. The processing circuitry detects whether the output has stabilized at a point in time before the end of a clock cycle of the clock signal, the point in time being based at least upon a delay line. In response to detecting whether the output has stabilized at a point in time, the processing circuitry dynamically adjusts at least one of the supply voltage or the frequency of the clock signal.

Abstract: Associating processor and processor core energy consumption with a task such as a virtual machine is disclosed. Various events cause a trace record to be written to a trace buffer for a processor. An identifier associated with a task using a processor core of the processor is read. In addition, one or more values associated with an energy consumption of the processor core are read. In response to the event, the one or more values associated with the energy consumption of the processor core and the identifier are written to the trace buffer memory.

Abstract: A detecting system includes a sense terminal and detecting circuitry coupled to the sense terminal. The sense terminal receives an indicative signal indicative of a supply current of a power source. The detecting circuitry calculates variation in the supply current based on the indicative signal, estimates power consumption of an application program residing on a computer-readable medium according to the variation, and detects whether an abnormal condition occurs by comparing the estimated power consumption with a reference.

Abstract: A method and circuit arrangement utilize a general purpose processing unit having a low power DSP mode for reconfiguring the general purpose processing unit to efficiently execute DSP workloads with reduced power consumption. When in a DSP mode, one or more of a data cache, an execution unit, and simultaneous multithreading may be disabled to reduce power consumption and improve performance for DSP workloads. Furthermore, partitioning of a register file to support multithreading, and register renaming functionality, may be disabled to provide an expanded set of registers for use with DSP workloads. As a result, a general purpose processing unit may be provided with enhanced performance for DSP workloads with reduced power consumption, while also not sacrificing performance for other non-DSP/general purpose workloads.

Abstract: A system with scalable data collection for system management comprises a plurality of local data collectors and a system collector. Each of the local data collectors is coupled with a corresponding subsystem of the system. Each of the local data collectors is configured to periodically collect power management related data from the corresponding subsystem, and to format the collected power management related data for conveyance along any one of a plurality of channels between the local data collector and the system collector. The system collector is coupled with the plurality of local data collectors via the plurality of channels. The system collector selects from the channels between the system collector and each of the local data collectors based, at least in part, on channel states, and retrieves the power management related data collected by each of the local data collectors along a selected channel for the local data collector.

Abstract: A method, an apparatus, and a computer program product for allocating a total power budget among a plurality of components of a user device are provided. The apparatus prioritizes the plurality of components based on a user experience model (performance/power model) for each of the plurality of components. The user experience model (performance/power model) of a component includes a measure of component attribute as a function of component power consumption. The apparatus allocates portions of the total power budget among the user-device components based on priority established by the user experience model. The apparatus may further prioritize the components based on weights assigned to the components.

Abstract: A computer and a waking method thereof are provided. The computer includes a switch circuit, a chipset, a peripheral component interconnect express (PCIE) device, and an embedded controller. The chipset includes a first wake-up pin and a power button pin, wherein the first wake-up pin is coupled to a terminal of the switch circuit. The PCIE device includes a second wake-up pin, and the embedded controller includes a general purpose input pin and a general purpose output pin. The general purpose input pin and the second wake-up pin are coupled to another terminal of the switch circuit. The general purpose output pin is coupled to the power button pin.

Abstract: A time measurement device includes a first measurement unit configured to measure a clock number of a first reference clock signal within a specific cycle of a second reference clock signal; a calculation unit configured to calculate a physical amount indicating a variance amount of the clock number relative to a reference clock number; a compensation unit configured to compensate an expected measurement value indicating the clock number of the first reference clock signal corresponding to a time as a measurement target according to the physical amount calculated with the calculation unit; and an output unit configured to output time information indicating that the clock number of the first reference clock signal reaches the expected measurement value when the clock number of the first reference clock signal measured with the first measurement unit reaches the expected measurement value compensated with the compensation unit.

Abstract: An electronic device includes a current detection module, two path switches, a processing unit, and two control circuits. Two terminals of the current detection module are connected to an external power port and a battery. The two path switches are connected to the two terminals. A first control circuit is connected to the processing unit and to one path switch. A second control circuit is connected to the processing unit and to another path switch. When the electronic device is powered on, whether using power from the battery or from the external power port, the device can analyze the power consumed by the functioning parts of the device, including (when power is taken from the external power port) the amount of current taken in charging the battery.