Patents Examined by Christian D. Wilson
  • Patent number: 7138724
    Abstract: A solder mask includes an opening through which intermediate conductive elements may be positioned to connect bond pads of a semiconductor die exposed through an aligned opening in a carrier substrate to which the solder mask is secured with corresponding contact areas of the carrier substrate. An assembly is formed by forming the solder mask on or securing the solder mask to the carrier substrate. The semiconductor die is attached to the carrier substrate such that bond pads of the semiconductor die are exposed through the aligned openings in the carrier substrate and solder mask. Intermediate conductive elements are used to electrically connect the bond pads to corresponding contact areas on the carrier substrate. An encapsulant material is introduced into an area defined by the solder mask and carrier substrate openings such that the intermediate conductive elements and semiconductor die surface within the aligned openings are encapsulated.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: November 21, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Ford B. Grigg, William J. Reeder
  • Patent number: 7125748
    Abstract: A solder mask includes an opening through which intermediate conductive elements may be positioned to connect bond pads of a semiconductor die exposed through an aligned opening in a carrier substrate to which the solder mask is secured with corresponding contact areas of the carrier substrate. An assembly is formed by forming the solder mask on or securing the solder mask to the carrier substrate. The semiconductor die is attached to the carrier substrate such that bond pads of the semiconductor die are exposed through the aligned openings in the carrier substrate and solder mask. Intermediate conductive elements are used to electrically connect the bond pads to corresponding contact areas on the carrier substrate. An encapsulant material is introduced into an area defined by the solder mask and carrier substrate openings such that the intermediate conductive elements and semiconductor die surface within the aligned openings are encapsulated.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: October 24, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Ford B. Grigg, William J. Reeder
  • Patent number: 7105434
    Abstract: One embodiment of the present invention is a method for making metallic interconnects, which method is utilized at a stage of processing a substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the field and the at least one opening being ready for depositing one or more seed layers, which method includes steps of: (a) depositing by an ALD technique at least an initial portion of a substantially conformal seed layer on the field and inside surfaces of the at least one opening, wherein said at least one opening has a width of less than about 0.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: September 12, 2006
    Inventor: Uri Cohen
  • Patent number: 7094643
    Abstract: A method of forming a gate of a flash memory cell, by which a coupling effect between floating and control gates can be enhanced by forming a polysilicon spacer in forming the floating gate to increase a surface area of the floating gate. The gate is formed by forming a nitride layer pattern on a substrate to define a prescribed space, forming a polysilicon spacer at a sidewall of the nitride layer pattern within the defined space on the first polysilicon, and removing the nitride layer pattern.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: August 22, 2006
    Assignee: DongbuAnam Semiconductor Inc.
    Inventor: Chul Jin Yoon
  • Patent number: 7084505
    Abstract: A porous film-forming composition comprising (A) a curable silicone resin having a Mn of at least 100, (B) a micelle-forming surfactant, and (C) a compound which generates an acid upon pyrolysis remains stable during storage. The composition is coated and heat treated to form a porous film which has flatness, uniformity, a low dielectric constant and a high mechanical strength so that it is best suited as an interlayer dielectric film in the fabrication of semiconductor devices.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: August 1, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshitaka Hamada, Fujio Yagihashi, Hideo Nakagawa, Masaru Sasago
  • Patent number: 7081643
    Abstract: A gain-clamped semiconductor optical amplifier having a horizontal lasing structure in which an oscillation direction of a laser is different from an amplification direction of a signal, and a method for manufacturing the gain-clamped semiconductor optical amplifier. The gain-clamped semiconductor optical amplifier includes a gain layer for amplifying an optical signal. A Bragg lattice layer is formed on both sides of the gain layer along a longitudinal direction of the gain layer for enabling light having a corresponding wavelength to resonate in a direction vertical to the longitudinal direction of the gain layer. A passive light waveguide restrains light resonating between lattices of the Bragg lattice layer. An electrode supplies current to the gain layer, and a current-blocking layer prevents current from flowing to an area other than the gain layer.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: July 25, 2006
    Assignee: Samsumg Electronics Co., Ltd.
    Inventors: Jeong-Seok Lee, Jung-Koo Kang, Seong-Taek Hwang
  • Patent number: 7078735
    Abstract: A light-emitting device, having high light extraction efficiency, capable of obtaining diffused light is obtained. This light-emitting device comprises a light-emitting diode, a portion, formed on a plane substantially parallel to a light-emitting surface of the light-emitting diode, having a dielectric constant periodically modulated with respect to the in-plane direction of the plane substantially parallel to the light-emitting surface and a member provided on the side of the light-emitting surface of the light-emitting diode for diffusing light emitted from the light-emitting diode.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: July 18, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masayuki Shono, Masayuki Hata
  • Patent number: 7078297
    Abstract: A memory cell includes devices having associated isolation recesses of differing magnitudes. The effective channel width of a corresponding transistor is substantially equal to a channel top surface width plus twice a sidewall width formed by the isolation recesses. In an SRAM cell, a latch transistor has a larger effective channel width than an associated pass transistor by forming larger recesses, and therefore larger sidewalls in isolation layers surrounding the latch transistor and limiting such recesses for pass transistors. During manufacture of the memory cell, a mask is used to mask an area of the pass transistor while exposing an area of the latch transistor. Accordingly, recesses in an isolation layer around the latch transistor are formed without affecting a corresponding area around the pass transistor.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: July 18, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: James D. Burnett, Suresh Venkatesan
  • Patent number: 7067360
    Abstract: A method of fabricating a fin field effect transistor is disclosed. An example method forms a thermal oxide layer as a hard mask for etching a silicon fin on an SOI substrate, transcribes a fin pattern, forms a fin FET body by etching using the fin pattern as an etch mask, and restores a sidewall damaged by the etching remove a sacrificial silicon oxide layer. The example method also deposits a high-K dielectric as a gate dielectric, deposits a metal layer, planarizes the metal layer to a height of a hard oxide, forms a nitride layer on the planarized metal layer, and patterns the nitride layer using a hard mask for forming a pattern to form a nitride layer pattern. Additionally, the example method forms a metal gate using the nitride layer pattern, removes a remaining hard oxide mask, and grows a sidewall oxide layer on the metal gate.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: June 27, 2006
    Assignee: DongbuAnam Semiconductor Inc.
    Inventor: Byeong Ryeol Lee
  • Patent number: 7064394
    Abstract: A memory cell and a selection transistor for selecting the memory cell are provided. The memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in the substrate, first and second control gates formed on the opposite sides of the floating gate to drive the floating gate, and an inter-gate insulation film formed between the first and second control gates and the floating gate. The selection transistor includes a selection gate•wiring including a first portion constituted of the same conductive layer as the first conductive layer, and a second portion constituted of the same conductive layer as the second conductive layer, and a second diffusion layer formed in the substrate, facing the second portion of the selection gate•wiring.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: June 20, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kikuko Sugimae, Hiroyuki Kutsukake
  • Patent number: 7056789
    Abstract: The present invention relates to a semiconductor substrate production method, field effect transistor production method, semiconductor substrate and field effect transistor which, together with having low penetrating dislocation density and low surface roughness, prevent worsening of surface and interface roughness during heat treatment of a device production process and so forth. A production method of a semiconductor substrate W, in which SiGe layers 2 and 3 are formed on an Si substrate 1, is comprised of a heat treatment step in which heat treatment is performed either during or after the formation of the SiGe layers by epitaxial growth, at a temperature that exceeds the temperature of the epitaxial growth, and a polishing step in which irregularities in the surface formed during the heat treatment are removed by polishing following formation of the SiGe layers.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: June 6, 2006
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Ichiro Shiono, Kazuki Mizushima, Kenji Yamaguchi
  • Patent number: 7052980
    Abstract: A method for manufacturing a transistor, includes the steps of preparing a substrate, preparing a liquid material containing a silane compound, the silane compound forming a high order silane when photopolymerized, coating the liquid material on the substrate so as to form a coating film, exposing the coating film to an atmosphere comprising at least one of oxygen and ozone so as to oxidize a surface of the coating film, and performing at least one of thermal processing and photoirradiation processing on the coating film in an inert atmosphere so as to transform the coating film into a silicon layer and a silicon oxide layer disposed on the silicon layer.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: May 30, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Takashi Aoki
  • Patent number: 7052978
    Abstract: Arrangements incorporating laser-induced cleaving.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: May 30, 2006
    Assignee: Intel Corporation
    Inventors: Mohamad A. Shaheen, Mark Y. Liu, Mitchell C. Taylor
  • Patent number: 7045858
    Abstract: There is provided a semiconductor device comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, the second conductivity type being different from the first conductivity type, a third semiconductor layer of the first conductivity type selectively formed on the second semiconductor layer, a trench formed through the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer, a gate dielectric film formed along side and bottom surfaces of the trench, and a gate electrode formed to be in contact with the gate dielectric film at the side surfaces of the trench, surfaces of the gate electrode that are opposite to the surfaces contacting the gate dielectric film, and the gate dielectric film at a bottom of the trench forming a hollow portion extending from the bottom to an opening side of the trench.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: May 16, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noboru Matsuda, Shoji Takayama, Yasuo Ebuchi
  • Patent number: 7045396
    Abstract: Leadframe-type semiconductor packages that allow the semiconductor packages to be stacked on top of each other. One aspect of the semiconductor package includes a leadframe, a plurality of electrical connectors, a semiconductor chip, and a sealing material for encapsulating the above components. The leadframe has a plurality of leads, with each one of the plurality of leads running from the top of the semiconductor package to the bottom of the semiconductor package. Each one of the plurality of leads has a top portion protruding from the top surface of the semiconductor package and a bottom portion protruding from the top surface of the semiconductor package and a bottom portion protruding from the bottom surface of the semiconductor package. The leads allow for electrical connection of a second semiconductor package placed on top of the first semiconductor package. Further, the protruding parts of the leads form a space between the stacked semiconductor packages for improved heat dissipation.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: May 16, 2006
    Assignee: Amkor Technology, Inc.
    Inventors: Sean Timothy Crowley, Angel Orabuena Alvarez, Jun Young Yang
  • Patent number: 7045431
    Abstract: Methods are disclosed that fabricating semiconductor devices with high-k dielectric layers. The invention removes portions of deposited high-k dielectric layers not below gates and covers exposed portions (e.g., sidewalls) of high-k dielectric layers during fabrication with an encapsulation layer, which mitigates defects in the high-k dielectric layers and contamination of process tools. The encapsulation layer can also be employed as an etch stop layer and, at least partially, in comprising sidewall spacers. As a result, a semiconductor device can be fabricated with a substantially uniform equivalent oxide thickness.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: May 16, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Antonio L. P. Rotondaro, Douglas E. Mercer, Luigi Colombo, Mark Robert Visokay, Haowen Bu, Malcolm John Bevan
  • Patent number: 7045870
    Abstract: It is an object of the invention to provide an improved solid image-pickup device which is compact in size and low in production cost. The solid image-pickup device is so formed that its semiconductor substrate has on its surface an image-pickup area having a plurality of light sensors arranged thereon. A transparent plate having the same shape and the same size as those of the semiconductor substrate when viewed as a plan view is bonded to the surface of the semiconductor substrate. A plurality of bonding pads are formed on the surface of the semiconductor substrate and arranged around the image-pickup area. Further, a plurality of through holes are formed through the semiconductor substrate, extending from the lower surfaces of the bonding pads to the back surface of the semiconductor substrate. An insulating film is tightly attached to the inner surface of each of the through holes, while another insulating film is tightly attached to the back surface of the semiconductor substrate.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: May 16, 2006
    Assignee: Sony Corporation
    Inventor: Yukinobu Wataya
  • Patent number: 7041585
    Abstract: A process for producing an electronic component includes covering a substrate with a portion defining, with the substrate, a volume at least partly filled with a temporary material. The temporary material is then removed via chimney for access to said volume. A deposition of a fill material is then made in said volume, the fill material being obtained from precursors supplied via the chimney. The process is particularly suitable for producing a gate of an MOS-type transistor. In this case, the fill material is conducting or semiconducting, and an electrically insulating coating material may also be deposited in said volume before the (semi) conducting fill material. The process also includes defining a trench in a substrate filled with a temporary material. The filled trench is then covered with a circuit portion. The temporary material is then removed via a chimney for access to the trench. A deposition of low dielectric fill material is then made in the trench.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: May 9, 2006
    Assignee: STMicroelectronics S.A.
    Inventors: Jessy Bustos, Philippe Coronel, Christophe Regnier, François Wacquant, Brice Tavel, Thomas Skotnicki
  • Patent number: 7037731
    Abstract: A method of manufacturing a ferroelectric capacitor. In this method, a lower electrode is formed on a base at first. A ferroelectric film which includes a PZTN complex oxide including lead, zirconium, titanium, and niobium on the lower electrode is formed, and then an upper electrode is formed on the ferroelectric film. A protective film is then formed to cover the lower electrode, the ferroelectric film, and the upper electrode, and heat treatment for crystallizing the PZTN complex oxide is performed at least after forming the protective film.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: May 2, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Takeshi Kijima, Koji Ohashi, Eiji Natori
  • Patent number: 7037760
    Abstract: A method of fabricating a semiconductor integrated circuit device uses a mold which is provided with a plurality of air vents and movable pins which are formed such that the movable pins include grooves in the distal ends thereof which project into the air vents. By clamping the mold in a state such that the distal ends of the movable pins are pushed against a multi-cavity board at the time of clamping the mold, resin can be filled while leaking air inside the cavity through the grooves formed in the distal ends of the movable pins by setting the depths of the respective air vents to a fixed value irrespective of the irregularities in thickness of the multi-cavity boards. Accordingly, it is possible to prevent insufficient filling of resin in the cavity, the leaking of resin or defective welding, whereby the yield rate of products can be enhanced.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: May 2, 2006
    Assignees: Renesas Technology Corp., Renesas Eastern Japan Semiconductor, INC
    Inventors: Bunshi Kuratomi, Fukumi Shimizu