Abstract: Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.

Abstract: A memory device includes a DRAM memory cell array, which is implemented as a 6 F×F array, and peripheral circuitry. The word lines of the memory cell array are implemented as buried word lines, and, in addition, the bit lines including the bit line contacts are made of a bit line layer stack. The peripheral circuitry includes a peripheral transistor including first and second source/drain regions, a channel connecting the first and the second source/drain regions as well as a peripheral gate electrode for controlling an electrical current of the channel. The peripheral gate electrode is made of a peripheral gate stack including a layer stack which is identical with the bit line stack.

Abstract: Provided is an electroluminescent display device having a negligibly small voltage drop of a cathode, no external light reflection, and high contrast and luminance. The electroluminescent display device includes a rear substrate, a first electrode layer formed above the rear substrate, a second electrode layer formed above the first electrode layer, the second electrode layer facing the first electrode layer, a light-emitting layer interposed between the first electrode layer and the second electrode layer, the light-emitting layer having at least an emission layer, a front substrate facing the rear substrate and contacting an upper surface of the second electrode layer, and a functional thin film formed between the second electrode layer and the front substrate, the functional thin film having a conductive material at least in a portion thereof contacting the second electrode layer.

Abstract: The present invention relates to a non-volatile memory comprising: a first electrode (11); a second electrode (12); and a phase-change recording medium (14) sandwiched between the first electrode (11) and the second electrode (12), in which resistance value is varied by applying an electrical pulse across the first electrode (11) and the second electrode (12), at least one of the first electrode (11) and the second electrode (12) contains as a main ingredient at least one member selected from the group consisting of ruthenium, rhodium and osmium, and the phase-change recording medium (14) is formed of a phase-change material that contains chalcogen(s). This non-volatile memory exhibits improved durability and reliability by preventing deterioration of property (i.e., mutual impurity diffusion between the electrode and the phase-change recording medium) caused by application of current.

Abstract: A semiconductor device is improved in reliability by suppressing the electric-field concentration at a top edge of a trench or the leak current at a bottom edge thereof. A first thermal oxide film is formed by carrying out low-temperature wet oxidation at a silicon substrate heating temperature of approximately 950° C., extending from over a bottom surface of the trench formed in a main surface of a silicon substrate to an intermediate point on a sidewall of the trench. Thereafter, a second thermal oxide film is formed by carrying out high-temperature dry oxidation at a silicon substrate heating temperature of approximately 1100° C., extending from the intermediate point to over the main surface of the silicon substrate outside the trench.

Abstract: An underlayer film-forming material for copper, a method for forming the underlayer, an underlayer film for copper, and a semiconductor device including a substrate, the underlayer and copper wiring film, which prevents copper diffusion as well as provides superior adhesion to a copper wiring film, even if the film is thinner than conventional barrier metals. The underlayer film-forming material for copper is formed from a compound represented by a (R1R2)P—(R)n—Si(X1X2X3), wherein at least one of X1, X2, and X3 represents a hydrolysable group; each of R1 and R2 represents an alkyl group; R represents a divalent linear organic group which is selected from an alkylene group, an aromatic ring, and an alkylene group including an aromatic ring; and n is an integer from 1 to 6.

Abstract: A substrate undergoes a semiconductor fabrication process at different temperatures in a reactor without changing the temperature of the reactor. The substrate is held suspended by flowing gas between two heated surfaces of the reactor. Moving the two heated surfaces in close proximity with the substrate for a particular time duration heats the substrate to a desired temperature. The desired temperature is then maintained by distancing the heated surfaces from the substrate and holding the heated surface at the increased distance to minimize further substrate heating.

Abstract: The present invention enables to avoid a reduction in coupling ratio in a nonvolatile semiconductor memory device. The reduction is coupling ratio is caused due to difficulties in batch forming of a control gate material, an interpoly dielectric film material, and a floating gate material, the difficulties accompanying a reduction in word line width. Further, the invention enables to avoid damage caused in the batch forming on a gate oxide film. Before forming floating gates of memory cells of a nonvolatile memory, a space enclosed by insulating layers is formed for each of the floating gates of the memory cells, so that the floating gate is buried in the space. This structure is realized by processing the floating gates in a self alignment manner after depositing the floating gate material.

Abstract: The invention includes a memory device having a capacitor in combination with a transistor. The memory device can be within a TFT construction. The capacitor is configured to provide both area and perimeter components of capacitance for capacitive enhancement. The capacitor includes a reference plate which splits into at least two prongs. Each of the prongs is surrounded by a lateral periphery. A dielectric material extends around the lateral peripheries of the prongs, and a storage node surrounds an entirety of the lateral peripheries of the prongs. The storage node is separated from the reference plate by at least the dielectric material. Also, the invention includes electronic systems comprising novel capacitor constructions.

Abstract: A memory cell and a selection transistor for selecting the memory cell are provided. The memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in the substrate, first and second control gates formed on the opposite sides of the floating gate to drive the floating gate, and an inter-gate insulation film formed between the first and second control gates and the floating gate. The selection transistor includes a selection gate•wiring including a first portion constituted of the same conductive layer as the first conductive layer, and a second portion constituted of the same conductive layer as the second conductive layer, and a second diffusion layer formed in the substrate, facing the second portion of the selection gate•wiring.

Abstract: In a method of forming an electrically conductive lamination pattern, an insulating film is formed on a surface of a chromium-containing bottom layer, before an aluminum-containing top layer is formed over the insulating film, so that the insulating film separates the aluminum-containing top layer from the chromium-containing bottom layer. A first selective wet etching process is carried out for selectively etching the aluminum-containing top layer with a first etchant. A second selective wet etching process is carried out for selectively etching the chromium-containing bottom layer with a second etchant in the presence the insulating film which suppresses a hetero-metal-contact-potential-difference between the chromium-containing bottom layer and the aluminum-containing top layer during the second selective wet etching process.

Abstract: A ROM embedded DRAM provides ROM cells that can be programmed to a single state. The ROM cells include capacitors having a storage node. The storage node is processed to have a substantially high substrate leakage. The ROM cells, therefore, are hard programmed to a logic zero state. Bias techniques can be used to read un-programmed ROM cells accurately. As described, sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitry is coupled to bit lines to favor the un-programmed state. A differential pre-charge operation can also be used in another embodiment.

Abstract: The present invention relates to a method for fabricating a TFT using dual or multiple gates, and provides a TFT having superior characteristics and uniformity by providing a method for fabricating a TFT using dual or multiple gates comprising the steps of calculating probability including Nmax the maximum number of crystal grain boundaries in active channel regions according to the length of the active channels, and adjusting gap between the active channels capable of synchronizing the number of the crystal grain boundaries in each active channel regions of the TFT using the dual or multiple gates in case that Gs size of crystal grains of polycrystalline silicon forming a TFT substrate, ? angle in which “primary” crystal grain boundaries are inclined to a direction perpendicular to an active channel direction of the gates, width of the active channels and length of the active channels are determined.

Abstract: An embodiment of the present invention is a technique to distribute clock. At least a metal layer is formed to have a standing-wave structure to distribute a clock signal to receiver end points from a clock source such that the receiver end points are substantially electrically equivalent with respect to the clock source. The metal layer is embedded in dielectric layers made of thick film using a wafer-level thick film (WLTF) process.

Abstract: A metal-poly integrated capacitor structure that may be used in a charge pump circuit of a non-volatile memory. In one embodiment, the capacitor comprises a poly silicon layer, a first metal layer and a second metal layer. The first metal layer is positioned between the poly silicon layer and the second metal layer. The first metal layer has a first terminal and a second terminal. The first terminal is electrically isolated from the second terminal.

Abstract: Methods for fabricating semiconductor devices are disclosed. An illustrated method includes: etching a semiconductor substrate to form a trench, forming an ONO film on the semiconductor substrate, removing the ONO film from the upper surface of the semiconductor substrate while leaving the ONO film on an inside wall surface of the trench, forming a gate oxide film on the semiconductor substrate adjacent the ONO film, depositing polysilicon on the semiconductor substrate, and selectively removing the polysilicon to form SONOS gate electrodes on the gate oxide film and the trench, respectively. Because opposite sides of the polysilicon gate electrode are covered with an ONO layer, the size of the nitride film may be substantially maximized.

Abstract: The memory cell matrix encompasses (a) a plurality device isolation films running along column direction, (b) first conductive layers arranged along row and column-directions, adjacent groups of the first conductive layers are isolated from each other by the device isolation film disposed between the adjacent groups, (c) lower inter-electrode dielectrics arranged respectively on crests of the corresponding first conductive layers, (d) an upper inter-electrode dielectric arranged on the lower inter-electrode dielectric made of insulating material different from the lower inter-electrode dielectrics, and (e) second conductive layers running along the row-direction, arranged on the upper inter-electrode dielectric.

Abstract: A fabrication method of a semiconductor device which has on the same semiconductor layer a transistor with a different high voltage gate as well as a high voltage drain and an MNOS memory transistor.

Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.

Abstract: A ROM embedded DRAM provides ROM cells that can be programmed to a single state. The ROM cells include capacitors having a storage node. The storage node is processed to have a substantially high substrate leakage. The ROM cells, therefore, are hard programmed to a logic zero state. Bias techniques can be used to read un-programmed ROM cells accurately. As described, sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitry is coupled to bit lines to favor the un-programmed state. A differential pre-charge operation can also be used in another embodiment.