Abstract: A semiconductor device at least has a memory cell array. The memory cell array has active regions extending linearly in parallel with one another at predetermined intervals and each containing alternating source and drain regions, gate electrodes orthogonally crossing the active regions between the source and drain regions and each having a floating gate and a control gate laid one upon another, first conductors extending linearly in parallel with the gate electrodes and connected to corresponding ones of the source regions through source contacts, and second conductors connected to corresponding ones of the drain regions through drain contacts.

Abstract: A method of making byte erasable devices having elements made with nanotubes. Under one aspect of the invention, a device is made having nanotube memory elements. A structure is provided having a plurality of transistors, each with a drain and a source with a defined channel region therebetween, each transistor further including a gate over said channel. For a predefined set of transistors, a corresponding trench is formed between gates of adjacent transistors. For each trench, a defined pattern of nanotube fabric is provided over at least a horizontal portion of the structure and extending into the trench. An electrode is provided in each trench. Each defined pattern of nanotube fabric is suspended so that at least a portion is vertically suspended in spaced relation to the vertical walls of the trench and positioned so that the vertically suspended defined pattern of nanotube fabric is electromechanically deflectable into electrical communication with one of the drain and source of a transistor.

Abstract: A method for forming a trench having rounded corners in a semiconductor device comprises providing a substrate; forming a first pad oxide layer, a first silicon nitride layer, and a first oxide layer on the substrate sequentially; removing portions of the first oxide layer, the first silicon nitride layer, the first pad oxide layer, and the substrate to form at least one trench; and removing portions of the first oxide layer, the first silicon nitride layer, and the first pad oxide layer in the trench above an upper corner of the substrate in the trench. The substrate includes a lower corner at a bottom of the trench.

Abstract: There is provided an amplifying solid-state image pickup device capable of improving S/N and maintaining a charge-voltage conversion efficiency high. In the amplifying solid-state image pickup device, signal charges of a plurality of photodiodes 1 are added up on an input side of a switched capacitor amplification part 20 via the transfer transistors 2.

Abstract: A silicon oxide gap-filling process is described, wherein a CVD process having an etching effect is performed to fill up a trench with silicon oxide. The reaction gases used in the CVD process include deposition gases and He/H2 mixed gas as a sputtering-etching gas, wherein the percentage of the He/H2 mixed gas in the total reaction gases is raised with the increase of the aspect ratio of the trench.

Abstract: A low resistance copper damascene interconnect structure is formed by providing a thin dielectric film such as SiC or SiOC formed on the sidewalls of the via and trench structures to function as a copper diffusion barrier layer. The dielectric copper diffusion barrier formed on the bottom of the trench structure is removed by anisotropic etching to expose patterned metal areas. The residual dielectric thus forms a dielectric diffusion barrier film on the sidewalls of the structure, and coupled with the metal diffusion barrier subsequently formed in the trench, creates a copper diffusion barrier to protect the bulk dielectric from copper leakage.

Abstract: The invention provides a damascene gate process. A semiconductor substrate having a pad layer and an etch stop layer formed thereon is provided, and an insulating layer is formed to cover the etch stop layer, followed by forming an opening by partially removing the insulating layer, the etch stop layer, and the pad layer. A protective spacer is formed on the sidewall of the opening, wherein the top of the protective spacer is lower than the insulating layer. A gate conducting layer is then formed in the opening. The protective spacer and the insulating layer are removed to expose a portion of the semiconductor substrate and the etch stop layer. Implantation is then performed to form lightly doped drains. A gate spacer is then formed to cover the gate conducting layer. The etch stop layer and the pad layer are removed, and implantation is then performed to a form source/drain.

Abstract: A solder mask includes an opening through which intermediate conductive elements may be positioned between bond pads of a semiconductor die exposed through an aligned opening in a carrier substrate to which the solder mask is secured and corresponding contact areas of the carrier substrate. An assembly is formed by forming the solder mask on or securing the solder mask to the carrier substrate. The semiconductor die is then attached to the carrier substrate such that bond pads of the semiconductor die are exposed through the aligned openings in the carrier substrate and solder mask. Intermediate conductive elements are then used to electrically connect the bond pads to corresponding contact areas on the carrier substrate. An encapsulant material is introduced into an area defined by the solder mask and carrier substrate openings such that the intermediate conductive elements and semiconductor die surface within the aligned openings are encapsulated.

Abstract: A method is provided for fabricating a MOSFET device. The method begins by forming a semiconductor device having a substrate on which a gate conductor having sidewalls separates a source region and a drain region. An oxide layer is formed over the gate sidewalls and a portion of the substrate. Ions of a first conductivity are implanted into the source and the drain regions to define source and drain extensions that respectively extend in part under the gate conductor. A nitride layer is formed over the oxide layer that extends over the portion of the substrate. An angled ion implant is performed during which the gate conductor shields a portion of the nitride layer over at least a portion of the drain region from damage by the angled ion implant. The angled ion implant selectively damages portions of the nitride layer in which ions are implanted to form damaged portions of the nitride layer.

Abstract: An ultra-high density data storage device using phase-change diode memory cells, and having a plurality of emitters for directing beams of directed energy, a layer for forming multiple data storage cells and a layered diode structure for detecting a memory or data state of the storage cells, wherein the device comprises a phase-change data storage layer capable of changing states in response to the beams from the emitters, and a second layer forming one layer in the layered diode structure, the second layer comprising a material containing copper, indium and selenium. A method of forming a diode structure for a phase-change data storage array, having multiple thin film layers adapted to form a plurality of data storage cell diodes, comprises depositing a first diode layer of CuInSe material on a substrate and depositing a second diode layer of phase-change material on the first diode layer.

Abstract: A method for fabricating a dual-gate semiconductor device is disclosed.

Abstract: A quantum logic gate utilizes an inter-polarization (dipole—dipole) interaction between excitons having polarization in semiconductor quantum well structures, or a spin exchange interaction between spin polarized excitons in the semiconductor quantum well structures. Problems associated with conventional semiconductor quantum well structures are solved in that a phase relaxation time is very short because of using inter-subband electrons, and that there is no usable ultrashort optical pulse laser technology because a subband transition wavelength is in a far-infrared region and hence ultra fast control is impossible.

Abstract: A capacitor includes an array of first conductive units and an array of second conductive units. Each of the first conductive units includes a hollow first conductive post that has lateral sides. The first conductive posts of the first conductive units are interconnected to form a grid that defines a plurality of lattices. Each of the second conductive units includes a second conductive post that is disposed in a respective one of the lattices and that has lateral sides that are surrounded by the lateral sides of the first conductive post of a respective one of the first conductive units. The first conductive post of each of the first conductive units and the second conductive post of the respective one of the second conductive units cooperatively define a charge space. A dielectric material fills the charge space.

Abstract: In a semiconductor device having an N-channel MOS transistor and a P-channel MOS transistor, each of the N-channel and P-channel MOS transistors is made up of a polycrystal silicon layer, a gate insulating film, and a gate electrode containing a gate polysilicon on a glass substrate. A method of manufacturing the semiconductor device includes the steps of injecting an impurity into the gate polysilicon at a same time as or in a different step of impurity injection at a time of formation of source/drains of the MOS transistors or formation of an LDD (Lightly Doped Drain), to make an N-type of a gate polysilicon in the N-channel MOS transistor and make a P-type of a gate polysilicon in the P-channel MOS transistor and, furthermore, setting a thickness of the polycrystal silicon layer less than the width of a depletion layer which occurs when an inversion channel is formed. Thus, fluctuations in values of threshold voltages of the MOS transistors are reduced to realize low-voltage driving.

Abstract: The semiconductor device comprising a chalcogenide phase change material. The chalcogenide material being programmed from one resistance state to another resistance state by applying a programming current to a resistor which is in thermal contact with the chalcogenide material. The semiconductor device may be used as memory element or as a programmable fuse.

Abstract: A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s). A portion of the encapsulation material is removed to expose a back surface of the microelectronic die which has a metallization layer disposed thereon. A protective layer is disposed on the metallization layer prior to encapsulation, such that when the portion of the encapsulation material is removed, the protective layer prevents the metallization layer from being damaged. After the portion of the encapsulation material is removed, the protective layer is removed and the metallization layer is exposed. A heat spreader may then be attached to the microelectronic die by abutting the heat spreader against the metallization layer and reflowing the metallization layer.

Abstract: One embodiment of the present invention is a method for making metallic interconnects, which method is utilized at a stage of processing a substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the field and the at least one opening being ready for depositing of one or more seed layers, which method includes steps of: (a) depositing a substantially conformal seed layer over the field and inside surfaces of the at least one opening; (b) depositing a substantially non-conformal seed layer over the substantially conformal seed layer, said substantially non-conformal seed layer being thicker than said substantially conformal seed layer over the field, wherein the substantially conformal and the substantially non-conformal seed layers do not seal the at least one opening; and (c) electroplating a metallic layer over the substantially non-conformal seed layer, wherein the electroplated metallic layer comprises a material selected from a gr

Abstract: A product information providing apparatus is connected to a product information management apparatus having product information management data. The product information providing apparatus is capable of bidirectional communication via a communication network to a remote terminal, and includes receiving means for receiving from the remote terminal a request command requesting transmission of product information management data concerning a specified product via the communication network. Also, the product information providing apparatus includes obtaining means for obtaining from the product information management apparatus, in response to the request command, the product information management data concerning the specified product. The product information providing apparatus further includes transmitting means for transmitting to the remote terminal the obtained product information management data concerning the specified product.

Abstract: A semiconductor device in which a vertical pnp-bipolar transistor is formed in a prescribed element region on a semiconductor substrate includes: a buried n+-layer of a high concentration formed in the prescribed element region; and a p-type collector layer formed on the buried n+-layer. By introducing impurities that has a larger diffusion coefficient than the buried n+-layer, the collector layer can be formed on the buried n+-layer formed in common with other element regions, without any special masking.

Abstract: The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance of load capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the memory cell array, and a ferroelectric memory device. In the memory cell array, memory cells formed of ferroelectric capacitors are arranged in a matrix. The ferroelectric capacitors include first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and ferroelectric layers disposed linearly along either the first signal electrodes or the second signal electrodes. Alternatively, the ferroelectric layers may be disposed only in intersection areas of the first and second signal electrodes.