Abstract: A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.

Abstract: A method of fabricating a semiconductor device includes forming first and second gate dielectric layers on first and second regions of a semiconductor substrate, respectively, forming a first metal-containing layer on the first and second gate dielectric layers, performing a first annealing process with respect to the first metal-containing layer, removing the first metal-containing layer from the first region, forming a second metal-containing layer on an entire surface of the semiconductor substrate, performing a second annealing process with respect to the second metal-containing layer, forming a gate electrode layer on the second metal-containing layer, and partially removing the gate electrode layer, the second metal-containing layer, the first metal-containing layer, the first gate dielectric layer, and the second gate dielectric layer to form first and second gate patterns on the first and second regions, respectively.

Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

Abstract: A system and approach of importing data from site controllers as history imports with a history service by a supervisor in conjunction with a host processor. The history service may reconfigure the history imports to provide the history service virtually full control over the history imports. The history service may runs a history import cycle to ensure that virtually all enabled history imports are performed. The history service may establish a list of history imports to be processed at a beginning of the history import cycle. The history import cycle may query virtually all history imports in an order on a last success time of a history import operation where an oldest time is first on the list. The history service may ensure a maximum number of history imports are running by querying for a count of history imports of an in progress state.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a channel pattern on a substrate, the channel pattern extending in a first direction; a gate pattern on the substrate, the gate pattern extending in a second direction crossing the first direction and surrounding the channel pattern; and an interface layer between the channel pattern and the gate pattern, the interface layer being formed on at least one surface of an upper surface and a lower surface of the channel pattern.

Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

Abstract: Manufacturing of a device to connect at least one nano-object to an external electrical system, comprising a support provided with a semiconducting layer in which the first doped zones are formed at a spacing from each other, an external electrical system being connectable to the first doped zones, each first doped zone (8a, 8b) being in contact with a second doped zone on which a portion of the nano-object is located, the second doped zones being separated from each other and with a thickness less than the thickness of the first doped zones.

Abstract: A light emitting device includes a plurality of light emitting elements, a light transmissive member, a first member and a second member. Each of the light emitting elements has a pair of electrodes on a lower surface thereof. The light-transmissive member is disposed on an upper surface of each of the light emitting elements to transmit light from the light emitting elements. The first member is disposed on one or more lateral surfaces of the light-transmissive member and constitutes part of an upper surface of the light emitting device. The second member surrounds an outer periphery of each of the light emitting elements and constitutes part of a lower surface of the light emitting device. Lower surfaces of the electrodes are exposed from the second member.

Abstract: A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.

Abstract: A ferroelectric heterostructure may comprise a ferroelectric layer comprising a ferroelectric material and a first electrode layer comprising a first noncentrosymmetric metal, the first electrode layer disposed on the ferroelectric layer to form a ferroelectric-first electrode interface, wherein the ferroelectric layer is characterized by exhibiting an electric polarization and the first electrode layer is characterized by exhibiting polar ionic displacements and further wherein, a component of the polar ionic displacements of the first electrode layer is parallel to a component of the electric polarization of the ferroelectric layer.

Abstract: A display device includes a display panel, and a protective member disposed outside the display panel. The circuit layer includes a display area and a non-display area, and a first bending line and a second bending line crossing the first bending line are defined are defined in the non-display area. The non-display area includes: a first non-display area bent from the display area with respect to the first bending line; a second non-display area bent from the display area with respect to the second bending line; and a corner non-display area bent from the second non-display area with respect to the first bending line and bent from the first non-display area with respect to the second bending line. A slit is defined in the protective member, and the slit overlap at least a part of the first bending line and the second bending line.

Abstract: The present disclosure relates to an OLED encapsulation method and an OLED encapsulation structure. The OLED encapsulation method combines the frame glue encapsulation technology and the thin film encapsulation technology. By adopting the frame glue to block the organic layer and to limit the dimension of the organic layer, each of the organic layers can be completely covered by the inorganic layer arranged thereon. At the same time, the inorganic layers may be manufactured by the same mask, which reduces the number of the mask so as to reduce the cost. The OLED encapsulation structure combines the frame glue encapsulation technology and the thin film encapsulation technology. By adopting the frame glue to block the organic layer and to limit the dimension of the organic layer, each of the organic layers can be completely covered by the inorganic layer arranged thereon. At the same time, the inorganic layers may be manufactured by the same mask, which reduces the number of the mask so as to reduce the cost.

Abstract: A display panel and a method for manufacturing the same are disclosed. The display panel includes: a substrate, a display element located on the substrate, and a thin-film encapsulation layer located on the display element. The thin-film encapsulation layer includes at least one first encapsulation material layer and at least one second encapsulation material layer; the refractive index of the first encapsulation material layer is different from that of the second encapsulation material layer; wherein, at least one of the first encapsulation material layers is provided with a plurality of grooves; the grooves are filled with the second encapsulation material layer above the first encapsulation material layer provided with a plurality of grooves.

Abstract: A first lower interconnection structure and a second lower interconnection structure are formed using a first design rule on a first region of a substrate and a second region of the substrate, respectively. A memory element is formed on the first lower interconnection structure. The memory element includes a bottom electrode, a magnetic tunnel junction and a top electrode stacked on each other. An upper conductive line and an upper interconnection line are formed using a second design rule larger than the first design rule on the first lower interconnection structure and the second lower interconnection structure, respectively. The first lower interconnection structure, the memory element and the upper conductive line are stacked on each other so that the memory element is interposed between the first lower interconnection structure and the upper conductive line.

Abstract: A ReRAM device is provided. The ReRAM device comprises a bottom electrode, a resistance switching layer disposed on the bottom electrode, a top electrode disposed on the resistance switching layer, a metal layer disposed on the top electrode, and a blocking layer covering the metal layer, wherein the blocking layer surrounds the metal layer and the top electrode.

Abstract: A data processing system for a chromatograph including a standard sample data storage section; a standard sample sensitivity factor calculator; a post-correction standard sample chromatogram strength calculator; a specific designated retention time and specific designated wavelength setter; a measurement sample data storage section; a measurement sample sensitivity factor calculator; and a post-correction measurement sample chromatogram creator.

Abstract: A semiconductor device includes a substrate, at least one active region, at least one gate structure, and an insulating structure. The active region is present at least partially in the substrate. The gate structure is present on the active region. The gate structure has at least one end sidewall and a top surface intersecting to form a top interior angle. The top interior angle is an acute angle. The insulating structure is present adjacent to the end sidewall of the gate structure and on the substrate.

Abstract: A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.

Abstract: A method of producing a semiconductor device is disclosed in which, after proton implantation is performed, a hydrogen-induced donor is formed by a furnace annealing process to form an n-type field stop layer. A disorder generated in a proton passage region is reduced by a laser annealing process to form an n-type disorder reduction region. As such, the n-type field stop layer and the n-type disorder reduction region are formed by the proton implantation. Therefore, it is possible to provide a stable and inexpensive semiconductor device which has low conduction resistance and can improve electrical characteristics, such as a leakage current, and a method for producing the semiconductor device.

Abstract: Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Some embodiments include an integrated structure having a vertical stack of alternating conductive levels and insulative levels, and having a charge-passage structure extending vertically along the vertical stack. Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels, and having a charge-passage structure extending vertically along the vertical stack.