Patents Examined by Christine Enad
  • Patent number: 10438949
    Abstract: A method for reducing parasitic capacitance of a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming a first source/drain region between the fin structure and the substrate, forming first spacers adjacent the fin structure, forming second spacers adjacent the first source/drain region and recessing the first source/drain region in exposed areas. The method further includes forming a shallow trench isolation (STI) region within the exposed areas of the recessed first source/drain region, depositing a bottom spacer over the STI region, forming a metal gate stack over the bottom spacer, depositing a top spacer over the metal gate stack, cutting the metal gate stack, forming a second source/drain region over the fin structure, and forming contacts such the STI region extends a length between the metal gate stack and the first source/drain region.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Philip J. Oldiges, Wenyu Xu, Chen Zhang
  • Patent number: 10418416
    Abstract: There are provided a memory device and a memory unit that make it possible to improve retention property of a resistance value in low-current writing. The memory device of the technology includes a first electrode, a memory layer, and a second electrode in order, in which the memory layer includes an ion source layer containing one or more transition metal elements selected from group 4, group 5, and group 6 in periodic table, one or more chalcogen elements selected from tellurium (Te), sulfur (S), and selenium (Se), and one or both of boron (B) and carbon (C), and a resistance change layer having resistance that is varied by voltage application to the first electrode and the second electrode.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: September 17, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroaki Sei, Kazuhiro Ohba, Seiji Nonoguchi
  • Patent number: 10416135
    Abstract: A preparative liquid chromatographic apparatus comprising a column for separating components in a sample; a dispensing unit for dispensing an eluate from the column; a detector for the eluate; an analysis unit for the eluate; a display unit for displaying an analysis result a data storage unit; and an arithmetic control unit for controlling the display unit and the data storage unit. The analysis unit has at least one qualitative analysis unit for continuously and qualitatively analyzing the eluate. The display unit simultaneously displays a chromatogram acquired by the detector and the acquisition position of the dispensing unit and displays a correspondence relationship between each fraction and the chromatogram, and wherein by using the correspondence relationship between each fraction and the chromatogram shown in the display unit, the qualitative analysis data selected from the data storage unit is displayed on the display unit using the arithmetic control unit.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: September 17, 2019
    Assignee: YAMAZEN CORPORATION
    Inventor: Kihachiro Okura
  • Patent number: 10411035
    Abstract: Systems and methods herein relate to the fabrication of a single-crystal flexible semiconductor template that may be attached to a semiconductor device. The template fabricated comprises a plurality of single crystals grown by lateral epitaxial growth on a seed layer and bonded to a flexible substrate. The layer grown has portions removed to create windows that add to the flexibility of the template.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: September 10, 2019
    Assignee: UNIVERSITY OF HOUSTON SYSTEMS
    Inventor: Jae-Hyun Ryou
  • Patent number: 10403637
    Abstract: A memory device includes a plurality of stacks of conductive strips alternating with insulating strips, the insulating strips having first and second sides, and the conductive strips having first sidewalls recessed relative to the first sides of the insulating strips which define first recessed regions in sides of the stacks. Vertical channel pillars are disposed between the stacks, the vertical channel pillars having first and second channel films disposed on adjacent stacks and a dielectric material between and contacting the first and second channel films. Data storage structures at cross points of the vertical channel pillars and the conductive strips include tunneling layers in contact with the vertical channel pillars, discrete charge trapping elements in the first recessed regions in contact with the tunneling layers and blocking layers between the discrete charge trapping elements and the first sidewalls of the conductive strips.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: September 3, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hang-Ting Lue
  • Patent number: 10396135
    Abstract: The application provides an OLED substrate, a method for manufacturing the OLED substrate, and a display device. The OLED substrate comprises a plurality of pixel regions, at least one of which is provided with a pixel driving circuit, and includes a display region and a connection region. The OLED substrate comprising: a base; a reflective electrode layer disposed on the base, wherein each reflective electrode is correspondingly disposed in one display region; a pixel defining layer disposed on the reflective electrode layer, wherein the pixel defining layer is provided with a first opening corresponding to the display region and a second opening corresponding to the connection region; a light-emitting material layer disposed in the first opening; a display electrode continuously disposed on the light-emitting material layer and in the second opening, and the display electrodes in the respective pixel regions electrically insulated from each other.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: August 27, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Minghung Hsu
  • Patent number: 10388667
    Abstract: Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Some embodiments include an integrated structure having a vertical stack of alternating conductive levels and insulative levels, and having a charge-passage structure extending vertically along the vertical stack. Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels, and having a charge-passage structure extending vertically along the vertical stack.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Chris M. Carlson, M. Jared Barclay
  • Patent number: 10371684
    Abstract: A system for managing and monitoring a small or large collection of sealed containers, such as wine bottles, barrels, medicine containers, or bags, as well as individual grapes, batches of must, and other liquids, whose contents may be volatile and difficult to access without destroying the seal and the contents or risking contamination of the liquid. The system performs automated monitoring tasks by communicating with specially manufactured bottles or traditional bottles that have had a sensor installed. Sensor installation can be accomplished with unmodified commercialy available equipment.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: August 6, 2019
    Inventor: Mohsen Rezayat
  • Patent number: 10374066
    Abstract: A semiconductor structure and a method for fabricating the same. The structure includes a substrate, active fin structures, and non-active fin structures. The structure further includes isolation regions in contact with the active fin structures, and isolation regions in contact with the non-active fin structures. A first gate structure is in contact with the active fin structures and the isolation regions that are in contact with the active fin structures. A second gate structure is in contact with the non-active fin structures. The method includes forming an isolation region between fin structures. A mask is formed over active fin structures and dummy fin structures are then removed to form a plurality of trenches between the isolation regions. A nitride-based layer is formed in contact with isolation regions corresponding to the dummy fin structures. The nitride-based layer forms a non-active fin structure within each trench of the trenches.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventor: Soon-Cheon Seo
  • Patent number: 10374102
    Abstract: A semiconductor device includes first to fourth semiconductor regions, and first and second electrodes. The second semiconductor region is selectively disposed in a surface layer of one main surface of the first semiconductor region. The first electrode is in contact with a contact region of the second semiconductor region. The third semiconductor region is disposed in a surface layer on another main surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region. The second electrode is in contact with the third semiconductor region. The fourth semiconductor region of the second conductivity type is disposed in the first semiconductor region, and disposed closer to the one main surface than the third semiconductor region. The fourth semiconductor region is disposed at least within the contact region in a plan view.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: August 6, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi Onozawa, Takashi Yoshimura, Hiroshi Takishita
  • Patent number: 10366984
    Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10361311
    Abstract: A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: July 23, 2019
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES INC.
    Inventors: Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie
  • Patent number: 10361269
    Abstract: A method of forming a semiconductor structure includes forming a multi-layer structure. The multi-layer structure has a substrate and two or more nanosheet layers formed above the substrate. The method also includes forming a bottom isolation layer between the substrate and the two or more nanosheet layers. The method further includes performing a fin reveal in the multi-layer structure after formation of the bottom isolation layer to form a fin. The two or more nanosheet layers provide a channel stack for a nanosheet field-effect transistor.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chun W. Yeung, Chen Zhang
  • Patent number: 10359405
    Abstract: A specimen information storage section (361) holds specimen information showing the relationship between a number of specimens to be analyzed and compounds whose quantities need to be determined. An analysis method storage section (362) holds the files of analysis methods created by an administrator. When an operator selects and indicates analysis methods to be used in an analysis, a method information creation processor (32) extracts compound information from the selected analysis methods and creates method information showing the correspondence between the analysis methods and the compounds to be analyzed. When the operator registers the specimen numbers of the analysis targets, a used-method automatic determiner (34) refers to the specimen information and method information to identify a suitable analysis method for each compound in the registered specimens. An analysis schedule creator (35) creates a schedule table in which the specimens and analysis methods are described in order of the analysis.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: July 23, 2019
    Assignee: SHIMADZU CORPORATION
    Inventor: Kiriko Matsuo
  • Patent number: 10361386
    Abstract: Provided is a planar light emitting device which is highly productive employing inexpensive FPCs capable of being easily electrically connected, and which has a light emitting region with reduced unevenness in luminance and hence is highly reliable. The planar light emitting device, which has a light emitting surface and a back surface, includes a planar light emitting tile including a planar light emitting element and a plurality of flexible printed circuits (FPCs) disposed on the back surface. The planar light emitting tile includes a non-pad region where none of an anode pad and a cathode pad are disposed. In an overlapped region where part of two circuit boards overlap each other, an electrical connection site where an equipotential region of the two circuit boards are directly electrically connected to each other is formed. The non-pad region forms a connecting-part disposed region that overlaps with the electrical connection site.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: July 23, 2019
    Assignee: KANEKA CORPORATION
    Inventor: Hidemaro Saiki
  • Patent number: 10355105
    Abstract: A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Ming-Hua Yu
  • Patent number: 10347180
    Abstract: An organic light-emitting pixel driving circuit, a driving method thereof, and an organic light-emitting display panel are provided. The organic light-emitting pixel driving circuit comprises a light-emitting element, a driving transistor for driving the light-emitting element, an initialization unit, a storage unit, a data write-in unit, and a light-emitting control unit. The initialization unit is configured to transmit a first power supply voltage signal to a gate electrode of the driving transistor and transmit a reference voltage signal to a source electrode of the driving transistor and an anode of the light-emitting element. The storage unit is configured to maintain a voltage signal transmitted to the driving transistor. The data write-in unit is configured to transmit a data voltage signal to the gate electrode of the driving transistor, thus compensating a threshold voltage of the driving transistor. The light-emitting control unit is configured to control the light-emitting element.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: July 9, 2019
    Assignees: Shanghai Tianma AM-OLED Co., Ltd., Tianma Micro-Electronics Co., Ltd.
    Inventors: Renyuan Zhu, Yue Li, Tong Wu
  • Patent number: 10347712
    Abstract: A method for fabricating semiconductor device includes: forming a metal-oxide semiconductor (MOS) transistor on a substrate; forming a first interlayer dielectric (ILD) layer on the MOS transistor; removing part of the first ILD layer to form a trench adjacent to the MOS transistor; forming a trap rich structure in the trench; forming a second ILD layer on the MOS transistor and the trap rich structure; forming a contact plug in the first ILD layer and the second ILD layer and electrically connected to the MOS transistor; and forming a metal interconnection on the second ILD layer and electrically connected to the contact plug.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: July 9, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Chia-Huei Lin, Kuo-Yuh Yang
  • Patent number: 10347759
    Abstract: Techniques relate to forming a vertical field effect transistor (FET). One or more fins are formed on a bottom source or drain of a substrate, and one or more fins extend in a vertical direction. Gate material is formed to be positioned on sides of the one or more fins. Gate encapsulation material is formed on sides of the gate material to form a trench, such that top portions of the one or more fins are exposed in the trench. A top source or drain is formed on top of the one or more fins such that the top source or drain is laterally confined by the trench in a lateral direction that is parallel to the one or more fins.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Huiming Bu, Fee Li Lie, Edward J. Nowak, Junli Wang
  • Patent number: 10340352
    Abstract: Device structures for a field-effect transistor and methods for forming a device structure for a field-effect transistor. A first dielectric layer is formed, and a second dielectric layer are formed on the first dielectric layer. An opening is formed that extends vertically through the first and second dielectric layers. After the first opening is formed, the second dielectric layer is laterally recessed relative to the first dielectric layer with a selective etching process, which widens a portion of the opening extending vertically through the second dielectric layer relative to a portion of the opening extending vertically through the first dielectric layer. After the second dielectric layer is laterally recessed, a gate electrode is formed that includes a narrow section in the portion of the opening extending vertically through the first dielectric layer and a wide section in the portion of the opening extending vertically through the second dielectric layer.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven M. Shank, Alvin J. Joseph, John J. Ellis-Monaghan