Patents Examined by Christine Enad
  • Patent number: 12040387
    Abstract: Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Feng Young, Chih-Yu Chang, Sai-Hooi Yeong, Chi On Chui, Chih-Hao Wang
  • Patent number: 12033897
    Abstract: A method for forming a semiconductor structure includes forming a first FET device and a second FET device over a substrate. Forming a first gate trench in the first FET device and a second gate trench in the second FET device. Forming a first high-k gate dielectric layer in the first gate trench, and a second high-k gate dielectric layer in the second gate trench. Forming a first barrier layer over the first high-k gate dielectric layer, and a second barrier layer over the second high-k gate dielectric layer. Increasing N nitridations in the first and second barrier layers. Removing the second barrier layer to expose the second high-k gate dielectric layer. Forming a first work function metal layer over the first barrier layer and a second work function metal layer over the second high-k gate dielectric layer.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chien-Hao Chen
  • Patent number: 12034061
    Abstract: A method for forming a semiconductor structure includes forming a gate structure over a substrate. The method also includes forming a spacer on a sidewall of the gate structure. The method also includes forming a source/drain recess beside the spacer. The method also includes treating the source/drain recess and partially removing the spacers in a first cleaning process. The method also includes treating the source/drain recess with a plasma process after performing the first cleaning process. The method also includes treating the source/drain recess in a second cleaning process after treating the source/drain recess with the plasma process. The method also includes forming a source/drain structure in the source/drain recess after performing the second cleaning process.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Wei Lee, Yen-Ru Lee, Hsueh-Chang Sung, Yee-Chia Yeo
  • Patent number: 12033900
    Abstract: The present disclosure describes a semiconductor device having metal boundary trench isolation with electrically conductive intermediate structures acting as a metal diffusion barrier. The semiconductor structure includes a first fin structure and a second fin structure on a substrate, an insulating layer between the first and second fin structures, a gate dielectric layer on the insulating layer and the first and second fin structures, and a first work function stack and a second work function stack on the gate dielectric layer. The first work function stack is over the first fin structure and a first portion of the insulating layer, and the second work function stack is over the second fin structure and a second portion of the insulating layer adjacent to the first portion. The semiconductor structure further includes a conductive intermediate structure on the gate dielectric layer and between the first and second work function stacks.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: July 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Yuh-Ta Fan, Tien-Wei Yu
  • Patent number: 12027625
    Abstract: A method includes providing a semiconductor structure including a first semiconductor substrate, an insulator layer over the first semiconductor substrate, and a second semiconductor substrate over the insulator layer; patterning the second semiconductor substrate to form a top fin portion over the insulator layer; conformally depositing a protection layer to cover the top fin portion, wherein a first portion of the protection layer is in contact with a top surface of the insulator layer; etching the protection layer to remove a second portion of the protection layer directly over the top fin portion while a third portion of the protection layer still covers a sidewall of the top fin portion; etching the insulator layer by using the third portion of the protection layer as an etch mask; and after etching the insulator layer, removing the third portion of the protection layer.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: July 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Hao Kuo, Jung-Hao Chang, Chao-Hsien Huang, Li-Te Lin, Kuo-Cheng Ching
  • Patent number: 12027609
    Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin extending from a substrate. A sacrificial gate electrode layer is formed along a sidewall and a top surface of the fin. A patterning process is performed on the sacrificial gate electrode layer to form a sacrificial gate electrode. A reshaping process is performed on the sacrificial gate electrode to form a reshaped sacrificial gate electrode. The reshaped sacrificial gate electrode includes a first portion along the top surface of the fin and a second portion along the sidewall of the fin. A width of the first portion decreases as the first portion extends from a top surface of the first portion toward the top surface of the fin. A width of the second portion decreases as the second portion extends from the top surface of the fin toward the substrate.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: July 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Shang Hsiao, Ying Ming Wang, Ying Hsin Lu
  • Patent number: 12021084
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction. The gate structure includes a first portion and a second portion separated by the gate isolation structure and the dielectric fin. The first portion of the gate structure presents a first beak profile and the second portion of the gate structure presents a second beak profile. The first and second beak profiles point toward each other.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: June 25, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao Lin, Chih-Han Lin, Ming-Ching Chang, Shu-Yuan Ku, Tzu-Chung Wang
  • Patent number: 12021008
    Abstract: 3D semiconductor packages and methods of forming 3D semiconductor package are described herein. The 3D semiconductor packages are formed by mounting a die stack on an interposer, dispensing a thermal interface material (TIM) layer over the die stack and placing a heat spreading element over and attached to the die stack by the TIM layer. The TIM layer provides a reliable adhesion layer and an efficient thermally conductive path between the die stack and interposer to the heat spreading element. As such, delamination of the TIM layer from the heat spreading element is prevented, efficient heat transfer from the die stack to the heat spreading element is provided, and a thermal resistance along thermal paths through the TIM layer between the interposer and heat spreading element are reduced. Thus, the TIM layer reduces overall operating temperatures and increases overall reliability of the 3D semiconductor packages.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu
  • Patent number: 12020950
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. In some embodiments, a method is provided. The method includes following operations. A sacrificial gate structure is formed over a fin structure. The sacrificial gate structure includes a sacrificial gate layer and a sacrificial dielectric layer. The sacrificial gate layer is removed to form a gate trench exposing the sacrificial dielectric layer. A doped region is formed in the fin structure covered by the sacrificial dielectric layer. The sacrificial dielectric layer, a portion of the doped region and a portion of the fin structure are removed from the gate trench. An interfacial layer is formed over the fin structure in the gate trench.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Sheng Chen, Siao-Jing Li, Yi-Jing Li
  • Patent number: 12015039
    Abstract: The present technology relates to an image pickup device and an electronic apparatus that are configured to enhance characteristics. A solid-state image pickup device includes a photoelectric conversion section that is arranged on a semiconductor substrate and configured to photoelectrically convert an incident light, a moth-eye section that includes recesses and projections formed on a surface on a light incident side in the semiconductor substrate and has, when a cross section approximately parallel to a direction toward the photoelectric conversion section from the light incident side is viewed, a recessed portion protruding toward the side of the photoelectric conversion section, the recessed portion having a curvature or a polygonal shape, and a region that is arranged adjacent to and opposite to the photoelectric conversion section of the moth-eye section and has a refractive index different from a refractive index of the semiconductor substrate.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: June 18, 2024
    Assignee: Sony Group Corporation
    Inventors: Satoe Miyata, Itaru Oshiyama
  • Patent number: 12016220
    Abstract: A stretchable display panel and a display device are provided. The stretchable display panel includes a center display area, a transition display area, and a wiring area, and in a direction from the center display area to the wiring area, a width of bridge structures in the transition display area gradually increases. Island structures located at a peripheral area include an edge bridge structure, and through meeting of adjacent edge bridge structures, a width of the edge bridge structures is increased to increase tensile strength of the edge bridge structures, decreasing risk of wires breaking in the transition display area.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: June 18, 2024
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Wenqiang Wang
  • Patent number: 12009428
    Abstract: A semiconductor device including nanosheet field-effect transistors (NSFETs) in a first region and fin field-effect transistors (FinFETs) in a second region and methods of forming the same are disclosed. In an embodiment, a device includes a first memory cell, the first memory cell including a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chuan Yang, Kuo-Hsiu Hsu, Feng-Ming Chang, Kian-Long Lim, Lien Jung Hung
  • Patent number: 12009406
    Abstract: A semiconductor device includes a fin extending from a substrate, a gate stack over and along a sidewall of the fin, a spacer along a first sidewall of the gate stack and the sidewall of the fin, a dummy gate material along the sidewall of the fin, wherein the dummy gate material is between the spacer and the gate stack, and a first epitaxial source/drain region in the fin and adjacent the gate stack.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 12002714
    Abstract: A method of forming a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, removing portions of the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a first titanium nitride layer wrapping around the nanosheets, wherein an atomic ratio of titanium to nitrogen of the first titanium nitride layer is less than 1, and forming a metal fill layer over the first titanium nitride layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi Lee, Kuan-Yu Wang, Cheng-Lung Hung, Chi-On Chui
  • Patent number: 11996470
    Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes second spacers over the semiconductor fin. The second spacers vertically extend farther from the semiconductor fin than the first spacers. The semiconductor device includes a metal gate over the semiconductor fin, the metal gate is sandwiched by the first spacers. The metal gate includes a glue layer that contains tantalum nitride.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jian-Jou Lian, Tzu Ang Chiang, Ming-Hsi Yeh, Chun-Neng Lin, Po-Yuan Wang, Chieh-Wei Chen
  • Patent number: 11991898
    Abstract: A display device according to an exemplary embodiment of the present disclosure can include a back cover, a display panel disposed on the back cover, a polarizing plate disposed on the display panel, a barrier film disposed on the polarizing plate, and a side film which has one end disposed between the back cover and the display panel and another end disposed between the polarizing plate and the barrier film to enclose side surfaces of the display panel and the polarizing plate. Therefore, the moisture permeation into the polarization layer is delayed, which in turn improves the reliability of the display device.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: May 21, 2024
    Assignee: LG DISPLAY CO., LTD.
    Inventors: JiHun Song, Hoiyong Kwon
  • Patent number: 11990538
    Abstract: Provided is an insulated gate bipolar transistor (IGBT) device. The IGBT device includes p-type body regions located on a top of an n-type drift region, a first n-type emitter region located within the p-type body region; a first gate structure located over the p-type body region, where the first gate structure includes a first gate dielectric layer, a first gate and an n-type floating gate which are located above the first gate dielectric layer, where the n-type floating gate is located on a side close to the n-type drift region in a lateral direction; an insulating dielectric layer located between the n-type floating gate and the first gate; and one opening in the first gate dielectric layer. The n-type floating gate is in contact with the p-type body region to form a p-n junction diode through the one opening.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: May 21, 2024
    Assignee: SUZHOU ORIENTAL SEMICONDUCTOR CO., LTD.
    Inventors: Yi Gong, Rui Wang, Wei Liu, Yuanlin Yuan, Xin Wang
  • Patent number: 11991915
    Abstract: The present application provides a display panel and a display device, the display panel includes a light-emitting layer and a light-concentrating layer positioned on the light-emitting layer, the light-emitting layer includes a plurality of light-emitting units, the light-concentrating layer includes a first member and a second member for converging light, wherein the first member includes a plurality of openings, an edge of the openings includes a first inclined surface for reflecting light and a second inclined surface positioned on the first inclined surface, and the first inclined surface and the second inclined surface are connected by a first connecting portion.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: May 21, 2024
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Haoran Wang, Kan Wang
  • Patent number: 11990376
    Abstract: A semiconductor device and a method of making the same are provided. A method according to the present disclosure includes forming a first type epitaxial layer over a second type source/drain feature of a second type transistor, forming a second type epitaxial layer over a first type source/drain feature of a first type transistor, selectively depositing a first metal over the first type epitaxial layer to form a first metal layer while the first metal is substantially not deposited over the second type epitaxial layer over the first type source/drain feature, and depositing a second metal over the first metal layer and the second type epitaxial layer to form a second metal layer.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Peng-Wei Chu, Sung-Li Wang, Yasutoshi Okuno
  • Patent number: 11984472
    Abstract: A double-sided capacitor structure and a method for forming the same are provided. The method includes: providing a base including a substrate, capacitor contacts in the substrate, a stacked structure on a surface of the substrate, and capacitor holes penetrating through the stacked structure and exposing the capacitor contacts, and the stacked structure includes sacrificial layers and supporting layers which are alternately stacked in a direction perpendicular to the substrate; forming a first electrode layer, a first dielectric layer and a second electrode layer on inner walls of the capacitor holes; filling the capacitor holes with a first conductive material to form a first conductive filling layer; completely removing several of the sacrificial layers and/or the supporting layers to remain at least two of the supporting layers; and forming a second dielectric layer and a third electrode layer that covers a surface of the second dielectric layer.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: May 14, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yong Lu