Abstract: A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface and a recess extending from the first surface towards the second surface, a first die at least partially disposed within the recess and including a first die substrate and a first bonding member disposed over the first die substrate, a second die disposed over the first die and including a second die substrate and a second bonding member disposed a second die substrate and the second die substrate, a redistribution layer (RDL) disposed over the second die, and a conductive bump disposed over the RDL, wherein the first bonding member is disposed opposite to and is bonded with the second bonding member.

Abstract: An organic light emitting diode display includes a substrate, a thin film transistor on the substrate, a first electrode on and connected to the thin film transistor, a pixel defining layer on the first electrode and defining a pixel area, an organic light emitting layer on the first electrode and contacting the first electrode exposed in the pixel area, a second electrode on the organic light emitting layer, and a light blocking layer on the second electrode and exposing the second electrode at a position corresponding to the pixel area. The light blocking layer may include a first metal layer on the second electrode and exposing the second electrode at a position corresponding to the pixel area, a first intermediate layer covering the first metal layer, a second metal layer covering the first intermediate layer, and a second intermediate layer covering the second metal layer.

Abstract: Disclosed herein is a light emitting diode (LED) including: a gallium nitride substrate; a gallium nitride-based first contact layer disposed on the gallium nitride substrate; a gallium nitride-based second contact layer; an active layer having a multi-quantum well structure and disposed between the first and second contact layers; and a super-lattice layer having a multilayer structure and disposed between the first contact layer and the active layer. By employing the gallium nitride substrate, the crystallinity of the semiconductor layers can be improved, and in addition, by disposing the super-lattice layer between the first contact layer and the active layer, a crystal defect that may be generated in the active layer can be prevented.

Abstract: A method for reducing parasitic capacitance of a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming a first source/drain region between the fin structure and the substrate, forming first spacers adjacent the fin structure, forming second spacers adjacent the first source/drain region and recessing the first source/drain region in exposed areas. The method further includes forming a shallow trench isolation (STI) region within the exposed areas of the recessed first source/drain region, depositing a bottom spacer over the STI region, forming a metal gate stack over the bottom spacer, depositing a top spacer over the metal gate stack, cutting the metal gate stack, forming a second source/drain region over the fin structure, and forming contacts such the STI region extends a length between the metal gate stack and the first source/drain region.

Abstract: After forming an epitaxial germanium layer over a germanium-on-insulator substrate including an insulator layer and a doped germanium layer overlying the insulator layer, the doped germanium layer is selectively removed and a passivation layer is formed within a space between the epitaxial germanium layer and the insulator layer that is formed by removal of the doped germanium layer. A lateral bipolar transistor is subsequently formed in the epitaxial germanium layer.

Abstract: A semiconductor package includes an interposer, a semiconductor element installed on a first surface of the interposer, bumps formed on a second surface of the interposer, and a chip component installed on the second surface of the interposer. The interposer is a silicon interposer; the semiconductor element is flip-chip mounted on the first surface of the interposer; the chip component is a thin film passive element formed by carrying out a thin film process on a silicon substrate, and a pad being formed on one surface of the thin film passive element; and the pad of the chip component is connected to a land formed on the second surface of the interposer using a conductive bonding material. According to this structure, the reliability of a bond between the interposer and the chip component of the semiconductor package can be ensured while achieving a small size.

Abstract: A semiconductor device includes a supporting plate including a first surface, a second surface opposite to the first surface, and a through hole extending from the first surface to the second surface; and a semiconductor unit fixed to the first surface. The semiconductor unit includes an insulating plate, a circuit plate fixed to a front surface of the insulating plate, a semiconductor chip fixed to the circuit plate, and a protruding metal block fixed to a rear surface of the insulating plate and penetrating through the through hole to extend to the second surface.

Abstract: A semiconductor device includes a pillar-shaped semiconductor layer and a first gate insulating film around the pillar-shaped semiconductor layer. A metal gate electrode is around the first gate insulating film and a metal gate line is connected to the gate electrode. A second gate insulating film is around a sidewall of an upper portion of the pillar-shaped semiconductor layer and a first contact made of a second metal surrounds the second gate insulating film. An upper portion of the first contact is electrically connected to an upper portion of the pillar-shaped semiconductor layer, and a third contact resides on the metal gate line. A lower portion of the third contact is made of the second metal.

Abstract: A method of producing a semiconductor device is disclosed in which, after proton implantation is performed, a hydrogen-induced donor is formed by a furnace annealing process to form an n-type field stop layer. A disorder generated in a proton passage region is reduced by a laser annealing process to form an n-type disorder reduction region. As such, the n-type field stop layer and the n-type disorder reduction region are formed by the proton implantation. Therefore, it is possible to provide a stable and inexpensive semiconductor device which has low conduction resistance and can improve electrical characteristics, such as a leakage current, and a method for producing the semiconductor device.

Abstract: Deterioration in reliability is prevented regarding a semiconductor device. The deterioration is caused when an insulating film for formation of a sidewall is embedded between gate electrodes at the time of forming sidewalls having two kinds of different widths on a substrate. A sidewall-shaped silicon oxide film is formed over each sidewall of a gate electrode of a low breakdown voltage MISFET and a pattern including a control gate electrode and a memory gate electrode. Then, a silicon oxide film beside the gate electrode is removed, and a silicon oxide film is formed on a semiconductor substrate, and then etchback is performed. Accordingly, a sidewall, formed of a silicon nitride film and the silicon oxide film, is formed beside the gate electrode, and a sidewall, formed of the silicon nitride film and the silicon oxide films, is formed beside the pattern.

Abstract: A method for integrating a vertical transistor and a three-dimensional channel transistor includes forming narrow fins and wide fins in a substrate; forming a first source/drain (S/D) region at a base of the narrow fin and forming a gate dielectric layer and a gate conductor layer over the narrow fin and the wide fin. The gate conductor layer and the gate dielectric layer are patterned to form a vertical gate structure and a three-dimensional (3D) gate structure. Gate spacers are formed over sidewalls of the gate structures. A planarizing layer is deposited over the vertical gate structure and the 3D gate structure. A top portion of the narrow fin is exposed. S/D regions are formed on opposite sides of the 3D gate structure to form a 3D transistor, and a second S/D region is formed on the top portion of the narrow fin to form a vertical transistor.

Abstract: The present invention relates to semiconductor materials that include a silicon-based quantum dot; and a conjugated organic ligand connected to the silicon-based quantum dot to obtain a functionalized quantum dot. An additional aspect of the present invention is to provide methods that include providing a silicon-based quantum dot; and connecting a conjugated organic ligand connected to the silicon-based quantum dot to obtain a functionalized quantum dot.

Abstract: Systems and methods herein relate to the fabrication of a single-crystal flexible semiconductor template that may be attached to a semiconductor device. The template fabricated comprises a plurality of single crystals grown by lateral epitaxial growth on a seed layer and bonded to a flexible substrate. The layer grown has portions removed to create windows that add to the flexibility of the template.

Abstract: In a method for manufacturing a semiconductor device, a doped layer is formed in a substrate. A barrier layer that is in contact with the doped layer is formed. A semiconductor layer is formed over the substrate and the barrier layer. A fin structure is formed by patterning the semiconductor layer, the barrier layer, and the doped layer such that the fin structure includes a channel region including the semiconductor layer and a well region including the doped layer. An isolation insulating layer is formed such that a first portion of the fin structure protrudes from the isolation insulating layer and a second portion of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over the fin structure and the isolation insulating layer.

Abstract: Described herein are devices and methods related to fabrication of organic electroluminescent devices and related components. In certain embodiments, devices and methods for fabricating OLED panels on substrates with non-uniform reflection or un-even surfaces require that the non-uniform features are arranged in a way such that they are not presented in the region where photolithography features are needed. In certain embodiments, where precision processing such as photolithography features are needed, the substrate is designed to be flat.

Abstract: A light emitting device package includes a cell array including a plurality of semiconductor light emitting units, and having a first surface and a second surface opposite the first surface, each of the plurality of semiconductor light emitting units having a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer stacked on each other.

Abstract: A method of forming a REO dielectric layer and a layer of a-Si between a III-N layer and a silicon substrate. The method includes depositing single crystal REO on the substrate. The single crystal REO has a lattice constant adjacent the substrate matching the lattice constant of the substrate and a lattice constant matching a selected III-N material adjacent an upper surface. A uniform layer of a-Si is formed on the REO. A second layer of REO is deposited on the layer of a-Si with the temperature required for epitaxial growth crystallizing the layer of a-Si and the crystallized silicon being transformed to amorphous silicon after transferring the lattice constant of the selected III-N material of the first layer of REO to the second layer of REO, and a single crystal layer of the selected III-N material deposited on the second layer of REO.

Abstract: A manufacturing method of a semiconductor device according to the present invention comprises cleaning a semiconductor substrate. A first chemical liquid for forming a water-repellent protection film and a second chemical liquid coating the first chemical liquid are supplied on a surface of the semiconductor substrate. Alternatively, the semiconductor substrate is immersed in the first chemical liquid coated with the second chemical liquid. The semiconductor substrate is then dried.

Abstract: Field effect transistor stacks include a first field-effect transistor having a source finger, a drain finger, and a gate finger interposed therebetween, the source finger and the drain finger of the first field-effect transistor being separated by a first drain-to-source distance, and a second field-effect transistor in a series connection with the first field-effect transistor, the second field-effect transistor having a source finger, a drain finger, and a gate finger interposed therebetween, the source finger and the drain finger of the second field-effect transistor being separated by a second drain-to-source distance that is different than the first drain-to-source distance.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor body with a horizontal surface. An epitaxy hard mask is formed on the horizontal surface. An epitaxial region is formed by selective epitaxy on the horizontal surface relative to the epitaxy hard mask so that the epitaxial region is adjusted to the epitaxy hard mask. The epitaxial region is polished by a chemical-mechanical polishing process stopping on the epitaxy hard mask. A vertical trench is formed in the semiconductor body. An insulated field plate is formed in a lower portion of the vertical trench and an insulated gate electrode is formed above the insulated field plate. Further, a method for forming a field-effect semiconductor device is provided.