Abstract: A semiconductor device includes a substrate having first and second regions, first fin groups spaced along a first direction on the first region, each of the first fin groups including adjacent first and second fins having longitudinal directions in a second direction intersecting the first direction, and third to fifth fins spaced along a third direction on the second region, the third to fifth fins having longitudinal directions in a fourth direction intersecting the third direction. The third through fifth fins are at a first pitch, the first and second fins are at a second pitch equal to or smaller than the first pitch, each of the first fin groups is at a first group pitch greater than three times the first pitch and smaller than four times the first pitch, and a width of the first and second fins is same as width of the third fin.

Abstract: A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks.

Abstract: An illustrative device disclosed herein includes a semiconductor substrate and a FinFET transistor device positioned above the semiconductor substrate, wherein the FinFET transistor device has a single active fin structure. The device also includes an electrically inactive dummy fin structure positioned adjacent the single active fin structure, wherein the electrically inactive dummy fin structure is electrically inactive with respect to electrical operation of the FinFET transistor having the single active fin.

Abstract: A panel comprises a substrate; a transistor disposed on the substrate and including: a source electrode, a drain electrode, a gate electrode, a gate insulation layer, an active layer, an auxiliary source electrode configured to electrically connect one end of the active layer to the source electrode, and an auxiliary drain electrode configured to electrically connect an other end of the active layer to the drain electrode; and a capacitor disposed on the substrate and including a first plate and a second plate. The first plate of the capacitor is made of a same material as the auxiliary source electrode and the auxiliary drain electrode.

Abstract: A back-side illuminated imaging device includes a substrate including a photoelectric conversion region, a contact plug connecting a wiring layer and the substrate, and a capacitive element including a first metal electrode and a second metal electrode disposed between the first metal electrode and the substrate. A distance between the second metal electrode and the substrate is shorter than a length of the contact plug. The second metal electrode overlaps at least a part of the photoelectric conversion region in a planar view with respect to a main surface of the substrate.

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.

Abstract: A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes forming a source/drain recess adjacent to the gate structure. The method also includes wet cleaning the source/drain recess in a first wet cleaning process. The method also includes treating the source/drain recess with a plasma process. The method also includes wet cleaning the source/drain recess in a second wet cleaning process after treating the source/drain recess via the plasma process. The method also includes growing a source/drain epitaxial structure in the source/drain recess.

Abstract: Disclosed is an LDMOS device comprising a drift region formed by a selected area of a doped layer of a first conductivity type on a semiconductor substrate, a gate structure comprising a gate dielectric layer and a gate conductive layer which are sequentially formed on a surface of the doped layer of the first conductivity type, a doped self-aligned channel region of a second conductivity type, and a doped layer formed by tilted ion implantation with a first side face of the gate structure as a self-alignment condition. A method for manufacturing an LDMOS device is further disclosed. The channel length is not affected by lithography and thus can be minimized to fulfill an ultralow specific-on-resistance, and the distribution uniformity of the channel length can be improved, so that the performance uniformity of the device is improved.

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a first set of transistor fins and a first set of contact metallization. An upper device layer is bonded onto the lower device layer, where the upper device layer includes a second structure comprising a second set of transistor fins and a second set of contact metallization. At least one power isolation wall extends from a top of the upper device layer to the bottom of the lower device layer, wherein the power isolation wall is filled with a conductive material such that power is routed between transistor devices on the upper device layer and the lower device layer.

Abstract: A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.

Abstract: A semiconductor device having a gate structure and a method of forming same are provided. The semiconductor device includes a substrate and a gate structure over the substrate. The substrate has a first region and a second region. The gate structure extends across an interface between the first region and the second region. The gate structure includes a first gate dielectric layer over the first region, a second gate dielectric layer over the second region, a first work function layer over the first gate dielectric layer, a barrier layer along a sidewall of the first work function layer and above the interface between the first region and the second region, and a second work function layer over the first work function layer, the barrier layer and the second gate dielectric layer. The second work function layer is in physical contact with a top surface of the first work function layer.

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, first and second source/drain regions arranged on the fin-type active region; a first source/drain contact pattern connected to the first source/drain region and including a first segment having a first height in a vertical direction, a second source/drain contact pattern connected to the second source/drain region and including a second segment having a second height less than the first height in the vertical direction, and an insulating capping line extending on the gate line in the second horizontal direction and including an asymmetric capping portion between the first segment and the second segment, the asymmetric capping portion having a variable thickness in the first horizontal direction.

Abstract: Disclosed are multi-junction light emitting diode (LED) formed by using eutectic bonding and method of manufacturing the multi-junction LED. The multi-junction LED is formed by stacking a separately formed light emitting structure on another light emitting structure by using eutectic bonding. Since separately grown light emitting structure is stacked on the light emitting structure using the eutectic metal alloy bonding, it is possible to prevent crystal defects occurring between the light emitting structures when sequentially grown. Further, since the eutectic metal alloy can be formed in various patterns, it is possible to control and optimize adhesive strength, transmittance of the light generated in the upper light emitting structure, and resistance.

Abstract: A solid state imaging device including a semiconductor layer comprising a plurality of photodiodes, a first antireflection film located over a first surface of the semiconductor layer, a second antireflection film located over the first antireflection film, a light shielding layer having side surfaces which are adjacent to at least one of first and the second antireflection film.

Abstract: The invention provides an OLED display panel and manufacturing method thereof. The manufacturing method of OLED display panel of the invention forms a first scattering layer on the thin film encapsulation layer, a quantum dot layer on the first scattering layer, and a second scattering layer on the quantum dot layer. The first scattering layer extracts light from the OLED device, so that the light totally reflected by OLED device through thin film encapsulation layer is emitted as much as possible; the light extracted by the first scattering layer reaches the quantum dot layer. The quantum dots are excited to perform light color matching to emit light of desired color. Since the light excited by quantum dot layer is dispersed, the second scattering layer extracts the light excited by the quantum dot layer in an orderly manner, so that the OLED display panel emits light uniformly, thereby improving luminous efficiency.

Abstract: Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

Abstract: The structure of a semiconductor device with core-shell nanostructured channel regions between source/drain regions of FET devices and a method of fabricating the semiconductor device are disclosed. A semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate, and nanostructured shell regions wrapped around the second nanostructured regions. The nanostructured shell regions and the second nanostructured regions have semiconductor materials different from each other. The semiconductor device further includes first and second source/drain (S/D) regions disposed on the substrate and a gate-all-around (GAA) structure disposed between the first and second S/D regions. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions and the GAA structure is wrapped around each of the nanostructured shell regions.

Abstract: A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.

Abstract: A photosensor including: a first electrode; a second electrode; a photoelectric conversion layer between the first electrode and the second electrode; a first charge blocking layer between the first electrode and the photoelectric conversion layer; a second charge blocking layer between the second electrode and the photoelectric conversion layer; a voltage supply circuit supplying a voltage to the second electrode such that an electric field directed from the second electrode toward the first electrode is generated in the photoelectric conversion layer; and a transistor. The first charge blocking layer suppresses movement of holes from the photoelectric conversion layer to the first electrode and movement of electrons from the first electrode to the photoelectric conversion layer, and the second charge blocking layer suppresses movement of electrons from the photoelectric conversion layer to the second electrode and movement of holes from the second electrode to the photoelectric conversion layer.

Abstract: A method of forming a semiconductor device includes removing a dummy gate from over a semiconductor fin; depositing a glue layer and a fill metal over the semiconductor fin; and simultaneously etching the glue layer and the fill metal with a wet etching solution, the wet etching solution etching the glue layer at a faster rate than the fill metal and reshaping the fill metal.