Abstract: A method of forming a semiconductor device includes removing a dummy gate from over a semiconductor fin; depositing a glue layer and a fill metal over the semiconductor fin; and simultaneously etching the glue layer and the fill metal with a wet etching solution, the wet etching solution etching the glue layer at a faster rate than the fill metal and reshaping the fill metal.

Abstract: A micro-electro-mechanical system (MEMS) device includes a substrate, a proof mass, and a piezoelectric bump. The substrate has a surface. The proof mass is suspended over the surface of the substrate, wherein the proof mass is movable with respect to the substrate. The piezoelectric bump is disposed on the surface of the substrate and extends a distance from the surface of the substrate toward the proof mass.

Abstract: OLED device structures are provided that include an OLED, a high index optical layer (HOL), a thin film barrier disposed over the high index optical layer, and a low index optical layer (LOL) disposed over the thin film barrier. It is shown that such devices provide acceptable color emission that is at least comparable to a conventional device, while also exhibiting improved efficiency and luminance.

Abstract: A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole.

Abstract: The present disclosure relates to the field of display technologies, and in particular, to an OLED display panel, a method of fabricating the same, and a display apparatus. The OLED display panel includes; a base substrate, a plurality of first electrodes located on the base substrate. The OLED display panel include a pixel defining frame, located on the base substrate and separating a plurality of the first electrodes. The pixel defining frame is configured to define a plurality of sub-pixel regions. The OLED display panel includes an organic functional layer located on each of the sub-pixel regions and the pixel defining frame. The organic functional layer has a hollow structure at a position corresponding to the pixel defining frame, and the hollow structure forms an insulation between two adjacent sub-pixel regions in the organic functional later. The OLED display panel includes a second electrode, located on the organic functional layer.

Abstract: MOL non-SAC structures and techniques for formation thereof are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming gates over the fins and source/drains offset by gate spacers; lining upper sidewalls of the gates with a first dielectric liner; depositing a source/drain metal; lining upper sidewalls of the source/drain metal with a second dielectric liner; depositing a dielectric over the gates and source/drains; forming a first via in the dielectric which exposes the second dielectric liner over a select source/drain; removing the second dielectric liner from the select source/drain; forming a second via in the dielectric which exposes the first dielectric liner over a select gate; removing the first dielectric liner from the select gate; forming a source/drain contact in the first via; and forming a gate contact in the second via. A semiconductor device is also provided.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first gate structure and a second gate structure formed over a semiconductor substrate. The semiconductor device structure also includes a first insulating cap structure formed between and adjacent to the first gate structure and the second gate structure. The first insulating cap structure is separated from the semiconductor substrate by a first air gap. The first air gap includes a first portion extending into the first insulating cap structure and a second portion extended from the bottom of the first portion toward the semiconductor substrate. The first portion has a width that is less than the width of the second portion.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming a spacer element over a sidewall of the dummy gate stack. The spacer element has an inner spacer and a dummy spacer, and the inner spacer is between the dummy spacer and the dummy gate stack. The method also includes forming a dielectric layer to surround the spacer element and the dummy gate stack and replacing the dummy gate stack with a metal gate stack. The method further includes removing the dummy spacer of the spacer element to form a recess between the inner spacer and the dielectric layer. In addition, the method includes forming a sealing element to seal the recess such that a sealed hole is formed between the metal gate stack and the dielectric layer.

Abstract: Split gate semiconductor with non-uniform trench oxide. A metal oxide semiconductor field effect transistor (MOSFET) comprises a plurality of parallel trenches. Each such trench comprises a first electrode coupled to a gate terminal of the MOSFET and a second electrode, physically and electrically isolated from the first electrode. The second electrode is beneath the first electrode in the trench. The second electrode includes at least two different widths at different depths below a primary surface of the MOSFET. The trenches may be formed in an epitaxial layer. The epitaxial layer may have a non-uniform doping profile with respect to depth below a primary surface of the MOSFET. The second electrode may be electrically coupled to a source terminal of the MOSFET.

Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a nanosheet field effect transistor (FET) device. The fabrication operations include forming a sacrificial structure over a substrate, wherein the sacrificial structure includes a central region, a first leg at a first end of the central region, and a second leg at a second end of the central region. A nanosheet stack is formed over the central region. An isolation material is deposited within a space that was occupied by the sacrificial structure to form a wrap-around bottom dielectric isolation (BDI) structure having a BDI central region, a first BDI leg at a first end of the BDI central region, and a second BDI leg at a second end of the BDI central region.

Abstract: A wiring circuit board includes a first insulating layer, a terminal, a second insulating layer disposed at one side in a thickness direction of the terminal, and a wire continuous to the terminal in a direction crossing the thickness direction. The first insulating layer has an opening portion passing through the first insulating layer in the thickness direction and having the opening cross-sectional area increasing as being closer to one side in the thickness direction. The terminal has a peripheral end portion and a solid portion. The peripheral end portion contacts with an inner side surface of the first insulating layer. The inner side surface forms the opening portion. The solid portion integrally disposed with the peripheral end portion at the inner side of the peripheral end portion. The peripheral end portion and the solid portion fill the entire opening portion.

Abstract: A system and method for generating air quality scores for air quality within certain locations are presented. The method includes identifying at least one air pollution source within the predetermined perimeter around the at least one location; extracting an air quality score range based on the at least one location from at least one data source; identifying at least one environmental variable based on the at least one location and the at least one time parameter; simulating at least one air pollution measurement based on the at least one environmental variable and the at least one air pollution source; and generating at least one air quality score respective of the air quality score range, wherein the at least one air quality score is based on the at least one air pollution measurement.

Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.

Abstract: A semiconductor device including a first source/drain region at a lower portion thereof, a second source/drain region at an upper portion thereof, a channel region between the first source/drain region and the second source/drain region and close to peripheral surfaces thereof, and a body region inside the channel region. The semiconductor device may further include a gate stack formed around a periphery of the channel region.

Abstract: Provided is a flexible display device in which an average thickness of a layered body, a touch panel, and a polarizing plate in a bending region is thinner than an average thickness of the layered body, the touch panel, and the polarizing plate in a region other than the bending region.

Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.

Abstract: A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region disposed adjacent to the first gate electrode, a first S/D contact disposed on the first S/D region, a first spacer layer disposed between the first gate electrode and the first S/D region, a first contact layer in contact with the first gate electrode and the first S/D contact, and a first wiring layer integrally formed with the first contact layer. There is no interface between the first contact layer and the first wiring layer in a cross sectional view, and the first contact layer has a smaller area than the first wiring layer in plan view.

Abstract: A 3D semiconductor device, the device including: a first level; a second level; and a third level, where the first level includes single crystal silicon and a plurality of logic circuits, where the plurality of logic circuits includes a first logic circuit and a second logic circuit, where the second level is disposed directly above the first level and includes a first plurality of arrays of memory cells, where the third level is disposed directly above the second level and includes a plurality of on-chip RF circuits, and where a portion of interconnections between the first logic circuit and the second logic circuit includes the plurality of on-chip RF circuits.

Abstract: An apparatus comprising at least one transistor in a first area of a substrate and at least one transistor in a second area, a work function material on a channel region of each of the at least one transistor, wherein an amount of work function material in the first area is different than an amount of work function material in the second area. A method comprising depositing a work function material and a masking material on at least one transistor body in a first area and at least one in a second area; removing less than an entire portion of the masking material so that the portion of the work function material that is exposed in the first area is different than that exposed in the second area; removing the exposed work function material; and forming a gate electrode on each of the at least one transistor bodies.

Abstract: A semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked with each other, and a channel layer passing through the stacked structure, wherein the channel layer is a single layer, the single layer including a first GIDL region, a cell region, and a second GIDL region, and the first GIDL region has a greater thickness than each of the cell region and the second GIDL region.