Patents Examined by Christine T. Tu
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Patent number: 12176919Abstract: Disclosed is a memory device which includes a memory cell array that stores first data and first parity data, an error correction code (ECC) circuit that performs ECC decoding based on the first data and the first parity data and outputs error-corrected data and a decoding status flag, and an input/output circuit that provides the error-corrected data and the decoding status flag to a memory controller. The ECC circuit includes a syndrome generator that generates a syndrome based on the first data and the first parity data, a syndrome decoding circuit that decodes the syndrome to generate an error vector, a correction logic circuit that generates the error-corrected data based on the error vector and the first data, and a fast decoding status flag (DSF) generator that generates the decoding status flag based on the syndrome, without the error vector.Type: GrantFiled: November 16, 2022Date of Patent: December 24, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Rae Kim, Kijun Lee, Myungkyu Lee, Sunghye Cho, Jin-Hoon Jang, Isak Hwang
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Patent number: 12176923Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A channel encoding method in a communication or broadcasting system includes identifying an input bit size, determining a block size (Z), determining an LDPC sequence for LDPC encoding, and performing the LDPC encoding based on the LDPC sequence and the block size.Type: GrantFiled: October 16, 2023Date of Patent: December 24, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Seokki Ahn, Kyungjoong Kim, Seho Myung, Hongsil Jeong, Min Jang
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Patent number: 12165010Abstract: A quantum error correcting code with dynamically generated logical qubits is provided. When viewed as a subsystem code, the code has no logical qubits. Nevertheless, the measurement patterns generate logical qubits, allowing the code to act as a fault-tolerant quantum memory. Each measurement can be a two-qubit Pauli measurement.Type: GrantFiled: May 11, 2022Date of Patent: December 10, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Matthew Hastings, Jeongwan Haah
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Patent number: 12154645Abstract: Pulse detection in microelectronic devices, and related methods, devices, and systems, are described herein. A device may detect and compare a number of pulses of a signal to a timing aperture to determine if any of the number of pulses is unacceptable. The timing aperture, which may be based on a timing signal and/or one or more pulse width thresholds, may define an acceptable pulse versus an unacceptable pulse.Type: GrantFiled: August 1, 2023Date of Patent: November 26, 2024Assignee: Micron Technology, Inc.Inventors: Linh H. Nguyen, Diana C. Majerus, Tyler J. Gomm
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Patent number: 12149259Abstract: A memory device and a system that implements a single symbol correction, double symbol detection (SSC-DSD+) error correction scheme are provided. The scheme is implemented by calculating four syndrome symbols in accordance with a Reed-Solomon (RS) codeword; determining three location bytes in accordance with three corresponding pairs of syndrome symbols in the four syndrome symbols; and generating an output based on a comparison of the three location bytes. The output may include: corrected data responsive to determining that the three location bytes match; an indication of a detected-and-corrected error (DCE) responsive to determining that two of the three location bytes match; or an indication of a detected-yet-uncorrected error (DUE) responsive to determining that none of the three location bytes match. A variant of the SSC-DSD+ decoder may be implemented using a carry-free subtraction operation to perform sanity checking.Type: GrantFiled: September 21, 2022Date of Patent: November 19, 2024Assignee: NVIDIA CorporationInventors: Michael Brendan Sullivan, Nirmal R. Saxena, Stephen William Keckler
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Patent number: 12147874Abstract: A decoder apparatus for decoding syndromes of a quantum error correction code, the syndromes comprising measurement data from a quantum computer, the quantum computer comprising an array of qubits including syndrome qubits and data qubits. The decoder apparatus is configured to: receive syndrome index data representative of: a physical location of each of the array of qubits within the quantum computer; and lattice dimensions of the array of qubits; receive the syndromes of the quantum error correction code from the quantum computer; determine physical co-ordinate positions for each of the array of qubits based on the syndrome index data; decode the syndromes of the quantum error correction code using the determined physical co-ordinate positions.Type: GrantFiled: November 15, 2022Date of Patent: November 19, 2024Assignee: RIVERLANE LTDInventors: Ben Andrew Barber, Kenton Michael Barnes, Kauser Yakub Johar, Luka Skoric
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Patent number: 12143124Abstract: A sending device may obtain a first to-be-encoded vector. The sending device may perform first encoding on the first to-be-encoded vector, to obtain a second to-be-encoded vector. The sending device may encode the second to-be-encoded vector based on a first generator matrix, to obtain an encoded codeword. The first generator matrix may include at least N+1 submatrices a, and N of the submatrices a may be located on a main diagonal of the first generator matrix. The first generator matrix may be a block upper triangular matrix, or the first generator matrix may be a block lower triangular matrix. The submatrix a is a polar kernel matrix with a size of 2m*2m, m is a natural number, and N is a natural number. The sending device may send the encoded codeword.Type: GrantFiled: August 8, 2023Date of Patent: November 12, 2024Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Huazi Zhang, Wen Tong, Jun Wang, Rong Li, Jiajie Tong, Xianbin Wang
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Patent number: 12124330Abstract: A memory system having a memory block and a memory controller in communication with the memory block. The memory controller is configured to: read and decode codewords from the memory block, determine a fail bit count (FBC), a strong correct (SC) rate indicating a percentage of failed bits correctable through log likelihood ratios (LLRs), and a number of spare bytes in the codewords decoded from the memory, predict a soft decoding error based on a fixed FBC, a fixed SC rate, and the number of spare bytes, and determine soft errors in the codewords read from the memory block based on the predicted soft decoding error.Type: GrantFiled: February 28, 2023Date of Patent: October 22, 2024Assignee: SK hynix Inc.Inventors: Fan Zhang, Meysam Asadi
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Patent number: 12125550Abstract: The present technology includes a memory device, a memory system including the memory device, and a test operation of the memory device. The memory device includes a memory block connected to word lines and select lines, a bit line connected to the memory block, a voltage generator configured to generate a test voltage to be applied to a selected line among the word lines and the select lines, a page buffer configured to sense a voltage of the bit line to store and output test data, and a control logic circuit configured to determine whether a first defect exists in the memory block according to the test data.Type: GrantFiled: October 15, 2021Date of Patent: October 22, 2024Assignee: SK hynix Inc.Inventors: Jun Hyuk Lee, Deung Kak Yoo, Dong Jae Jung, Min Kyu Lee
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Patent number: 12111721Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.Type: GrantFiled: October 19, 2023Date of Patent: October 8, 2024Assignee: Apple Inc.Inventors: Marc A. Schaub, Roy G. Moss, Michael Bekerman
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Patent number: 12092687Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.Type: GrantFiled: September 27, 2023Date of Patent: September 17, 2024Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 12073903Abstract: A method may be performed by a leakage monitoring and compensation system configured to estimate and compensate for leakage current in memory unit cells. The method may include identifying a leakage monitoring component associated with a memory unit cell. Further, the method may include sampling multiple leak events during a first exposure window. The method may include storing a first count representing the plurality of leak events sampled during the first exposure window. Each leak event may correspond to a unit of memory leakage. The method may include sampling multiple sensing events during a second exposure window. The method may include detecting a second count representing the sensing events sampled during the second exposure window. The method may include determining a compensation value representing a difference between the first count and the second count.Type: GrantFiled: February 22, 2023Date of Patent: August 27, 2024Assignee: Meta Platforms Technologies, LLPInventors: Umanath Ramachandra Kamath, Ali Mesgarani, Robert Wiser
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Patent number: 12074703Abstract: In a transmission method according to one aspect of the present disclosure, a encoder performs error correction coding on an information bit string to generate a code word. A mapper modulates a first bit string in which the number of bits is the predetermined integral multiple of (X+Y) in the code word using a first scheme, the first scheme being a set of a modulation scheme in which an X-bit bit string is mapped to generate a first complex signal and a modulation scheme in which a Y-bit bit string is mapped to generate a second complex signal, and modulates a second bit string in which the first bit string is removed from the code word using a second scheme different from the first scheme.Type: GrantFiled: May 3, 2023Date of Patent: August 27, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICAInventors: Yutaka Murakami, Tomohiro Kimura, Mikihiro Ouchi
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Patent number: 12073115Abstract: A memory system having a mode indicator, a set of hardware resources, a set of media, and a controller. When the mode indicator identifies a factory mode, a first portion of the hardware resources is reserved for performance of factory functions by the controller and a second portion of the hardware resources is allocated for performance of normal functions. When the mode indicator identifies a user mode, both the first portion and the second portion are allocated for the performance of the normal function. The normal functions are performed by the controller to at least store data in and retrieve data from the set of media in response to requests from a host system.Type: GrantFiled: January 5, 2022Date of Patent: August 27, 2024Assignee: Micron Technology, Inc.Inventor: Alex Frolikov
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Patent number: 12068851Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The present disclosure discloses a method for effective retransmission when HARQ is applied to data encoded with a low density parity check (LDCP) code. A data transmission method of the transmitter may include: initially transmitting data encoded with an LDPC code to a receiver; receiving a negative acknowledgement (NACK) from the receiver; determining retransmission related information for data retransmission; and retransmitting, in response to the NACK, LDPC-encoded data based on the retransmission related information.Type: GrantFiled: June 9, 2023Date of Patent: August 20, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Hongsil Jeong, Kyungjoong Kim, Seho Myung
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Patent number: 12066488Abstract: The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYS (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC) production cycles.Type: GrantFiled: May 16, 2023Date of Patent: August 20, 2024Assignee: Sandisk Technologies, Inc.Inventors: Doron Ganon, Eitan Lerner
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Patent number: 12067255Abstract: Methods, systems, and devices for error detection for programming single level cells of a memory system are described. The memory system may receive a write command for writing data to a block of memory cells and generate a write voltage to write the data to the block of memory cells. The memory system may compare the write voltage to a reference voltage and determine whether the write voltage satisfies a threshold tolerance associated with the reference voltage. The memory system may generate signaling indicating an error associated with writing the data to the block of memory cells, based on determining that the write voltage does not satisfy the threshold tolerance.Type: GrantFiled: July 22, 2022Date of Patent: August 20, 2024Assignee: Micron Technology, Inc.Inventors: Tomer Tzvi Eliash, Yu-Chung Lien
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Patent number: 12055588Abstract: A system and method are disclosed for assembling a testbench for evaluating electronic systems. The method includes assembling large testbenches by using verification features associated with functional components, automatically creating component connections, and statistically checking the testbench prior to generation and simulation. The system includes a computer system that implements the method.Type: GrantFiled: September 29, 2022Date of Patent: August 6, 2024Assignee: ARTERIS, INC.Inventors: Benoit Lafage, Insaf Meliane, Cyril Habert, Gregoire Avot
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Patent number: 12050515Abstract: A computing system comprises a memory and a controller, and the controller is configured to store a first type of data and a second type of data in the memory, to divide the first type of data into a first part and a second part, to generate parity information on the first part and to store the parity information in the memory, and a refresh interval of a region of the memory where the first type of data is stored is larger than a refresh interval of a region of the memory where the second type of data is stored.Type: GrantFiled: March 31, 2023Date of Patent: July 30, 2024Assignee: SK HYNIX INC.Inventors: Jin Ho Baek, Young Pyo Joo
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Patent number: 12045496Abstract: A semiconductor memory device includes; a memory semiconductor die including a volatile memory device configured to perform a normal operation in response to at least one of a command and an address received from a host device, and a test chip vertically stacked with the memory semiconductor die and including a nonvolatile memory device. The test chip is configured in the normal mode to store log information corresponding to at least one of a command and an address received by the semiconductor memory device from the host device, and is further configured in a debugging mode to read the log information from the nonvolatile memory device.Type: GrantFiled: March 28, 2022Date of Patent: July 23, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Boayeong Oh, Kwanghyun Kim