Patents Examined by Christine T. Tu
  • Patent number: 10454625
    Abstract: Methods are disclosed herein for generating and using outer codes based on non-equal length code blocks. In one embodiment, the outer code has a length equal to the length of the longest code block. This can be achieved by padding shorter code blocks such that they are also of equal length to the longest code block. The padding may be a standardized pseudo-random pattern or a standardized repeating pattern. In another embodiment, the outer code has a length shorter than the length of the longest code block. If a code block is received in error it may be recovered by using one or more of: the first outer code block, information bits of other code blocks and the parity bits of the failed code block.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: October 22, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Ming Jia, Jianglei Ma
  • Patent number: 10452472
    Abstract: A dot-product engine (DPE) implemented on an integrated circuit as a crossbar array (CA) includes memory elements comprising a memristor and a transistor in series. A crossbar with N rows, M columns may have N×M memory elements. A vector input for N voltage inputs to the CA and a vector output for M voltage outputs from the CA. An analog-to-digital converter (ADC) and/or a digital-to-analog converter (DAC) may be coupled to each input/output register. Values representing a first matrix may be stored in the CA. Voltages/currents representing a second matrix may be applied to the crossbar. Ohm's Law and Kirchoff's Law may be used to determine values representing the dot-product as read from the crossbar. A portion of the crossbar may perform Error-correcting Codes (ECC) concurrently with calculating the dot-product results. ECC codes may be used to only indicate detection of errors, or for both detection and correction of results.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: October 22, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Catherine Graves, John Paul Strachan, Dejan S. Milojicic, Paolo Faraboschi, Martin Foltin, Sergey Serebryakov
  • Patent number: 10447430
    Abstract: A current frame in a sequence and one or more previous frames in the sequence may be encoded and decoded with forward error correction (FEC). The current frame is encoded at a first bitrate to generate one or more encoded source frames and the one or more previous frames are encoded at an equal or lower second bitrate to generate one or more encoded FEC frames. The encoded source frame(s) and FEC frame(s) are packetized into one or more data packets, which are stored in a memory or transmitted over a data network. The encoded source frame information and previous frame information is unpackaged from the packets and the encoded source frames are decoded. If given source frame of the sequence is missing, one or more encoded FEC frames that correspond to the given source frame are identified from among the data packets and decoded and used to reconstruct the given frame.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: October 15, 2019
    Assignee: Sony Interactive Entertainment LLC
    Inventors: Kim-Huei Low, Kelvin Yong
  • Patent number: 10438678
    Abstract: The present disclosure relates to a structure which includes a memory which is configured to enable zero test time built-in self-test (BIST) at a read/write port while concurrently performing at least one functional read operation at a read port.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Igor Arsovski, Eric D. Hunt-Schroeder, Michael A. Ziegerhofer
  • Patent number: 10437670
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving a write command to write data, the write command being received from a log structure array at a host location. The computer-implemented method also includes: extracting metadata information from the received write command; sequentially adding the extracted metadata information to a metadata buffer; extracting parity information from the received write command; adding the extracted parity information to a parity buffer; sending the data corresponding to the received write command to memory; determining whether an open segment in the memory which corresponds to the write command has been filled; updating the parity buffer with the metadata information included in the metadata buffer in response to determining that the open segment has been filled; and destaging the metadata information from the metadata buffer and parity information from the parity buffer to a physical storage location in the memory.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ioannis Koltsidas, Charles J. Camp, Nikolas Ioannou, Roman A. Pletka, Antonios K. Kourtis, Sasa Tomic, Radu I. Stoica, Christopher Dennett, Andrew D. Walls
  • Patent number: 10430275
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: October 1, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
  • Patent number: 10424388
    Abstract: A memory system includes multiple storage devices that each include a nonvolatile memory device. A client device is configured to collect deterioration information of the nonvolatile memory devices provided from the storage devices. A server device is configured to receive the collected deterioration information and to predict a degree of deterioration of the nonvolatile memory devices in real time by performing machine learning based on the collected deterioration information and initial deterioration information. The client device determines a read level of the nonvolatile memory device based on the degree of deterioration of the nonvolatile memory devices from the server device. The storage device sets the nonvolatile memory device to operate based on the read level determined in the client device.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: September 24, 2019
    Assignee: Samsung ELectronics Co., Ltd.
    Inventors: Hyunkyo Oh, Seungkyung Ro, Heewon Lee, Seongnam Kwon, Oak-Ha Kim, Donggi Lee
  • Patent number: 10417169
    Abstract: The present disclosure provides a link assist capability that may be added to a compiled design that includes a transceiver. The transceiver with the link assist capability may be dynamically reconfigured to operate in a link assist mode, which is a diagnostic and test mode. The link assist mode may interact with a HSSI link partner, or a design software tool, or a user-defined program. The link assist mode may also facilitate remote debugging. One embodiment relates to an apparatus for serial interface link assist. Another embodiment relates to a method of dynamic reconfiguration of transceiver settings. Another embodiment relates to a method of tuning a bidirectional serial link. Other features, aspects and embodiments are also disclosed.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: September 17, 2019
    Assignee: Altera Corporation
    Inventors: Han Hua Leong, Suresh Gordhanlal Andani, Peter Schepers
  • Patent number: 10404280
    Abstract: Techniques are described for joint encoding and decoding of information symbols. In one embodiment, a method for joint encoding includes, in part, obtaining a sequence of information symbols, generating a plurality of cyclic codewords each corresponding to a portion of the sequence of information symbols, jointly encoding the plurality of cyclic codewords to generate at least one combined codeword, and providing the combined codeword to a device. The at least one combined codeword may be generated through Galois Fourier Transform (GFT).
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: September 3, 2019
    Assignee: WESTHOLD CORPORATION
    Inventors: Shu Lin, Khaled Ahmed Sabry Abdel-Ghaffar, Juane Li, Keke Liu
  • Patent number: 10395747
    Abstract: An exemplary system, method, and computer-accessible medium for modifying a memory unit(s) may be provided, which may include, for example, determining a location of a first memory built-in self-test (MBIST) logic(s) in the memory unit(s), removing the first MBIST logic(s) from the memory unit(s), and inserting a second MBIST logic(s) into the memory unit(s) at the location. The second MBIST logic(s) may be based on the first MBIST logic(s). The second MBIST logic(s) may be generated, which may be performed by modifying the first MBIST logic(s). The first MBIST logic(s) may be modified based on a modification(s) to a register transfer level (RTL) list associated with the memory unit(s). A pattern control file or a Test Data Register mapping file may be modified based on the modification to the first MBIST logic(s).
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: August 27, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Steven Lee Gregor, Puneet Arora, Norman Robert Card
  • Patent number: 10387063
    Abstract: A method includes retrieving a read threshold number of integrity check value list (ICVL) encoded data slices of a set of ICVL encoded data slices. The method further includes determining whether an appended ICVL of each ICVL encoded data slice of the read threshold number of ICVL encoded data slices substantially match. When the appended ICVL of one of the ICVL encoded does not substantially match the appended ICVL of other ICVL encoded data slices, the method further includes determining a likely cause for the mismatch. When the likely cause is missing a revision update, the method further includes initiate rebuilding of the encoded data slice portion. The method further includes generating an integrity check value for the rebuilt encoded data slice and updating the integrity check value list. The method further includes appending the updated integrity check value list to the rebuilt encoded data slice.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Niall J. McShane, Jason K. Resch, Ilya Volvovski
  • Patent number: 10388400
    Abstract: Memory systems may include an encoder suitable for arranging data in rows of data blocks as a plurality of codewords, and permuting the data block rows and constructing row parities on the permuted rows, and a decoder suitable for decoding the codewords, and correcting stuck error patterns when decoding of the codewords fails.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventors: Naveen Kumar, Aman Bhatia, Lingqi Zeng
  • Patent number: 10379937
    Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 13, 2019
    Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Om Ranjan, Riccardo Gemelli, Abhishek Gupta
  • Patent number: 10374638
    Abstract: An error correction circuit includes a control unit suitable for receiving a data chunk including a plurality of data blocks, each of the data blocks being included in a corresponding codeword of a first direction and a corresponding codeword of a second direction; and a decoder suitable for performing a decoding operation on a codeword, which is selected by the control unit, in the data chunk, wherein the control unit calculates a first reference value by applying a correction capability value of the first direction to a flag of the first direction, calculates a second reference value by applying a correction capability value of the second direction to a flag of the second direction, selects a priority direction from the first direction and the second direction based on the first reference value and the second reference value, and preferentially selects codewords of the priority direction for decoding operations.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: August 6, 2019
    Assignee: SK hynix Inc.
    Inventor: Jang Seob Kim
  • Patent number: 10361726
    Abstract: A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: July 23, 2019
    Assignee: PANASONIC CORPORATION
    Inventor: Mihail Petrov
  • Patent number: 10361727
    Abstract: Provided is an error correction encoder. The error correction encoder includes input nodes for receiving input words, first encoders for generating first parities by performing a first error correction encoding on each of the input words, an interleaver for generating interleaved words by performing interleaving on the input words, a second encoder for generating a plurality of second parities by performing a second error correction encoding on each of the interleaved words, output nodes for outputting each of the input words, first parity output nodes for outputting the first parities, and second parity output nodes for outputting the second parities.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: July 23, 2019
    Assignee: ELECTRONICS AN TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: In San Jeon, Hyuk Kim
  • Patent number: 10353768
    Abstract: A computer including a processor and a memory and a storage device that is connected to the computer and stores data has an FPGA that acquires data and an operation command from a control unit that controls reading and writing with respect to a non-volatile semiconductor storage unit to perform a data operation. The computer generates and transmits the operation command from an access request that has been received to the storage device. The computer receives execution results for the operation command from the storage device, and when the number of execution results for the operation command reaches a prescribed value, instructs the FPGA to detect a soft error, receives all execution results with respect to the generated operation command, and if there is no soft error, transmits the execution results.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: July 16, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Satoru Watanabe, Yoshiki Kurokawa, Yoshitaka Tsujimoto
  • Patent number: 10353001
    Abstract: A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 16, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Rajesh Maruti Bhagwat, Nitin Satishchandra Kabra, Jay Shah
  • Patent number: 10355711
    Abstract: A data processing method based on a quasi-cyclic LDPC includes: when a size of service data is less than a magnitude of information bit of the quasi-cyclic LDPC, calculating a difference value between the magnitude of the information bit of the quasi-cyclic LDPC and the size of the service data, and filling the service data with the same amount of known data as the difference value (S103); coding the filled service data to obtain redundancy check data corresponding to the service data (S104); and sending the service data and the redundancy check data to a corresponding physical location in the storage unit (S105). It ensures that when a code length of the quasi-cyclic LDPC is constant, the code length ideally adapts to internal space of the storage unit, and the quasi-cyclic LDPC has a relatively high error correction capability, thereby improving reliability and service life of the storage unit.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: July 16, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yanxing Zeng, Jianqiang Shen
  • Patent number: 10348454
    Abstract: An error resilience method comprising: using a computer, creating and storing, in computer memory, one or more FEC filter tables for use by the FEC filter for selectively forwarding a FEC packet; selectively forwarding a request for the FEC packet through a FEC filter based on the FEC table and a dynamic packet loss level at a receiver; limiting a re-transmission request for a particular packet through the FEC filter based on a number of re-transmission requests for the particular packet; and selectively skipping a key frame request based on a number of key frame requests received from a plurality receiver devices, wherein the method is performed by one or more special-purpose computing devices.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: July 9, 2019
    Assignee: Zoom Video Communications, Inc.
    Inventors: Qiyong Liu, Zhaofeng Jia, Kai Jin, Jing Wu, Huipin Zhang