Patents Examined by Christine T. Tu
  • Patent number: 11461172
    Abstract: A storage device includes a nonvolatile memory device, and a controller that reads first data from the nonvolatile memory device. When a number of first errors of the first data is not smaller than a first threshold value, the controller determines whether the first errors include timing errors arising from a variation of signal transmission timings between the nonvolatile memory device and the controller and performs a retraining operation on the signal transmission timings when the first errors include the timing errors.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: October 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chulseung Lee, Soon Suk Hwang, Choongeui Lee
  • Patent number: 11462287
    Abstract: The present disclosure provides a memory test method, a storage medium and a computer device. The memory test method comprises: obtaining a target test pattern that needs to be written into a plurality of chip interfaces, the plurality of chip interfaces being connected to a plurality of physical interfaces in a one-to-one correspondence; determining second information of the chip interfaces corresponding to first information of the physical interfaces, and using the first information and the second information as corresponding connection information; remapping the corresponding connection information to obtain mapped connection information; and determining, according to the target test pattern and the mapped connection information, an initial test pattern that needs to be written into the physical interfaces.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: October 4, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Guangteng Long, Hao He, Dan Lu, Bo Hu
  • Patent number: 11436085
    Abstract: Write operations are performed to write data to user blocks of the memory device and to write, to a first set of purposed blocks, purposed data related to the first data written at the memory device. Whether the first set of purposed blocks satisfy a condition indicating an endurance state of the first set of purposed blocks is determined. Responsive to the first set of purposed blocks satisfies the condition, one or more blocks from a pool of storage area blocks of the memory device are allocated to a second set of purposed blocks.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Sampath K. Ratnam
  • Patent number: 11422184
    Abstract: Systems, apparatuses, and methods for implementing a multi-die clock stop trigger are described. A computing system includes a plurality of semiconductor dies connected together and sharing a global clock stop trigger signal which is pulled high via a resistor tied to a supply voltage. Each semiconductor die has a clock generation unit which generates local clocks for the die. Each clock generation unit monitors for local clock stop triggers, and if one of the local triggers is detected, the clock generation unit stops local clocks on the die and pulls the global clock stop trigger signal low. When the other clock generation units on the other semiconductor dies detect the global clock stop trigger at the logic low level, these clock generation units also stop their local clocks. Captured data is then retrieved from the computing system for further analysis.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: August 23, 2022
    Assignee: Apple Inc.
    Inventors: Charles J. Fleckenstein, Tal Lazmi, Ori Isachar
  • Patent number: 11415622
    Abstract: An automated testing machine with data processing function and an information processing method thereof are introduced. The automated testing machine includes a test head for testing more than one device under testing (DUT), and the test head further includes a test processing unit for providing more than one electrical test signal to the DUTs and conducting a processing and analyzing on more than one electrical feedback data fed back from the DUTs, so as to generate analysis result information. With the test processing unit capable of conducting data processing directly provided in the test head, signals obtained from the DUTs can be directly analyzed and processed to enable increased data processing efficiency, increased convenience in use and reduced costs of the automated test machine and the information processing method thereof.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: August 16, 2022
    Assignee: HEFEI SPIROX TECHNOLOGY CO., LTD.
    Inventor: Hsing-Fu Lin
  • Patent number: 11417412
    Abstract: A cell trace circuit includes a memory cell, a voltage generator and a measuring circuit. The memory cell has a resistor and a memory layer coupled in series to have a top electrode, a middle electrode and a bottom electrode, wherein the resistor and the memory layer are coupled at the middle electrode. The voltage generator provides a test bias to the memory cell ranging from a negative voltage to a positive voltage in a reset path or ranging from the positive voltage to the negative voltage in a set path. The measuring circuit is to determine a current (I) and a voltage (V) crossing the memory layer by the test bias.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: August 16, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Hao Chen, Hsiao-Hua Lu
  • Patent number: 11409595
    Abstract: Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Martin Brox, Peter Mayer, Wolfgang Anton Spirkl, Thomas Hein, Michael Dieter Richter, Timothy M. Hollis, Roy E. Greeff
  • Patent number: 11403169
    Abstract: Systems, methods, and apparatus related to data recovery in memory devices. In one approach, a memory device encodes stored data. The memory device reads a codeword from a storage media and determines that a number errors in the codeword exceeds an error correction capability of the memory device. The errors are due, for example, to one or more stuck bits. In response to this determination, one or more data patterns are written to the storage media at the same address from which the codeword is read. The data patterns are read to identify bit locations of the stuck bits. The identified locations are used to correct bit errors of the read codeword that correspond to the identified locations. The corrected code word is sent to a host device (e.g., which requested data from the memory device using a read command).
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Richard Edward Fackenthal, Sean S. Eilert
  • Patent number: 11398880
    Abstract: This disclosure introduces an advancement to the error indication message to provide detailed information about errors in configurations that are arriving from the Layer 2 to the Layer 1. A method is disclosed, comprising: performing physical layer control (PHY) of a wireless signal at a Layer 1 (L1) software module; performing medium access control (MAC) of the wireless signal at a Layer 2 (L2) software module; providing an application programming interface between the L1 software module and the L2 software module for receiving L1 configuration messages and providing error codes to the L2 software module; receiving a L1 configuration message at a Layer 1 software module; and providing an enhanced error code progressively from a L1 software module to the Layer 2 (L2) software module.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: July 26, 2022
    Assignee: Parallel Wireless, Inc.
    Inventors: Mudassar Khan, Ajay Sharma, Somasekhar Pemmasani
  • Patent number: 11387683
    Abstract: An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Jer Wang, Ching-Nen Peng, Chewn-Pu Jou, Feng Wei Kuo, Hao Chen, Hung-Chih Lin, Huan-Neng Chen, Kuang-Kai Yen, Ming-Chieh Liu, Tsung-Hsiung Lee
  • Patent number: 11386973
    Abstract: The present embodiments provides a memory repair solution finding device and method which find a fault by testing a memory and find a repair solution in parallel and dynamically reconfigure the stored fault information to minimize a repair solution searching time with an optimal repair rate.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: July 12, 2022
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Sungho Kang, Ha Young Lee
  • Patent number: 11379331
    Abstract: An error rate measuring apparatus includes an operation unit that sets one Codeword length and one FEC Symbol length of FEC according to a communication standard of a device under test W, a storage unit that stores symbol string data obtained by receiving and converting a signal from the device under test W, data division means for dividing the stored symbol string data into MSB data and LSB data, a data comparison unit that compares each of the divided MSB data and LSB data with error data to detect each of MSB errors and LSB errors of each one Codeword length, and detects FEC Symbol Errors of each of the MSB data and the LSB data at one FEC Symbol interval, and error counting means for counting the detected MSB errors, LSB errors, and FEC Symbol Errors.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: July 5, 2022
    Assignee: ANRITSU CORPORATION
    Inventor: Hiroyuki Onuma
  • Patent number: 11367506
    Abstract: A data channel aging circuit, a memory, a data channel aging method, and a memory aging method are provided. The data channel aging circuit includes: a memory cell storing a voltage switching signal configured to provide a target voltage state for each of a plurality of data channels in an integrated circuit (IC); a control unit configured to generate a voltage control signal and to send the voltage control signal to each data channel; and a strobe unit configured to switch a conductive state of each data channel based on the voltage switching signal, and to adjust a voltage level of each data channel through the voltage control signal to induce voltage stress aging. The data channel aging circuit improves the reliability of the aging test and the operational stability of the IC products that have went through the aging test.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: June 21, 2022
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Yung-Shiuan Chen
  • Patent number: 11362680
    Abstract: A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: June 14, 2022
    Assignee: PANASONIC HOLDINGS CORPORATION
    Inventor: Mihail Petrov
  • Patent number: 11353506
    Abstract: A safety circuit for the multi-channel processing of an input signal. The safety circuit includes an analog-to-digital conversion device having a first analog input and a second analog input and at least one digital output for processing the input signal. Furthermore, the safety circuit has a test device which is set up to apply a test signal at the first and/or second input of the A/D conversion device in such a way that the test signal superposes the input signal such that the test signal dominates the input signal.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: June 7, 2022
    Assignee: WAGO Verwaltungsgesellschaft mit beschraenkter Haftung
    Inventors: Alexander Buelow, Christian Voss, Torsten Meyer
  • Patent number: 11348659
    Abstract: Devices and techniques for an adjustable voltage drop detection threshold in a memory device are disclosed herein. A voltage drop detection threshold of a memory device is dynamically established. A power loss event is triggered when the supply voltage falls below the voltage drop detection threshold. An error parameter associated with performing multiple memory operations on the memory device is collected. The multiple memory operations are performed while applying a supply voltage at a second supply voltage level of the memory device which is less than a first supply voltage level established as a first operating voltage for the memory device. Determining whether the error parameter is below an allowable error threshold. In response to determining that the error parameter is below the allowable error threshold, the voltage drop detection threshold is established at a voltage level less than the first supply voltage level.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: May 31, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Giuseppe Cariello
  • Patent number: 11347583
    Abstract: A method of correcting errors in a data storage system including a first node, a second node, and shared persistent storage (the first and second nodes being configured to process data storage requests) is provided. The method includes (a) reading cached pages from a first cache disposed within the first node, the cached pages being cached versions of respective persistent pages stored in the shared persistent storage; (b) in response to determining that one of the cached pages is corrupted, requesting that the second node return to the first node a corresponding remote page from a second cache disposed within the second node, the cached page and the remote page each caching a same persistent page of the shared persistent storage; and (c) in response to determining that the remote page received from the second node by the first node is not corrupted, correcting the cached page using the remote page.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: May 31, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Philippe Armangau, Vamsi K. Vankamamidi, Geng Han, Xinlei Xu
  • Patent number: 11349605
    Abstract: A receiver is provided. The receiver includes: a first decoder configured to decode a superposition-coded signal by using a parity check matrix to generate Low Density Parity Check (LDPC) information word bits and first parity bits corresponding to a first layer signal; an encoder configured to encode the LDPC information word bits and the first parity bits to generate second parity bits, or encode the LDPC information word bits to generate the first parity bits and the second parity bits, by using the parity check matrix; and a second decoder configured to decode a signal which is generated by removing the first layer signal, corresponding to the LDPC information word bits, the first parity bits, and the second parity bits, from the superposition-coded signal, to reconstruct bits transmitted through the second layer signal.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: May 31, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Kyung-joong Kim, Hong-sil Jeong
  • Patent number: 11336298
    Abstract: Methods, systems, and devices for operating a memory device are described. An error correction bit flipping scheme may include methods, systems, and devices for performing error correction of one or more bits (e.g., a flip bit) and for efficiently communicating error correction information. The data bits and the flip bit (e.g., an error corrected flip bit) may be directly transmitted (e.g., to a flip decision component). The flip bit may be transmitted to the flip decision component over a dedicated and/or unidirectional line that is different from one or more other lines that carry data bits (e.g., to the flip decision component).
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Jongtae Kwak
  • Patent number: 11327854
    Abstract: Systems, methods, and computer-readable storage media for receiving, at a central server from a first remote data transmission device, first product data for a product at a first location and second product data for the product from a second remote data transmission device at a second location. The respective data is processed sequentially, then determined to contain identical data, such that the system selects a data transmission device as the leader. Then, at a second time, the system receives receiving additional product data from only the selected data transmission device and not from the ignored transmission device, then processes the additional product data as though it had been received from both the first remote data transmission device and the second remote data transmission device.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: May 10, 2022
    Assignee: Walmart Apollo, LLC
    Inventors: Anand Kotriwal, Anirban Bhattacharjee