Patents Examined by Christine T. Tu
  • Patent number: 11016843
    Abstract: Methods, systems, and devices for operating memory cell(s) using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. An output of the error correction circuit may be used to generate syndrome bits, which may be decoded by a syndrome decoder. The syndrome decoder may indicate whether a bit of the data should be corrected by selectively reacting to inputs based on the type of data to be corrected. For example, the syndrome decoder may react to a first set of inputs if the data bit to be corrected is a regular data bit, and react to a second set of inputs if the data bit to be corrected is a redundant data bit.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Kiyoshi Nakai
  • Patent number: 11018805
    Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The present disclosure discloses a method for effective retransmission when HARQ is applied to data encoded with a low density parity check (LDCP) code. A data transmission method of the transmitter may include: initially transmitting data encoded with an LDPC code to a receiver; receiving a negative acknowledgement (NACK) from the receiver; determining retransmission related information for data retransmission; and retransmitting, in response to the NACK, LDPC-encoded data based on the retransmission related information.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: May 25, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hongsil Jeong, Kyungjoong Kim, Sehe Myung
  • Patent number: 11018695
    Abstract: Disclosed are devices, systems and methods improving the convergence of a bit-flipping decoder in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated based on a parity check matrix of a low-density parity-check code and provided to a communication channel prior to reception by the bit-flipping decoder, and performing a single decoding iteration on the received noisy codeword, the single decoding iteration spanning a plurality of stages. In some embodiments, performing a single decoding iteration includes computing a metric corresponding to a single column of the parity check matrix, flipping at least one bit in the single column upon a determination that the metric exceeds a flipping threshold, computing, subsequent to the flipping, a syndrome as a product of the noisy codeword and the parity check matrix, and updating the flipping threshold upon a determination that the syndrome is not zero.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: May 25, 2021
    Assignee: SK hynix Inc.
    Inventors: Fan Zhang, Chenrong Xiong, Haobo Wang, Hongwei Duan, Jiangnan Xia
  • Patent number: 11017135
    Abstract: Embodiments of the present disclosure may include a system for scanning a circuit, the embodiments including flip-flops, latches interleaved between the flip-flops, multiplexers configured to propagate scan data between the flip-flops and latches, and scan logic configured to control the multiplexers to load test data into the flip-flops and latches. A first pair of latches are interleaved between a first pair of flip-flops.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: May 25, 2021
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Athmanathan Vaidyanathan
  • Patent number: 11012102
    Abstract: Systems and methods are disclosed herein for puncturing Polar-encoded bits. In some embodiments, a method of operation of a radio node that utilizes a Polar encoder comprising performing Polar encoding of a plurality of bits to provide a plurality of Polar-encoded code bits and puncturing the plurality of Polar-encoded code bits using a hybrid puncturing scheme to provide a plurality of rate-matched Polar-encoded code bits, wherein the hybrid puncturing scheme uses different puncturing patterns for different code rate regions.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: May 18, 2021
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Dennis Hui, Yufei Blankenship
  • Patent number: 11010304
    Abstract: A method performed by a memory is described. The method includes sensing first bits from a first activated column associated with a first sub-word line structure simultaneously with the sensing of second bits from a second activated column associated with a second sub-word line structure. The method also includes providing the first bits at a same first bit location within different read words of a burst read sequence and providing the second bits at a same second bit location within the different read words of the burst read sequence.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Uksong Kang, Kjersten E. Criss, Rajat Agarwal, John B. Halbert
  • Patent number: 11005458
    Abstract: A semiconductor integrated circuit comprises a scan flipflop comprising a scan input and a data input; and scan control circuitry. The scan control circuitry is configured to control the scan flipflop to capture a value inputted to the scan input in a capture mode.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: May 11, 2021
    Assignee: Synaptics Incorporated
    Inventor: Takahisa Nakako
  • Patent number: 11003375
    Abstract: Methods, systems, and devices for code word formats and structures are described. A code word format and structure may include various fields that facilitate a reliable transaction of user data during an access operation associated with a memory medium. For example, the bit fields may include information directed to an error control operation for a port manager to perform on a code word configured in accordance with the code word format and structure. Additionally, the code word format and structure may be configured for low latency operation and reliable transaction of the user data during the access operation. For example, the port manager may receive a first portion of the code word and parse the first portion of the code word concurrently with receiving an additional portion of the code word.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Joseph Thomas Pawlowski
  • Patent number: 10996269
    Abstract: Techniques for implementing a self-test procedure of an integrated circuit are provided, where the self-test procedure comprises testing for an electrical connection between first and second input-output pads of the integrated circuit. A control device is capable of adapting a functional configuration of usage of the first and second input-output pads in dependence on presence of the electrical connection. A corresponding integrated circuit, printed circuit and method are also provided. These techniques allow the integrated circuit to be used in a variety of contexts, without requiring physical customisation of the integrated circuit to adapt it to its usage context, in particular where connections from the context to the pads of the integrated circuit may be made to individual pads in some contexts or may span more than one pad in other contexts.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: May 4, 2021
    Assignee: ARM Limited
    Inventors: James Edward Myers, Parameshwarappa Anand Kumar Savanth
  • Patent number: 10998036
    Abstract: A memory controller includes a clock signal generator generating a clock signal; a first data receiving circuit receiving a serial signal having a plurality of logic values from a memory, using the serial signal to compensate for a phase error of the clock signal, and generating a phase-compensated clock signal as a first clock signal; and at least one second data receiving circuit receiving data from the memory, receiving the first clock signal from the first data receiving circuit, and using the first clock signal to recover the data.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 4, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kihwan Seong, Soomin Lee, Sanghune Park
  • Patent number: 10990298
    Abstract: A computer-implemented method according to one embodiment includes sending a data request from a host to a storage drive, where the data request includes quality of service (QoS) information, receiving, in response to the data request, a response from the storage drive at the host, and performing one or more actions at the host, based on the response.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: April 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Greco, Edwin R. Childers, Simeon Furrer, Roy D. Cideciyan, Mark A. Lantz
  • Patent number: 10985781
    Abstract: An error correction circuit includes a control unit suitable for receiving a data chunk including a plurality of data blocks, each of the data blocks being included in a corresponding codeword of a first direction and a corresponding codeword of a second direction; and a decoder suitable for performing a decoding operation on a codeword, which is selected by the control unit, in the data chunk, wherein the control unit calculates a first reference value by applying a correction capability value of the first direction to a flag of the first direction, calculates a second reference value by applying a correction capability value of the second direction to a flag of the second direction, selects a priority direction from the first direction and the second direction based on the first reference value and the second reference value, and preferentially selects codewords of the priority direction for decoding operations.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: April 20, 2021
    Assignee: SK hynix Inc.
    Inventor: Jang Seob Kim
  • Patent number: 10979175
    Abstract: Encoded information corresponding to the encoded source frames and the one or more previous frames is unpackaged from each data packet. Each data packet in the plurality contains encoded information corresponding to a source frame in a sequence encoded at a first bitrate and one or more previous frames in the sequence encoded as forward error correction (FEC) frames at a second bitrate that is equal to or lower than the first bitrate. The encoded source frames are decoded to generate corresponding decoded source frames. Encoded FEC frames that correspond to a given source frame for which encoded information is missing are decoded to generate corresponding decoded FEC frames. A reconstructed frame is generated corresponding to the given source frame using the one or more decoded FEC frames. The decoded source to frames and the reconstructed missing frame are stored in a memory and/or presented with a display.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: April 13, 2021
    Assignee: SONY INTERACTIVE ENTERTAINMENT LLC
    Inventors: Kim-Huei Low, Kelvin Yong
  • Patent number: 10970164
    Abstract: A storage device includes a nonvolatile memory device, and a controller that reads first data from the nonvolatile memory device. When a number of first errors of the first data is not smaller than a first threshold value, the controller determines whether the first errors include timing errors arising from a variation of signal transmission timings between the nonvolatile memory device and the controller and performs a retraining operation on the signal transmission timings when the first errors include the timing errors.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: April 6, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chulseung Lee, Soon Suk Hwang, Choongeui Lee
  • Patent number: 10972217
    Abstract: Methods, systems, and devices for wireless communications are described. Efficient low-density parity-check (LDPC) scheduling of layered decoding may include receiving a message encoded as an LDPC code that includes a number of check nodes and a number of bit nodes, applying a first number of decoding iterations to decoding the message, applying a second number of decoding iterations to decoding the message after the first number of decoding iterations are applied, and decoding the message through completion of both the first number of decoding iterations and the second number of decoding iterations. In some cases, only a portion of the number of check nodes is decoded during each of the first number of decoding iterations and all of the number of check nodes are decoded during each of the second number of decoding iterations.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: April 6, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Ying Wang, Jing Jiang, Peter John Black, Joseph Binamira Soriaga, Gabi Sarkis
  • Patent number: 10972216
    Abstract: Disclosed in an embodiment of the present invention are a polar code encoding method and device, the method comprising: utilizing a common information bit set to represent each of m polar code blocks, the polar codes in each polar code block having the same code length and different code rates, and m being greater than or equal to 2; according to the common information bit set corresponding to the polar code block, acquiring an information bit set corresponding to each polar code in the polar code block; and according to the information bit set corresponding to each polar code in the polar code block, conducting polar code encoding on information to be encoded, thus reducing polar code representation overhead, and solving the problem in the prior art of excessively high polar code representation overhead.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: April 6, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Hui Shen, Bin Li, Jun Chen
  • Patent number: 10956264
    Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: March 23, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Masamichi Fujiwara, Kazumasa Yamamoto, Naoaki Kokubun, Tatsuro Hitomi, Hironori Uchikawa
  • Patent number: 10951232
    Abstract: Methods, systems, and devices for operating a memory device are described. An error correction bit flipping scheme may include methods, systems, and devices for performing error correction of one or more bits (e.g., a flip bit) and for efficiently communicating error correction information. The data bits and the flip bit (e.g., an error corrected flip bit) may be directly transmitted (e.g., to a flip decision component). The flip bit may be transmitted to the flip decision component over a dedicated and/or unidirectional line that is different from one or more other lines that carry data bits (e.g., to the flip decision component).
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Jongtae Kwak
  • Patent number: 10949293
    Abstract: Methods, systems, and devices for erroneous bit discovery in a memory system are described. A controller or memory controller, for example, may read a code word from a memory medium. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) of the memory medium. Each MSR may include a portion of memory cells of the memory medium and be associated with a counter to count a quantity of erroneous bits in each MSR. When the controller identifies a quantity of erroneous bits in the code word using an error control operation, the controller may update values of counters associated with respective MSRs that correspond to the quantity of erroneous bits to count erroneous bit counts for each MSR. In some cases, the controller may perform operations described herein as part of a background operation.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: March 16, 2021
    Assignee: Micron Technology Inc.
    Inventor: Joseph Thomas Pawlowski
  • Patent number: 10942808
    Abstract: Embodiments for adaptive placement of parity information within Redundant Array of Independent Disks (RAID) stripes in a computer storage environment. A RAID controller periodically collects a physical capacity usage of each of a plurality of storage devices within the RAID. The RAID controller determines a placement of data and the parity information within at least one of the plurality of storage devices according to at least one of a plurality of factors associated with the physical capacity usage. The RAID controller writes the data and the parity information to the at least one of the plurality of storage devices according to the determined placement.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: March 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roman Alexander Pletka, Sasa Tomic, Timothy Fisher, Nikolaos Papandreou, Nikolas Ioannou, Aaron Fry