Abstract: The present disclosure discloses a memory device including a controller for bit reordering. The controller receives an input bit sequence including a plurality of bits with a first bit order. The controller identifies a physical location of a non-volatile memory element in the memory device and determines a correspondence between the first bit order and a second bit order based on the physical location. The controller generates an output bit sequence including the plurality of bits with the second bit order based on the correspondence.

Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

Abstract: An optical switch control method and an apparatus are disclosed, to reduce impact on access performance by time overheads of optical link switching. The method includes: receiving an optical link establishment request sent by a computation node; determining whether the first optical link that needs to be established conflicts with the existing optical link; and if the first optical link that needs to be established conflicts with the existing optical link, determining whether to allow establishment of the first optical link, and establishing the first optical link if the establishment of the first optical link is allowed; or establishing the first optical link if the first optical link that needs to be established does not conflict with the existing optical link.

Abstract: The disclosure is related to an interface card module which is configured to be inserted into a PCIe slot on a motherboard and to be inserted with a cable electrically connected to a function chip. The interface card module includes an adapter card and a function card. The adapter card includes a mainboard, a first PCIe male connector, a socket and at least one cable connector. The first PCIe male connector, the socket and the cable connector are respectively disposed on different sides of the mainboard. The first PCIe male connector is configured to be inserted into the PCIe slot on the motherboard. The at least one cable connector is inserted with the cable. The function card has a second PCIe male connector configured to be inserted into the socket of the adapter card. In addition, the disclosure is also related to an adapter card.

Abstract: Disclosed herein are techniques for maintaining a secure execution environment on a server. In one embodiment, the server includes a bus manager circuit. The bus manager circuit comprises a first bus interface configured to be coupled with a first hardware device of the server, and a second bus interface configured to be coupled with a second hardware device of the sever. The bus manager further includes a control module. Under a first mode of operation, the control module is configured to receive an access request from the first hardware device to access the second hardware device, and responsive to determining not to grant the access request based on a pre-determined access policy, and block at least some of data bits corresponding to the access request from the second bus interface. The control module may also process the access request in a different manner under other modes of operations.

Abstract: A physical layer integrated circuit (PHY), including an accessory charger adapter (ACA) bridge circuit to communicate with an ACA via a universal serial bus (USB) cable having at least an ID pin and a VBUS pin. The PHY is also to communicate with an ACA-agnostic USB controller configured to act as an A-device or as a B-device. The ACA comprises a USB accessory port. The ACA bridge circuit comprises detection and control logic configured to detect, based on a resistance sensed on the ID pin, that a B-device is connected to the USB accessory port of the ACA and, as a result of such a detection, generate a signal to the USB controller that causes the USB controller to act as an A-device and ignore a VBUS drive signal from the USB controller that, if not ignored, would cause the PHY to drive the VBUS pin.

Abstract: When a first interface board receives from an Ethernet switch chip a first Ethernet data packet, once a destination board of the data packet is determined as second interface board logical device of the first interface board encapsulates the data packet into a PCI-E packet that takes a PCI-E memory space address of a board memory in the second interface board as a destination address, so as to enable a PCI-E Endpoint to forward the first PCI-E packet to a forwarding board of a network device; when the first interface board obtains from a board memory a second PCI-E packet coming from a third interface board, logical device of the first interface board parses out a Ethernet data packet from the second PCI-E packet, and transmits the data packet to the Ethernet switch chip, the third interface board and second interface board being the same or not same.

Abstract: A memory controller accessing a memory including a plurality of blocks is provided. The memory controller includes a storage circuit and a control circuit. The storage circuit stores a refresh value and a data table. The data table has a plurality of bits. Each bit indicates whether a corresponding block has valid data. The control circuit selects a specific block according to the refresh value and determines whether the specific block stores valid data according to the data table. When the specific block stores valid data, the control circuit accesses the memory after a first waiting time. When the specific block does not store any data or stores invalid data, the control circuit accesses the memory after a second waiting time. The second waiting time is shorter than the first waiting time.

Abstract: The invention provides a system and method of provisioning a resource to an electronic device. The method comprises the steps of: (a) maintaining a library of resources at a remote server from the device; (b) after a triggering event, providing a data transmission to the device, the data transmission containing access information for the library that can be extracted by the device and used to access the library; and (c) after a selection event initiated on the device for a specific resource from the library, providing a second data transmission to the device, the second data transmission containing a copy of the specific resource. The system provides a server, a resource, a device and a communication link incorporating the method.

Abstract: A connection confirmation system includes a connection detection apparatus and an information processing apparatus communicable with each other. The connection detection apparatus acquires a setting relating to a connection mode of a device to be connected to a sound processing apparatus, detects a connection mode of a device actually connected to the sound processing apparatus, and determines a difference between the detected actual connection mode and the connection mode indicated by the acquired setting.

Abstract: A system and approach for addressing modules on a platform bus that may incorporate a master module and one or more slave modules. The platform bus may run through sub-base connectors that interlock modules together on a rail. Addressing of the modules may occur automatically and dynamically in that the master module may have a first address by default, and a first slave module adjoining the master module may be assigned a second address. A second slave module adjoining the first slave module, if there is one, may be assigned a third address. Each of the other slave modules, adjoining a preceding slave module assigned an address, may be assigned a next address after an address assigned to a preceding slave module. Addresses may be assigned in a numerical order to each module based on a physical position of the respective module on a rail.

Abstract: A data storage system includes a bridging device. The bridging device is configured to receive, from a host through a network, a host data block size. A sub-block size is determined based on the host data block size. One or more storage devices are configured to include a plurality of storage sub-blocks each having the sub-block size. A first write command to write first host data including a first number of host data blocks to the one or more storage devices is received. The bridging device compresses the first host data to generate first compressed data, and write the first compressed data to a second number of storage sub-blocks of the one or more storage devices.

Abstract: A method performed at the electronic device for identifying an electronic device and peripheral apparatuses is provided. The method acquires image data regarding emitters of the peripheral apparatuses, determines emitting colors emitted from the emitters based on the acquired image data, and acquires identification information of the peripheral apparatuses mapped with the emitting colors.

Abstract: A configurable sponge function engine. The configurable engine includes a register having bitrate and capacity sections, each having a variable size, where a sum of the bitrate and capacity sizes is fixed. A controller generates a bitrate size indication. A configurable message processor receives an input message from an input bus, receives the size indication, fragments the input message into fragmented blocks of a size specified by the size indication, and converts the blocks to a bus width of the bitrate and capacity sizes. An iterative calculator receives the blocks, performs iterative processing operations on the blocks, and stores a result of each operation in the register overwriting a previous register value. An output adaptor receives a value stored in the register after the block corresponding to the end of the input message is processed and outputs the register value converted to have an output bus width.

Abstract: Power supply of ECUs connected to a communication network is optimally controlled so that power consumption is reduced. A transceiver/receiver converts a message of a differential signal received via a CAN bus into a digital signal. A select circuit determines whether the converted message is in a CAN format or a UART format. If it is in the UART format, the select circuit outputs a message to the UART circuit. A UART circuit determines whether the message matches a UART format. If matched, an ID determination circuit determines whether the input message is specifying a CAN ID of its own ECU. If it is the CAN ID of the ECU, the ID determination circuit outputs an enable signal to turn on a regulator and supply power to an MCU and an actuator.

Abstract: An asynchronous interface according to the disclosure includes: a transmission circuit that transmits, with data of W bits as one word, the data on the one-word basis, and transmits an REQ signal whose value differs by one bit per transmission of the data of one word; a reception circuit including a reception buffer having a reception buffer word count of n (n is an integer of 4 or more), in which the reception circuit receives the data on the one-word basis, and transmits an ACK signal whose value differs by one bit per reception of the data of one word; a data signal line that has a bit width of W, and transfers the data from the transmission circuit to the reception circuit; an REQ signal line that has a bit width of log2 (n) or more, and transfers the REQ signal from the transmission circuit to the reception circuit; and an ACK signal line that has a bit width of log2(n) or more, and transfers the ACK signal from the reception circuit to the transmission circuit.

Abstract: A modular control apparatus, having a head module, and at least one supply module and peripheral module arranged on the head module and having a bus structure. The supply module and the peripheral module have a base module part, an electronic module part and a connection module part. The base module parts are arranged next to one another and provide the bus structure that electrically couples the head module, the supply module and the peripheral module to one another. The supply module additionally comprises an electrical line that runs from the connection module part through the electronic module part to the base module part and connects the supply connection of the supply module to the bus structure. An overload identification unit is arranged at the electrical line and determines a parameter of the electrical line and produces a warning signal if the parameter exceeds a threshold value.

Abstract: A method and device for processing an input/output (I/O) request in a network file system (NFS) includes sending, by a NFS server, a request for parsing the unidentifiable NFS FH to a centralized controller when a NFS file handle (NFS FH) in an I/O request cannot be identified, receiving, by the NFS server, a file identifier that corresponds to the unidentifiable NFS FH from the centralized controller according to the parsing request, where the file identifier is determined according to a pre-stored correspondence between NFS FHs and file identifiers, and processing, by the NFS server, the I/O request according to the file identifier.

Abstract: Example implementations relate to a switch resource manager for a network switching device. In an example, a network switching device includes a packet switching device and an operating system kernel. The operating system kernel includes a driver for the packet switching device. The network switching device also includes a switch resource manager including a library of commands for the packet switching device. The switch resource manager can send commands to the packet switching device via the driver. The operating system kernel can load a network operating system instance into user space of the network switching device.

Abstract: A method, non-transitory computer readable medium and storage controller computing device that retrieves an anchor record from a shared memory of a peer storage controller using a direct memory access (DMA) provider device. The anchor record includes an indication of a message first in first out (FIFO) memory region of the peer storage controller. A work request is obtained from a queue. The work request is inserted into the queue by a client application using an application programming interface (API). One of a plurality of types of the work request is determined. The DMA provider device is instructed based on the determined type of the work request and, when the determining indicates that the work request is a request to send a network message, use the message FIFO memory region of the peer storage controller computing device.