Abstract: Technologies for flexible I/O protocol acceleration include a computing device having a root complex, a smart endpoint coupled to the root complex, and an offload complex coupled to the smart endpoint. The smart endpoint receives an I/O transaction that originates from the root complex and parses the I/O transaction based on an I/O protocol and identifies an I/O command. The smart endpoint may parse the I/O transaction based on endpoint firmware that may be programmed by the computing device. The smart endpoint accelerates the I/O command and provides a smart context to the offload complex. The smart endpoint may copy the I/O command to memory of the smart endpoint or the offload complex. The smart endpoint may identify protocol data based on the I/O command and copy the protocol data to the memory of the smart endpoint or the offload complex. Other embodiments are described and claimed.

Abstract: Enhancements for managing quality of service in a multi-host Peripheral Component Interconnect Express (PCIe) switching environment involve a host system configured to maintain quality of service statistics corresponding to data interactions with a PCIe storage device available via a PCIe switch. The host system may further receive secondary quality of service statistics for one or more other host systems communicatively coupled to the PCIe device via the PCIe switch, and determine a maximum queue depth for the host system based on the quality of service statistics and the second quality of service statistics to maintain a quality of service for at least the host system.

Abstract: A bus control circuit comprises an arbitration circuit which receives a bus-transfer request from each of a plurality of bus masters and outputs an arbitration result signal, in accordance with a priority order, to one of the bus masters, and a plurality of bus switches, wherein each bus switch comprises a selection circuit which includes a plurality of input terminals for receiving a plurality of bus transfer signals and an output terminal for transmitting one bus transfer signal to a downstream side, and a control circuit which receives the arbitration result signal from the arbitration circuit and controls the selection circuit based on the arbitration result signal to select one of the plurality of input terminals, and a slave module is connected to the output terminal of the selection circuit in the bus switch located at a most downstream position.

Abstract: The present disclosure may provide a method for loading a driver during a terminal starting up and a terminal device. The terminal includes at least one component having a driver to be loaded during starting up. The method includes: receiving a startup instruction; reading a component list; determining whether the component list comprises a driver related to a component; and if the component list includes the driver related to the component, loading the related driver. By such means, the present disclosure increases a startup speed and improves user experience.

Abstract: A method of remote control is provided. A user interface of a controlling end inputs switching control signal. A first port of the controlling end transfers the control signal to a USB connector of an image capture unit. After being handled by a processor, the control signal is transferred to at least one controlled end through a second port by a USB-C connector of the image capture unit. Thus, the controlling end connects to and communicates with the controlled end, where the controlling end operates the controlled end with the user interface. Hence, the controlling end operates the controlled end with the connection of the image capture unit without switches and network. A simple method is obtained with cost effectively reduced.

Abstract: An integrated circuit system includes a host device; and a memory module suitable for communicating with the host device according to a first protocol, the memory module comprising: at least one memory device suitable for storing data or outputting stored data, and executing communication according to a second protocol; and a protocol converter suitable for transferring information among the host device and the at least one memory device, wherein information to be inputted to the at least one memory device is transferred by being converted according to the second protocol and information to be outputted from the at least one memory device is transferred by being converted according to the first protocol.

Abstract: A bandwidth estimation method is disclosed for measuring memory bandwidth consumption or the bandwidth consumption of any I/O bus in real time on a computer system without the use of hardware counters. The bandwidth estimation method, designed to run in isolation on a core in a multi-core computer system, generates temporally sequential and spatially random accesses to a bus such as the memory bus and reports the average latency per request. Using a pre-calculated latency-bandwidth relationship, the bandwidth on the bus is calculated and reported at runtime for every latency sample. The bandwidth estimation method allows profiling processors and computer systems in real time to determine the amount of memory or I/O traffic they are using while running a workload.

Abstract: In one embodiment, a host controller includes: a first credit tracker comprising at least one credit counter to maintain credit information for a first device; and a first credit handler to send a command code having a first predetermined value to indicate a credit request to request credit information from the first device, where the first credit tracker is to update the at least one credit counter based on receipt of an in-band interrupt from the first device having the credit information. Other embodiments are described and claimed.

Abstract: Processing by an information processing system is speeded up. A first semiconductor integrated circuit designates a first address of a memory connected to a second semiconductor integrated circuit that is a data transmission destination, based on first memory map information in which addresses of memories respectively used by the semiconductor integrated circuits are defined, converts the first address to a second address of the memory defined in second memory map information referred to by the data transmission destination, and outputs the second address and transmission data by using a PCIe interface. A switch transfers the second address and the transmission data to the data transmission destination by using PCIe interfaces. The data transmission destination receives the second address and the transmission data by using a PCIe interface and writes the transmission data into the reception buffer region of the memory corresponding to the second address.

Abstract: In one embodiment, a system on chip includes a first endpoint to issue a non-posted memory write transaction to a memory and a Peripheral Component Interconnect (PCI)-based fabric including control logic to direct the non-posted memory write transaction to the memory, receive a completion for the non-posted memory write transaction from the memory and route the completion to the first endpoint. Other embodiments are described and claimed.

Abstract: The present disclosure relates to a bus device and a corresponding bus system. Furthermore, the present disclosure relates to a corresponding method of operating a bus device. In accordance with a first aspect of the present disclosure there is provided a bus device comprising a bus protocol controller with a transmit data output and a bus transceiver with a transmit data input coupled to the transmit data output of the bus protocol controller, wherein the bus protocol controller is configured to provide a serial bit stream designated for transmission through a bus via the transmit data output of the bus controller and via the transmit data input to the bus transceiver and to provide a switching signal within the serial bit stream, and wherein the bus transceiver is configured to switch between different operating modes in response to the switching signal.

Abstract: A method of detecting possible living body contact at an electrical contact surface, wherein the living body has a detectable characteristic initial impedance and a corresponding characteristic time constant defined by the initial impedance upon touching the electrical contact surface when the electrical contact surface is at a touching voltage, wherein the method comprises sending a non-hazardous probing signal to the contact surface, wherein the probing signal comprises one probing pulse or a plurality of probing pulses forming a probing pulse train, and the probing pulse has a base voltage level and a probing voltage level which is above the base voltage level and equal to the touching voltage or a probing voltage level which is below the base voltage level and equal to the touching voltage; detecting an electrical response from the contact surface in response to the electrical probing signal, wherein the electrical response comprises electrical response signals; and determining from the electrical respons

Abstract: Embodiments of the present disclosure may be related to an electronic device that includes a root complex; and a processor coupled with the root complex. The root complex may identify a first direct memory access (DMA) transaction and a second DMA transaction respectively related to a first task and a second task of a device communicatively coupled with the root complex through an input/output (I/O) fabric. The root complex may further cache a first memory translation related to the first DMA transaction in a first micro translation lookaside buffer (uTLB) of the root complex. The root complex may further cache a second memory translation related to the second DMA transaction in a second uTLB of the root complex. Other embodiments may be described and/or claimed.

Abstract: Disclosed herein are techniques for maintaining a secure execution environment on a server. In one embodiment, the server includes a bus manager circuit. The bus manager circuit comprises a first bus interface configured to be coupled with a first hardware device of the server, and a second bus interface configured to be coupled with a second hardware device of the sever. The bus manager further includes a control module. Under a first mode of operation, the control module is configured to receive an access request from the first hardware device to access the second hardware device, and responsive to determining not to grant the access request based on a pre-determined access policy, and block at least some of data bits corresponding to the access request from the second bus interface. The control module may also process the access request in a different manner under other modes of operations.

Abstract: A modular UPS system includes at least two power devices, a controlling device, and a serial bus. The power device is configured to receive control status information transmitted by the controlling device. The power device is configured to transmit a status signal data frame to the serial bus according to the control status information when determining that a current period is a first preset period, where the status signal data frame includes an identifier field, the identifier field includes a status signal data area, and the status signal data area is used to store a data value of a status signal. The serial bus is configured to receive status signal data frames transmitted by the at least two power devices, and transmit status signal data frames with a same value in status signal data areas to the controlling device in parallel.

Abstract: A pluggable module identification system, including: a detection device and a plurality of pluggable modules with surfaces thereof being conductors, where the detection device includes a receptor slot, a grounding assembly is provided on an inner side surface of the receptor slot at a location close to an insertion opening of the receptor slot, a detection assembly is provided on the inner side surface of the receptor slot at location close to a bottom of the receptor slot, the grounding assembly is grounded, and the detection assembly is connected to a main board.

Abstract: Presented herein are methodologies for scaling device management over a sideband management bus (SMBUS). A method includes receiving, at a first expander card, from baseboard management controller (BMC), a management message, addressed to a second expander card that is in communication with the first expander card, forwarding the management message to the second expander card, and sending, by the second expander card, the management message, via the sideband management bus, to a device in communication with the second expander card. The device may be, e.g., a Non-Volatile Memory Express (NVMe) drive. Expander cards can be deployed in a daisy chain, providing scalability. Each expander card can also send commands to connected devices in parallel.

Abstract: The present invention relates to a main electronic device for communicating within a network comprising an interface for enabling communication within the network and a controller for sending polling messages via the network to logical addresses via said interface in order to request information from at least one further electronic device. The present invention further relates to a method for operating a main electronic device for communicating within a network.

Abstract: A first end point and a second end point are provided. The first end point receives data from a root complex of a first platform among platforms, each serving as a computer that executes arithmetic processing. The second end point transfers the data to a root complex of a second platform among the platforms, the data to be transferred being received at the second end point by tunneling from the first end point.

Abstract: A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller hub, which includes a main communication chipset. The plurality of Sibling boards is coupled to the hub board by the common bus. Each of the Sibling boards includes a memory and at least one CPU. The memory is operative to host a Sibling operating system. The CPU is coupled to the memory. The Southbridge type chipset which resides in the hub board is shared amongst the plurality of Sibling boards. At least one of the plurality of Sibling boards functions as a master processing unit of the system. Sibling boards offer processing flexibility through the means of how they are configured in the system.