Patents Examined by Christopher Bartels
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Patent number: 10101734Abstract: An Enterprise Resource Planning (ERP) gateway is provided for routing of ERP messages to Manufacturing Execution System (MES) applications. The gateway can receive a message from an ERP system via a manufacturing services bus specifying a business objective requiring action at a control level of an enterprise. The received message can be routed to a selected MES application capable of carrying out the business objective based on attributes within the message. Message routing can be based on location tags contained in the message. The message can also be routed to a selected subset of MES applications based on an analysis of respective capabilities and control contexts of the MES applications. Messages can be routed between the ERP system and the MES applications via the manufacturing services bus, which can manage protocol transformations for a heterogeneous set of applications.Type: GrantFiled: February 10, 2017Date of Patent: October 16, 2018Assignee: Rockwell Automation Technologies, Inc.Inventors: David Cooper, Kevin Chao, Keith Chambers, Richard Sze, Crisler Moor, Brandon E. Henning, Suryanarayana Murthy Bobba
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Patent number: 10055298Abstract: A method, article of manufacture, and apparatus for accessing data during data recovery. In some embodiments, this includes sending an I/O request from an application to an object, wherein the object is being recovered, establishing an I/O intercept, intercepting the application's I/O request with the I/O intercept, and redirecting the I/O request based on the status of the object's sub-objects.Type: GrantFiled: May 25, 2017Date of Patent: August 21, 2018Assignee: EMC IP Holding Company LLCInventors: Michael John Dutch, Christopher Hercules Claudatos, Mandavilli Navneeth Rao
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Patent number: 10042413Abstract: Multiple bus generator and load control monitoring system for electrical switchgear is provided. In one arrangement, the system is designed to allow for the increased functionality of a single bus system to be used in multiple bus systems wherein the multiple buses are separated or combined together to act as a single bus. Each bus within the multiple bus system may be able to utilize increased functionality of a typical generator bus and load control system independently if separated. Separate bus structures may be separated by some sort of isolation device, for example: a circuit breaker, transfer switch, or the like. If the bus segments are connected together via isolation devices, then the combination of the overall connected bus structure will act as a single entity, while containing enhanced automation functions.Type: GrantFiled: June 19, 2015Date of Patent: August 7, 2018Assignee: ASCO POWER TECHNOLOGIES, L.P.Inventor: William J. Dustman
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Patent number: 10037301Abstract: Various example implementations are directed to circuits and methods for communicating between disparate processor circuits. According to an example implementation, a circuit arrangement includes a plurality of processor circuits and an inter-processor communication circuit. The inter-processor communication circuit is configured to provide, for each pair of the processor circuits, a respective communication channel between the pair of processor circuits. The inter-processor communication circuit includes a plurality of buffers including a respective first buffer and a respective second buffer for each communication channel. An access control circuit included in the inter-processor communication circuit is configured to restrict write access to the respective first buffer to the first processor circuit and restrict write access to the respective second buffer to the second processor circuit.Type: GrantFiled: March 4, 2015Date of Patent: July 31, 2018Assignee: XILINX, INC.Inventors: Sagheer Ahmad, Soren Brinkmann
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Patent number: 10025734Abstract: A method is used in managing input/output (I/O) operations based on application awareness. An I/O operation directed to storage is received. The storage is provisioned in accordance with an application and the provisioning includes selecting one or more default options in accordance with best practices of the application. Based on the provisioning in accordance with the application, an evaluation is performed of the acceptability of an I/O operation.Type: GrantFiled: June 29, 2010Date of Patent: July 17, 2018Assignee: EMC IP Holding Company LLCInventors: Paul J. Caruso, Stephen J. Todd
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Patent number: 10001977Abstract: A system and method identifies a set of operations or tasks, such as functions, of a programming system or technical computing environment based on a selection of input data. The technical computing environment may have a plurality of operations that may be called and executed. The operations may operate on one or more input arguments that may need to satisfy certain constraints. Upon selection of input data, a matching engine may classify the input data, and compare the classifications of the input data to the input argument constraints of a plurality of operations. The matching engine may identify those operations whose input argument constraints are satisfied by the selected input data, as well as those operations whose input argument constraints are not satisfied by the selected input data. The matching and non-matching operations may be provided to an action unit, which may be configured to perform some task or action with regard to some or all of the operations.Type: GrantFiled: June 5, 2009Date of Patent: June 19, 2018Assignee: The MathWorks, Inc.Inventors: James Gareth Owen, Claudia Gaudagnini Wey
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Patent number: 10002080Abstract: A memory system implements a plurality of virtual address modification policies and optionally a plurality of cache eviction policies. Virtual addresses are optionally, selectively, and/or conditionally modified by the memory system in accordance with a plurality of virtual address modification policies. The virtual address modification policies include no modification, modification according to two-dimensional Morton ordering, and modification according to three-dimensional Morton ordering. For example, in response to a reference to a particular virtual address, the particular virtual address is modified according to two-dimensional Morton ordering so that at least two elements in a same column and distinct respective rows of a two-dimensional data structure are loaded into a same cache line and/or are referenced via a same page table entry.Type: GrantFiled: December 30, 2013Date of Patent: June 19, 2018Inventor: Michael Henry Kass
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Patent number: 9910816Abstract: A method of communicating data over a Peripheral Component Interconnect Express (PCIe) Non-Transparent Bridge (NTB) comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message indicates an intent to transfer data to the remote processor, and receiving a second posted write message in response to the first posted write message, wherein the second posted write message indicates a destination address list for the data. Also disclosed is a method of communicating data over a PCIe NTB comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message comprises a request to read data, and receiving a data transfer message comprising at least some of the data requested by the first posted write message.Type: GrantFiled: November 25, 2013Date of Patent: March 6, 2018Assignee: Futurewei Technologies, Inc.Inventors: Norbert Egi, Guangyu Shi
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Patent number: 9891858Abstract: A system and method for performing coarse-grained deduplication of volume regions. A storage controller detects that a first region of a first volume is identical to a second region of a second volume, wherein the first volume points to a first medium and the second volume points to a second medium. In response to detecting the identical regions, the storage controller stores an indication that the first range of the first medium underlies the second range of the second medium. Also in response to detecting the identical regions, the mappings associated with the second range of the second medium are invalidated.Type: GrantFiled: January 26, 2017Date of Patent: February 13, 2018Assignee: Pure Storage, Inc.Inventors: John Colgrove, Ethan Miller, John Hayes, Cary Sandvig, Christopher Golden, Jianting Cao
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Patent number: 9880954Abstract: A method of providing access to first data stored at a first device to a second device, the first device storing the first data in a memory accessible to said second device. The method comprises, at a control element distinct from each of said first and second devices accessing the stored first data in said memory accessible to said second device before said first data is accessed in said memory accessible to said second device by said second device.Type: GrantFiled: December 4, 2008Date of Patent: January 30, 2018Assignee: Micron Technology, Inc.Inventor: Marek Piekarski
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Patent number: 9880956Abstract: In a bus system that includes at least two subscribed data processing units that exchange messages via a bus in a serial data transmission, the transmitted messages are of a logical structure that includes a start-of-frame bit, an arbitration field, a control field, a data field, a CRC field, an acknowledge field and an end-of-frame sequence, the control field including a data length code, which contains information regarding the length of the data field. The CRC field of the messages can include any of two or more different numbers of bits depending on a value of an associated switchover condition (UB3).Type: GrantFiled: March 29, 2012Date of Patent: January 30, 2018Assignee: ROBERT BOSCH GMBHInventor: Florian Hartwich
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Patent number: 9870220Abstract: An electronic device includes routing logic operatively coupled to a communication port that is externally accessible so that there is no need to disassemble the electronic device to gain access. The port may be a USB (universal serial bus) port and provides access to an internal bus. The routing logic is also operatively coupled to a memory subsystem such that it may route data from an external device, connected at the port, to the memory subsystem to modify or replace a boot code, including a BIOS code. A memory interface device includes an interface module, a memory interface module for communicating with a memory subsystem including a boot PROM (programmable read only memory), and a routing logic coupled to the interface module and the memory interface module. The routing logic routes data from the external device to the boot PROM, so that a boot code, including a BIOS (basic input/output system), may be modified or replaced.Type: GrantFiled: December 5, 2008Date of Patent: January 16, 2018Assignee: Advanced Micro Devices, Inc.Inventor: Mikhael Lerman
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Patent number: 9864614Abstract: A method for providing virtualization of information handling resources includes accessing a information handling system and a information handling resource, accessing a first virtual function configured to cause virtualized access to the information handling resource through the interface, accessing a second virtual function configured to cause virtualized access to the information handling resource through the interface, and selectively mapping the first virtual function and the second virtual function to information handling systems of the system. The selective mapping includes preventing the first virtual function and the second virtual function from both being mapped to the same information handling system.Type: GrantFiled: February 20, 2015Date of Patent: January 9, 2018Assignee: Dell Products L.P.Inventors: Babu Chandrasekhar, Michael Brundridge
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Patent number: 9864719Abstract: In accordance with methods of the present disclosure, a system may include a switch and a management controller communicatively coupled to the switch. The switch may be configured to route input/output communications between a processor and a device. The management controller may be configured to, based on a measured bandwidth of communications of a communication link between the switch and the device, dynamically control at least one of a link width and a per-lane link speed of the communication link.Type: GrantFiled: March 12, 2015Date of Patent: January 9, 2018Assignee: Dell Products L.P.Inventors: Cyril Jose, Timothy M. Lambert, Jonathan Adonis Kwahk
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Patent number: 9830288Abstract: One embodiment of the present invention sets forth a method for transmitting data rendered on a primary computer to a secondary computer. The method includes transmitting to GPU graphics processing commands received from a graphics application, where the graphics processing commands are configured to cause the GPU to render a first set of graphics data, determining that graphics data should be collected for transmission to the secondary computer, conveying to the GPU that the first set of graphics data should be stored in a first buffer within a frame buffer memory, transmitting to the GPU graphics processing commands received from a process application executing on the primary computer, where the graphics processing commands are configured to cause the GPU to perform operations on the first set of graphics data to generate a second set of graphics data, and transmitting the second set of graphics data to the secondary computer.Type: GrantFiled: December 19, 2011Date of Patent: November 28, 2017Assignee: NVIDIA CORPORATIONInventor: Franck Diard
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Patent number: 9830297Abstract: A cubesat communications system includes an on-board computer implemented on a hardware platform. The on-board computer may include a system on module having a processor and a memory storing “boot” information. The on-board computer may also include a plurality of hardware interfaces implemented on the hardware platform to facilitate communication between the processor and a plurality of peripherals external to the on-board computer. The on-board computer may have a backplane having a plurality of connectors connecting the processor to the peripherals.Type: GrantFiled: February 26, 2015Date of Patent: November 28, 2017Assignee: SPIRE GLOBAL, INC.Inventors: Jeroen Cappaert, Jesse Trutna, Nicholas Shrake
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Patent number: 9825852Abstract: A method is described for serial data transmission in a bus system having at least two participating data processing units, the data processing units exchanging messages via the bus, the sent messages having a logical structure in accordance with CAN standard ISO 11898-1. When a first changeover condition is present, then, deviating from CAN, the data field of the messages can include more than eight bytes, the values of the data length code being interpreted, given the presence of the first changeover condition to determine the size of the data field. For forwarding data between the data field and the application software, at least one buffer memory is provided, and, if the size of the data field differs from the size of the buffer memory used, the forwarded quantity of data is adapted at least corresponding to the difference in size between the data field and the buffer memory.Type: GrantFiled: April 26, 2012Date of Patent: November 21, 2017Assignee: ROBERT BOSCH GMBHInventor: Florian Hartwich
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Patent number: 9823879Abstract: Managing a networked storage system having a host operable to connect through a network fabric to storage apparatus comprises: a configuration component for inputting a configuration change into the networked storage system responsive to change instructions; a monitoring component operable in communication with the host and the network fabric to monitor I/O activity associated with elements of the networked storage system; an activity data storage component responsive to the monitoring component for storing a record of a monitored I/O activity; an analysis component, responsive to the configuration component for inputting configuration changes, for analyzing the record of a monitored I/O activity for a recent activity; and an alert component, responsive to the analysis component detecting a recent activity, for alerting the configuration component.Type: GrantFiled: April 6, 2015Date of Patent: November 21, 2017Assignee: International Business Machines CorporationInventors: Christopher Canto, Bernard John Grainger, Nicholas Michael O'Rourke, Sivan Tal
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Patent number: 9813662Abstract: An aspect provides a method, including: ascertaining, at a first device, a request to transfer media data to another device; determining, at the first device, a plurality of connected devices for potential transfer of media data corresponding to the request; providing, at the first device, a disambiguation cue to a user; ascertaining via the disambiguation cue a target device from the plurality of connected devices for transfer of the media data; and transferring the media data to the target device. Other aspects are described and claimed.Type: GrantFiled: November 30, 2012Date of Patent: November 7, 2017Assignee: Lenovo (Singapore) Pte. Ltd.Inventors: Philip Lee Childs, Michael Terrell Vanover, Hui Wang, Shaowei Chen
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Patent number: 9804788Abstract: The present invention provides a mechanism for fast routing of data in a Storage Area Network. A protocol interface module (PIM) interfaces with outside networks and the storage devices, such as over fiber channel (FC). The PIM encapsulates received data into a streaming protocol, enabling storage processors to direct data to/from the appropriate physical disk in a similar manner to the directing of network messages over the Internet or other network.Type: GrantFiled: July 26, 2013Date of Patent: October 31, 2017Assignee: NetApp, Inc.Inventors: Rahim Ibrahim, Nghiep Tran, Tuan Nguyen, Chan Ng, James L. Cihla