Abstract: Described are platforms, systems, and methods for processing a chain of operations through an input output (IO) subsystem without central processing unit (CPU) involvement. In one aspect, a computer-implemented method comprises: providing, via the CPU, the chain of operations to the IO subsystem, wherein the IO subsystem is coupled to the one or more processors over Peripheral Component Interconnect Express (PCIe); processing, with the IO subsystem, the chain of operations by: retrieving, from a memory, data associated with the chain of operations; executing each of the operations in the chain to determine an output based on the data and output determined for any prior executed operation in the chain; and providing the output of each the executed operations for execution of the respective next operation in the chain; and providing, via the IO subsystem, an output for the chain of operations to the CPU.

Abstract: In one example, a method comprises: receiving, by a hardware data processor and from a network adapter, a transfer complete message indicating that the network adapter has initiated a transfer of data received from a network to the hardware data processor, the transfer being performed over an interconnect coupled between the hardware data processor and the network adapter; based on receiving the transfer complete message, performing, by the hardware data processor, a flush operation to fetch any remaining portion of the data buffered in the interconnect to a local memory of the hardware data processor; based on determining that flush operation is complete, storing, by the data hardware processor, the transfer complete message at the local memory; and based on determining that the transfer complete message is stored at the local memory, starting the computation operation of the data at the hardware data processor or preforming an error handling operation.

Abstract: For a bi-directional bus topology, a node connection includes two select line connections for a select line of a serial network. The select line is broken at the node connection. A bus direction module configures a first select line connection for an input line and a second select line connection for an output line in response to detecting a selection event. At least a portion of the bus direction module includes one or more of hardware and executable code, the executable code stored on a memory.

Abstract: An electronic meeting tool and method for communicating arbitrary media content from users at a meeting comprises a node configuration means adapted to operate a display node of a communications network, the display node being coupled to a first display. The node configuration means is adapted to receive user selected arbitrary media content and to control display of the user selected arbitrary media content on the first display. A peripheral device adapted to communicate the user selected arbitrary media content via the communications network is a connection unit comprising a connector adapted to couple to a port of a processing device having a second display, a memory and an operating system, and a transmitter. A program is adapted to obtain user selected arbitrary media content, said program leaving a zero footprint on termination. The user may trigger transfer of said user selected arbitrary media content to said transmitter.

Abstract: Methods, systems, and devices for memory systems having a selectively interfaceable memory subsystem are described. A memory system may include the memory subsystem that may be configurable to provide volatile storage, nonvolatile storage, or both to a host system. The memory subsystem may include a plurality of ports each capable of communicating with the host system using different interfaces. The memory subsystem may be dynamically configurable to perform different functions based on the demands of the host system. In some examples, memory systems described herein may include a first memory subsystem to provide nonvolatile storage to the host system, a second memory subsystem to provide volatile storage to the host system, and a third memory subsystem configurable to provide volatile storage or nonvolatile storage or both to the host system.

Abstract: A host system and a method for unlocking an electronic lock are provided. The host system includes a chassis, an electronic lock and a system circuit board. The chassis has a side door. The electronic lock is arranged on the side door for locking the side door on the chassis. The system circuit board is configured in the chassis, coupled to the electronic lock, and the system board has a plurality of universal serial bus ports. When the system board is not activated and a trigger voltage is received, the system circuit board detects an input sequence in which the USB ports are being inserted, and when the input sequence is equal to a predetermined sequence, the system circuit board outputs an unlock signal to the electronic lock so as to unlock the electronic lock device.

Abstract: An electronic apparatus has a processor; a peripheral having a data interface and a data-attribute interface; a direct memory access (DMA) controller for the peripheral; a memory; a bus system connecting the processor, the DMA controller, and the memory; a data link between the DMA controller and the peripheral; and a data-attribute link between the DMA controller and the peripheral, separate from the data link. The DMA controller has data-transfer circuitry for transferring data between the memory and the data interface of the peripheral over the data link, and for transferring data-attribute information, associated with the data, between the memory and the data-attribute interface of the peripheral over the data-attribute link.

Abstract: A microcontroller has a central processing unit and a plurality of peripheral units and a plurality of port bit circuits provided through at least one input/output port. At least one port bit circuit of the plurality of port bit circuits is not connected to an external pin and the at least one port bit circuit is configurable to route a signal received at the port bit circuit to a selected peripheral of the microcontroller.

Abstract: Implementations of the present disclosure are directed to systems and methods for mapping point-to-point channels to packet virtual channels. A chip with an point-to-point interface converts point-to-point data to a packet format. The point-to-point channels are mapped to virtual channels of the packet transmission protocol. Information from multiple point-to-point channels may be combined in a single packet. Among the benefits of implementations of the present disclosure is that point-to-point devices may be connected to a packetized network without losing the benefits of separate channels for different types of communication. This allows existing point-to-point devices to communicate using a packetized network without internal modification or performance degradation.

Abstract: A multi-memory SD card includes an enclosure having the outer dimensions of a standard SD card. Two separate SiP SD packages are provided along with two separate sets of electrical contacts each according to the SD standard to provide, in a single SD card bundle, the functions and performance of two SD cards. The SiP packages may both be full size SD format, or one may be a micro- or nano- SD card. The first and second SiP SD packages has the same or different capacity and/or speed, and the micro- or nano- SiP package is permanent or removable. An onboard battery and/or PCB may also be housed in the enclosure for configuring WiFi/redundant array of independent disks (RAID) or backup.

Abstract: Disclosed are a three-in-one multimedia cable and an electronic drawing board system. The three-in-one multimedia cable includes a USB-type-C plug, an HDMI plug, a USB-type-A plug, and a power supply plug, the USB-type-C plug is connected to the HDMI plug, the USB-type-A plug, and the power supply plug respectively. The electronic drawing board system includes the three-in-one multimedia cable, a USB-type-C socket, an analog switch, and an electromagnetic screen module, the USB-type-C plug of the multimedia cable is connected to the USB-type-C socket, an output end of the USB-type-C socket is connected to an input end of the analog switch, and an output end of the analog switch is connected to an input end of the electromagnetic screen module. The three-in-one multimedia cable can reduce the number of cables, which is convenient for users to use, and can be widely applied to the field of data cables.

Abstract: A wiring aggregation apparatus includes at least one subunit. The subunit includes: an input/output module to output, to a control module, a first serial signal obtained by performing parallel-serial conversion on plural pieces of contact information collected from devices, and to output, to a corresponding device, each of plural pieces of contact information obtained by performing serial-parallel conversion on a second serial signal acquired from the control module; and the control module to generate a transmit frame by arranging the first serial signal acquired from the input/output module at a defined frame position, to transmit the generated transmit frame to another wiring aggregation apparatus, to extract the second serial signal arranged at a defined frame position from a receive frame acquired from the another wiring aggregation apparatus, and to output the extracted second serial signal to the corresponding input/output module.

Abstract: Methods, systems, and apparatuses are described for determining a power state of a device. Identification data may be received, e.g., in a media device hub, from one or more devices coupled to the device hub. In some example implementations, the devices coupled to the device hub may comprise an intermediate device coupled to the hub via a first multimedia cable and a sink media device coupled to the intermediate device via a second multimedia cable. Attributes may be identified in the received identification data, such as attributes relating to one or more of the coupled devices. The attributes may be associated with one or more of the devices that are coupled to the device hub. Based on an association of attributes, a power state of one or more of the devices coupled to the hub may be determined.

Abstract: A storage apparatus in which a controller reads out a port status of a switch in a short period of time is disclosed. The storage apparatus includes a switch and a plurality of storage controllers configured to communicate with each other through the switch. The switch includes a switch processor, a plurality of data ports, a switch integrated circuit, a memory, and a management interface. One of the plurality of data ports and a management port of the management interface are connected to each other. The switch processor stores a status of the plurality of data ports acquired from the switch integrated circuit into the memory. The plurality of storage controllers access the management interface through the plurality of data ports and the management port and receive the statuses of the plurality of data ports stored in the memory from the management interface.

Abstract: Techniques for managing computing devices involve: determining an associated weight of each storage device based on a mapping relationship between each storage device in storage devices and partitions included in a switch, the partitions being respectively associated with the computing devices, the storage devices being respectively connected to downstream physical ports of the switch; determining a total associated weight of a storage pool based on the associated weight of each storage device, the storage pool being created based on the storage devices; and if it is determined that the total associated weight does not satisfy a predetermined balance condition, adjusting the mapping relationship between the partitions and the downstream physical ports. Accordingly, such techniques can dynamically adjust the mapping between the partitions of the switch and downstream physical ports, thereby balancing the workloads on the computing devices and buses.

Abstract: Provided is a high-capacity SSD that has the same form factor as 3.5-inch hard disk drives and has a structure where memory cards, such as standard M.2 SSDs, M.3 SSDs or nonstandard full-scale SSDs, are inserted in a horizontal sliding manner into an exterior having the same size as a 3.5-inch hard disk drive, and are provided in a multi-stage arrangement in the vertical direction. The SSD multiplier provides a high-capacity SSD case structure having a novel structure where a vertical backplane board is placed at a fixed position such that the case does not need to be disassembled even when an SSD memory card is replaced with another SSD memory card having a different length. Further provided is a case structure which can handle the various sizes of SSD memory cards that are used, where individual SSD memory cards have vibration resistance characteristics against external vibrations in XYZ-axis directions.

Abstract: A hot-plugged PCIe device configuration system includes a PCIe device with a PCIe configuration space having PCIe configuration space registers. A computing system includes a PCIe connector and a PCIe setting record database storing a first PCIe setting record having a first register write location value and first register value information. The computing system detects that the PCIe device has been hot-plugged into the PCIe connector, and uses the first register write location value in the first PCIe setting record to determine a location in the PCIe configuration space that provides a first PCIe configuration space register. The computing system then uses the first register value information in the first PCIe setting record to determine at least one register value change for the first PCIe configuration register, and writes the at least one register value change to the first PCIe configuration space register using the location.

Abstract: A network architecture including network storage. The network architecture includes a plurality of streaming arrays, each streaming array including a plurality of compute sleds, wherein each compute sled includes one or more compute nodes. The network architecture includes a PCI Express (PCIe) fabric configured to provide direct access to the network storage from compute nodes of each of the plurality of streaming arrays, the PCIe fabric including a plurality of array-level PCIe switches, each array-level PCIe switch communicatively coupled to compute nodes of compute sleds of a corresponding streaming array and communicatively coupled to the storage server. The network storage is shared by the plurality of streaming arrays.

Abstract: A method, an apparatus, and a device for transmitting a file based on a BMC, and a medium are provided. The method includes: sending, by using a first BMC, a preset command to a second BMC, before the first BMC transmits a data file to the second BMC; controlling the second BMC to stop an IPMI process running based on an I2C bus in response to the preset command; and controlling the first BMC to transmit the data file to the second BMC by using a communication function of the I2C bus. With the method, when the data file is transmitted between the BMCs, the IPMI process running on the BMC receiving the data file is stopped, such that the data file is not intercepted and verified by the command processing function of the IPMI process, and the IPMI process is prevented from being blocked and crashing.

Abstract: A switchable I2S interface including a multiplexer, a switchable FIFO memory and a switchable shift register, is disclosed. The multiplexer receives a transmission instruction or a receiving instruction, and configured to generate a switching signal according to the received instruction. The switchable FIFO memory is connected to the multiplexer and receives the switching signal, and comprise a transmission control circuit and a receiving control circuit. According to the switching signal, the switchable FIFO memory switches on the transmission control circuit to transmit the audio output signal, or switches on the receiving control circuit to receive the audio input signal. The switchable shift register is connected to the switchable FIFO memory, and receives and temporarily stores the audio output signal and the audio input signal.