Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One apparatus includes an input/output memory management unit (IOMMU) comprising: a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to the IOMMU and at least a second IOMMU; and hardware control logic operative to: synchronize the plurality of MMIO registers of the at least the second IOMMU; receive, from a peripheral component endpoint coupled to the IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the at least the second IOMMU; access the plurality of MMIO registers of the IOMMU based on context data of the DMA request; and access, from the IOMMU, a function assigned to the memory address space belonging to the at least the second IOMMU based on the accessed plurality of MMIO registers.

Abstract: In a memory system, a switch is connected between a controller and multiple non-volatile storage units, where the switch comprises first and second pins, a data bus, and a plurality of enable outputs. Each of the enable outputs of the switch is connected to an enable input of one of the non-volatile storage units. The switch is configured to transmit a signal to enable a communication path between the controller and one of the non-volatile storage units and to receive data over the data bus to be stored in one of the non-volatile storage units when the first and second pins are not asserted. In addition, the switch is configured to receive a command to be executed by one of the non-volatile storage units when the first pin is not asserted and the second pin is asserted. The switch is also configured to receive an address of a storage location within one of the non-volatile storage units when the first pin is asserted and the second pin is not asserted.

Abstract: Disclosed herein are devices and systems that embed a physical layer (e.g., an M-PHY) on a configurable integrated circuit (e.g., an FPGA) and include glue hardware that provides AC coupling between a high-speed serial communication device (e.g., a MIPI device) and the configurable integrated circuit. The glue hardware provides AC coupling using only resistors, capacitors, and inductors. The configurable integrated circuit includes a logic block that manages the operation to provide the desired PHY connectivity. Because the disclosed devices and systems use AC coupling, the signaling drive and receive paths are controlled based on the received signal frequency and not based on the mode (e.g., LS mode or HS mode). Specifically, the line state of the MIPI device is inferred from observation of signal transitions as opposed to direct detection of DC signal levels.

Abstract: An electronic apparatus and a hot-swappable storage device thereof are provided. The hot-swappable storage device includes a carrier, a connector, a controller, and a wireless communication interface. The carrier is configured to carry a plurality of storage components. The connector is configured to be electronically connected to a host end for performing a data transfer operation. The controller detects a connection status between the connector and the host end. The wireless communication interface decides whether to perform the data transfer operation according to the connection status.

Abstract: Systems, apparatuses, and methods for performing an allreduce operation on an enhanced direct memory access (DMA) engine are disclosed. A system implements a machine learning application which includes a first kernel and a second kernel. The first kernel corresponds to a first portion of a machine learning model while the second kernel corresponds to a second portion of the machine learning model. The first kernel is invoked on a plurality of compute units and the second kernel is converted into commands executable by an enhanced DMA engine to perform a collective communication operation. The first kernel is executed on the plurality of compute units in parallel with the enhanced DMA engine executing the commands for performing the collective communication operation. As a result, the allreduce operation may be executed in parallel on the enhanced DMA engine to the compute units.

Abstract: Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.

Abstract: The present invention provides an OBD interface bus type detection method and apparatus. The method includes: determining a first bus feature of a connection cable associated with a selected pin in an on-board diagnostics OBD interface; matching the first bus feature with an OBD interface bus library and determining a bus type of the connection cable associated with the selected pin; determining, according to the bus type of the connection cable associated with the selected pin, a second bus feature of the connection cable associated with the selected pin; and sending the second bus feature to a vehicle diagnostic instrument, to enable the vehicle diagnostic instrument to perform communications protocol scanning on the selected pin in the OBD interface according to the second bus feature.

Abstract: A data processing method, including: obtaining, by a device in a server, a first I/O request sent by a virtual machine, where the device is connected to the server through a PCIe bus, the virtual machine runs on the server, the device provides a plurality of VFs for the server, the first I/O request is initiated by the virtual machine for any one VF of the plurality of VFs, the first I/O request includes a read operation or a write operation, the read operation is used to perform a data read operation on an I/O device in the server, the write operation is used to perform a data write operation on the I/O device in the server; and reading or writing, by the device, data from or into the I/O device in the server based on the first I/O request.

Abstract: A transfer device for coupling a priority signal and a standard signal and transferring the signal includes a reception unit that receives a plurality of signals transmitted from a device connected to an opposite side of a transfer route, a separation unit that separates the signal into the priority signal and the standard signal, a signal defragmentation unit that defragments the plurality of standard signals, a multiplexing unit that multiplexes each of the priority signal and the standard signal, a priority control unit that determines a transfer order of the signals, a header information copy unit that copy header information of the standard signal, a transmission unit that transmits the signal to a device connected to the transfer route, an interrupt transfer processing unit that perform an interruption process when the priority signal arrives during the transfer of the standard signal, a signal fragmentation unit that fragments the standard signal, a header information assignment unit that assigns the h

Abstract: A method for synchronous serial communication includes encoding, by a master device, a header field to be initially transmitted in a frame with a header identification code and a slave count value that defines a number of slave devices communicatively coupled to the master device. A plurality of address fields to be transmitted in the frame are also encoded by the master device. Each of the address fields corresponding to a different one the slave devices. A first of the address fields to be transmitted in the frame corresponds to a last of the slave devices to receive the header field, and a last of the address fields to be transmitted in the frame corresponds to a first of the slave devices to receive the header field. The frame is transmitted to the slave devices by the master device.

Abstract: Techniques for concurrent transmission of audio and ultrasound are described. In an example, a computing device generates, in a digital domain, mixed audio data from multiple sets of audio data, each set corresponding to a different audio channel. The computing device also generates, in the digital domain, ultrasound data, and generates serial data by providing the mixed audio data and the ultrasound data as different inputs to an I2S mixing module. In an analog domain, the computing device generates an output signal based at least in part on the serial data, and sends the output signal to a speaker.

Abstract: A hybrid docking station determines whether native video data exists and can be passed through to a video port or whether a virtual video processor should be activated to provide virtual video data to a video port. For example, a laptop is connected to a hybrid docking station using a USB™ 3.0 connection. The hybrid docking station recognizes that the USB™ 3.0 connection includes a native video data and passes the native video data to a DisplayPort™. By avoiding activating a virtualized video processor and using native video data, the laptop avoids installing software to communicate with the virtualized video processor and communicates with one or more displays using a native video channel. By avoiding installing software, it simplifies IT's and user's usage and experience with universal docking station.

Abstract: Example approaches for processing task deployment in adapter devices and accelerators, are described. In an example, a service request is received by an adapter device. The service request is indicative of a service associated with a virtual multi-layer network switch. An accelerator may be integrated to the adapter device or coupled to the adapter device. A set of processing tasks associated with the service is identified based on the service request. A processing task instance corresponding to at least one of the set of processing tasks is deployed in one of the adapter device and the accelerator, based on predefined configuration information. The predefined configuration information includes policies for executing each of the set processing tasks in one of the adapter device and the accelerator.

Abstract: A signal tuning method for a peripheral component interconnect express (PCIe) includes assigning a first signal setting to the PCIe to generate a first PCIe signal, and tuning a link by the first PCIe signal, and determining whether to assign a second signal setting to the PCIe according to a signal status of the link, for generating a second PCIe signal to tune the link; wherein the PCIe is connected to a plurality of electronic devices via the link.

Abstract: Embodiments of systems and methods for fast input/output (IO) on PCIE devices are described. Such methods include receiving an IO request from a user or application, the IO request comprising instructions for communicating data with a host system, the host system comprising a processing device and a memory device, analyzing information from the IO request in an IO block analyzer to select one of a plurality of communication paths for communicating the data with the host system, defining a routing instruction in a transfer routing information transmitter in response to the selected communication path, communicating the routing instruction in a Transaction Layer Packet (TLP) to an integrated IO (IIO) module of the host system routing the data from the peripheral device to either the processing device or the memory device according to the routing instruction with a data transfer router.

Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals and control messages over a serial communication link. An apparatus includes a serial bus, and a controller configured to represent a series of signaling state of physical general-purpose input/output (GPIO) in a batch that comprises a sequence of virtual GPIO messages and control messages, generate a first header that includes timing information configured to control timing of execution of the batch, transmit the first header over a communication link, and transmit the batch over the communication link.

Abstract: Disclosed is a data transmission method. The method includes: sending, instruction information of data transmission to a slave node in a preset first cycle; judging, by the slave node, whether data should be sent according to the instruction information of data transmission; sending the data to the a master node if the slave node judges that the data needs to be sent; and sending, by other slave nodes, the data sequentially to the master node according to a preset slave node priority, an electric potential condition and a data state of the other slave nodes in a preset second cycle. In a preset first cycle, data is actively requested from a slave node, and in a preset second cycle, other slave nodes can actively send the data to a master node according to a preset slave node priority, an electric potential condition and a data state of the other slave nodes.

Abstract: A floating device location identification system includes a chassis defining floating device housings and including respective chassis location identification features adjacent each floating device housing that identify the relative location of that floating device housing. A floating device may be positioned in a first floating device housing and adjacent a first chassis location identification feature. The first floating device includes floating device cabling connector(s) that are connected via a cabling subsystem to a device location identification subsystem, and chassis engagement elements that are coupled to the floating device cabling connector(s) and that engage the first chassis location identification feature.

Abstract: An apparatus including a handshake window enabler having a pair of differential inputs and a window enablement output, a common mode detector coupled to a power input and a ground input and having a handshake inhibit output, and a handshake disabler coupled to the handshake window enabler, the common mode detector, and the pair of differential inputs. If a common mode voltage that out of range (“too high”) is detected, high speed handshake protocols are such that the bus operates a lower data rate.

Abstract: A transmitter circuit includes a drive circuit including; a drive circuit disposed in a first electronic device and configured to generate a setting signal and transmit the setting signal via a channel from the first electronic device to a second electronic device connected to the channel, a current source array configured to provide a current signal to the drive circuit, and a current controller configured to control the current source array, wherein the current signal provided by the current source array increases over a period extending from a first edge of the setting signal to a subsequent second edge of the setting signal.