Abstract: In a storage system including plural source storage devices, a target storage device selects which source storage device to accept a copy request from the target storage device so as to minimize the load on the entire system. The system calculates first and second load values for job loads being processed. System load values for the system are derived from job load value of a specific data, and respective load values for first and second source storage devices. The system compares the system load values to select a storage device to provide the data copy so as to minimize the load on the entire system.

Abstract: Circuits and methods for performing search operations in a content addressable memory (CAM) array are provided. A system for searching a CAM includes a circuit that selectively activates a main-search of a two stage CAM search while a pre-search of the two stage CAM search is still active.

Abstract: A method includes, in a nonvolatile memory device that includes a plurality of dies, detecting that a first temperature associated with a first die is equal to or exceeds a temperature threshold. A metablock is defined to include a first plurality of storage blocks that includes a first storage block of the first die. Each storage block of the metablock resides in a distinct die of the plurality of dies. The method also includes, in response to detecting that the first temperature is equal to or exceeds the temperature threshold, redefining the metablock to exclude from the redefined metablock any storage block associated with the first die.

Abstract: A system on chip (SoC) including a memory management unit (MMU) and a memory address translation method thereof are provided. The SoC includes a master intellectual property (IP) configured to output a request corresponding to each of a plurality of working sets; an MMU module comprising a plurality of MMUs, each of which is allocated for one of the working sets and translates virtual addresses corresponding to the request into physical addresses; a first bus interconnect configured to connect the MMU module with a memory device and to transmit the request, on which address translation has been performed in at least one of the MMUs, to the memory device; and a second bus interconnect configured to connect the master IP with the MMU module and to allocate one of the MMUs for each of the working sets.

Abstract: The present invention provides a data processing method based on a cache node group for data caching, where each cache node in the group includes a local replacement-allowable data storage space for storing data accessed by a local client and a collaborative replacement-allowable data storage space for storing data content accessed by a non-local client. By using the data processing method to process data content stored in the local replacement-allowable data storage space and the collaborative replacement-allowable data storage space of the cache node, the clients can obtain data more accurately and directly during access to the cache node, thereby meeting different requirements for local optimization of the cache node.

Abstract: The present disclosure describes methods, systems, and computer program products for measuring strength of a unit test. One computer-implemented method includes receiving software unit source code associated with a unit test, analyzing a line of the software unit source code for removability, initiating, by operation of a computer, modification of the software unit source code to remove the line of the software unit source code and create a modified software unit, initiating execution of the modified software unit using the unit test, determining success or failure of a unit test execution, and analyzing a next line of the software unit source code for removability.

Abstract: An integrated circuit has registers which it can place in a low power condition in which their state is lost; a power domain capable of reading the registers, the current operating mode of the domain being dependent on the state of the registers; a memory; and a configuration controller for configuring the registers. The configuration controller has access to a set of mappings. Each mapping indicates for bits represented in the memory the state of other bits storable in the registers. The configuration controller is configured to perform a register configuration operation by reading bits from the memory and populating the registers with a corresponding bit state.

Abstract: A method of writing data in a memory comprising a NAND cell array is disclosed, wherein a data output device completes the writing process only by transmitting the data and a start address for writing the data to the memory.

Abstract: A block grouping method includes the following steps. Firstly, a link list is established. In the link list, plural blocks are classified into plural groups according to valid data counts of respective blocks. If a host refreshes a stored data of a flash memory of the solid state drive or adds a new data into the flash memory, the valid data count of the block corresponding to the refreshed data or the new data is changed, and the link list is updated according to the changed valid data count of the block. After the garbage collection is started by the solid state drive, the block to be subject to the garbage collection is selected according to the link list, and the garbage collection is performed.

Abstract: Apparatuses and methods for storing a validity mask and operating apparatuses are described. A number of methods for operating an apparatus include storing a validity mask that is associated with a number of pages of memory cells in a group of pages and that provides validity information for the number of pages of memory cells in the group of pages.

Abstract: A method for building a multi-processor system with nodes having multiple cache coherency domains. In this system, a directory built in a node controller needs to include processor domain attribute information, and the information can be acquired by configuring cache coherency domain attributes of ports of the node controller connected to processors. In the disclosure herein, the node controller can support the multiple physical cache coherency domains in a node.

Abstract: Embodiments of the present invention disclose a method and an apparatus for allocating a memory space with a write-combine attribute, including: determining, when resources of devices are scanned, a type and a size of a resource required by each device; determining, after the scanning of the resources of the devices is completed, a total size of write-combine memory spaces required by all first devices; then determining a starting address used to allocate a write-combine memory space to the first devices; and allocating one memory space jointly to all the first devices and allocating, from the one memory space, a sub-memory space to each first device. According to the embodiments of the present invention, a memory space with a write-combine attribute can be allocated to devices in a more reliable manner and by using a relatively simple allocation method.

Abstract: A transactional memory (TM) includes a selectable bank of hardware algorithm prework engines, a selectable bank of hardware lookup engines, and a memory unit. The memory unit stores result values (RVs), instructions, and lookup data operands. The transactional memory receives a lookup command across a bus from one of a plurality of processors. The lookup command includes a source identification value, data, a table number value, and a table set value. In response to the lookup command, the transactional memory selects one hardware algorithm prework engine and one hardware lookup engine to perform the lookup operation. The selected hardware algorithm prework engine modifies data included in the lookup command. The selected hardware lookup engine performs a lookup operation using the modified data and lookup operands provided by the memory unit. In response to performing the lookup operation, the transactional memory returns a result value and optionally an instruction.

Abstract: A storage controller that includes a cache receives a command from a host, wherein a set of criteria corresponding to read and write response times for executing the command have to be satisfied. The storage controller determines ranks of a first type and ranks of a second type corresponding to a plurality of volumes coupled to the storage controller, wherein the command is to be executed with respect to the ranks of the first type. Destage rate corresponding to the ranks of the first type are adjusted to be less than a default destage rate corresponding to the ranks of the second type, wherein the set of criteria corresponding to the read and write response times for executing the command are satisfied.

Abstract: A storage controller that includes a cache receives a command from a host, wherein a set of criteria corresponding to read and write response times for executing the command have to be satisfied. The storage controller determines ranks of a first type and ranks of a second type corresponding to a plurality of volumes coupled to the storage controller, wherein the command is to be executed with respect to the ranks of the first type. Destage rate corresponding to the ranks of the first type are adjusted to be less than a default destage rate corresponding to the ranks of the second type, wherein the set of criteria corresponding to the read and write response times for executing the command are satisfied.

Abstract: A data storage system comprises a controller, a first lower performance storage medium and a second higher performance storage medium. The controller is connected to the storage mediums and is arranged to control Input/Output (IO) access to the storage mediums. In operation, the controller is arranged to store an image on the first storage medium, initiate a copy function from the first storage medium to the second storage medium, direct all IO access for the image to the second storage medium, and periodically age data from the second storage medium to the first storage medium.

Abstract: Exemplary method, system, and computer program product embodiments for priority based depopulation of ranks in a computing storage environment are provided. In one embodiment, by way of example only, multiple ranks selected for depopulation are prioritized. The highest priority rank of the multiple ranks is depopulated to a target rank. Additional system and computer program product embodiments are disclosed and provide related advantages.

Abstract: A data storage system comprises a controller, a first lower performance storage medium and a second higher performance storage medium. The controller is connected to the storage mediums and is arranged to control Input/Output (IO) access to the storage mediums. In operation, the controller is arranged to store an image on the first storage medium, initiate a copy function from the first storage medium to the second storage medium, direct all IO access for the image to the second storage medium, and periodically age data from the second storage medium to the first storage medium.

Abstract: Provided are a computer program product, system, and method for managing write operations to an extent of tracks migrated between storage device. An operation to migrate an extent of tracks from the second storage to the first storage is processed. A determination is made of the tracks in the extent having a write indicator indicating that the track was updated in the second storage since the previous time. The data for the determined tracks is copied from the second storage to free locations in the first storage. An extent object for the extent is updated to indicate the free locations to which the data for the tracks were copied as an active address for the track.

Abstract: A block management method for a rewritable non-volatile memory module having a plurality of physical blocks, and a memory controller and memory storage apparatus using the same are provided. The method includes logically grouping the physical blocks at least into a data area, a free area and a replacement area and configuring a plurality of logical blocks for mapping to the physical blocks of the data area. The method also includes assigning bad physical blocks into the data area and marking the logical blocks mapping to the bad physical blocks as bad logical addresses, thereby forbidding the access of the logical blocks mapping to the bad physical blocks. According, the method can effectively use the rewritable non-volatile memory module having too many bad physical blocks to store data.