Abstract: A system includes a first memory configured to store a first lookup table (LUT) with first metadata. A second memory is configured to store a second LUT with second metadata, wherein the first metadata includes a first mapping between logical addresses and physical addresses. The second metadata includes a second mapping between the logical addresses and the physical addresses. A control module is configured to update the first metadata. The control module is configured to update segments of the second metadata based on the first metadata at respective predetermined times. Each of the segments refers to a predetermined number of entries of the second LUT.

Abstract: The present invention is directed to a command block protocol which may implemented by RAID firmware for synchronizing I/Os in a RAID system which includes co-existing hardware and software-based I/O paths. The command block protocol of the present disclosure ensures that there aren't any I/Os outstanding in the fast path or any other hardware engine by making sure that the region lock (ex.—Sentinel Region Lock) is taken for the entire size of the volume. When the Sentinel Region Lock is granted, the RAID firmware may assume that there aren't any commands outstanding in the fast path hardware or pending for the region lock to be obtained. The RAID firmware would not be able to maintain integrity of user data in the absence of the new command block protocol disclosed herein.

Abstract: A method for managing non-volatile memory is provided. The method includes determining at least one property of a data and determining to which type of a plurality of types of flash memory to write the data, based on the at least one property of the data. The plurality of types of flash memory includes at least two types having differing numbers of bits per cell. The method includes writing the data to a flash memory of the determined type. A flash manager and a flash storage device are provided.

Abstract: This invention provides a request controlling apparatus, processor and method. The request controlling apparatus is connected to a request storage unit and includes: a queue unit storing flag recording region configured to record a storing flag corresponding to a queue unit in the request storage unit, a comparing means configured to judge whether a incoming first queue unit corresponds to a same message as an already existing queue unit, where the already existing queue unit is in the request storage unit and a flag setting means is configured to set the storing flag corresponding to the already existing queue unit in the queue unit storing flag recording region, to indicate that a message state related to the already existing queue unit will not be stored if the first queue unit corresponds to the same message as in the already existing queue unit.

Abstract: Systems and methods are provided for zero buffer copying, where such a system includes one or more high performance computing systems, each including one or more processors and a high performance memory. The system further includes a user space that includes a Java virtual machine (JVM) and one or more application server instances; and a plurality of byte buffers accesible to the JVM and the one or more application server instances. When a request is received by a first application server instance data associated with the request is stored in a heap space associated with the JVM, and the JVM pins the portion of the heap space where the data is stored. The data is pushed to a first byte buffer where it is accessed by the first application server instance. A response is generated by the first application server using the data, and sent by the first application server.

Abstract: A memory device cooperating with a memory controller scrambles each unit of data using a selected scrambling key before storing it in an array of nonvolatile memory cells. This helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. For a given page of data having a logical address and for storing at a physical address, the key is selected from a finite sequence thereof as a function of both the logical address and the physical address. In a block management scheme the memory array is organized into erase blocks, the physical address is the relative page number in each block. When logical address are grouped into logical groups and manipulated as a group and each group is storable into a sub-block, the physical address is the relative page number in the sub-block.

Abstract: A data merging method for merging data belonging to a first logical block in a rewritable non-volatile memory module is provided. The method includes getting a second physical block from a free area of the rewritable non-volatile memory module and determining whether a valid logical page number is smaller than a predetermined number. The method also includes, when the valid logical page number is smaller than the predetermined number, storing a corresponding page mapping table in a start physical page of the second physical block and writing at least one valid page data belonging to the first logical block into at least one physical page of the second physical block. Accordingly, the method can effectively shorten the time for merging data.

Abstract: Data signal items output by a radix 4n2m fast Fourier transform (“FFT”) operation may not be in the order desired for further use of those data items (e.g., they may be output in a non-natural order rather than in a desired natural order). Memory circuitry (e.g., dual-port memory circuitry) may be used in conjunction with circuitry for addressing the memory circuitry with address signals that are reordered in a particular way for each successive set of N data items. This allows use of memory circuitry with fewer data item storage locations than would otherwise be required to reorder the data items from non-natural to natural order. In particular, the memory circuitry only needs to be able to store N data items at any one time, which is more efficient memory utilization than would otherwise be possible.

Abstract: According to an embodiment, a memory system includes semiconductor memories each having a plurality of blocks; a first table; a receiving unit; a generating unit; a second table; and a writing unit. The first table includes a plurality of memory areas each associated with each block and in each of which defect information is stored. The generating unit generates a set of blocks by selecting one block to which data are to be written in each semiconductor memory based on an index number indicating one of a plurality of rows in the first table and the first table. In the second table, an index number and a channel number are stored for each logical block address in association with one another. When a write command is received by the receiving unit, the writing unit writes data to a block associated with a selected channel number among blocks constituting the set.

Abstract: A storage system includes a redundant array of independent disks (RAID), a file subsystem, and a multiple device control unit. The RAID includes a plurality of disks and a bitmap. The file subsystem is used for executing a write command and a trim command. The multiple device control unit does not execute a first synchronization operation on the plurality of disks during the RAID is built, does not execute a second synchronization operation on expansion capacity of the plurality of disks during the RAID is expanded, executes a third synchronization operation on at least one added disk according to the blocks of the plurality of disks occupied by the data during the RAID is reshaped, and/or executes a corresponding operation on at least one added disk according to the blocks of the plurality of disks occupied by the data during the RAID is recovered.

Abstract: A method for distributing IO load in a RAID storage system is disclosed. The RAID storage system may include a plurality of RAID volumes and a plurality of processors. The IO load distribution method may include determining whether the RAID storage system is operating in a write-through mode or a write-back mode; distributing the IO load to a particular processor selected among the plurality of processors when the RAID storage system is operating in the write-through mode, the particular processor being selected based on a number of available resources associated with the particular processor; and distributing the IO load among the plurality of processors when the RAID storage system is operating in the write-back mode, the distribution being determined based on: an index of a data stripe, and a number of processors in the plurality of processors.

Abstract: Input bits are stored in memory cells by mapping the input bits into a larger number of transformed bits using a shaping encoding that has a downward asymptotic bias with respect to a mapping of bit patterns to cell states and programming some of the cells according to that mapping of bit patterns to cell states. The programmed cells are erased before being programmed to store any other bits. The invention sacrifices memory capacity to increase endurance.

Abstract: A memory management method for managing physical units of a rewritable non-volatile memory module is provided. In the method, the physical units are grouped into at least a data area and a free area. The method includes obtaining empty physical units from the free area to configure a first global random area and obtaining empty physical units from the data area to configure a second global random area. The method further includes using the physical units of the first global random area to write updated data, and using the physical units of the second global random area to write other updated data after the physical units of the first global random area are written full of the updated data. Accordingly, the method can increase the storage space of a global random area, and thereby reduces data merging operations and shortens the time for executing a write command.

Abstract: Fine-grained detection of data modification of original data is provided by associating separate guard bits with granules of memory storing original data from which translated data has been obtained. The guard bits indicating whether the original data stored in the associated granule is protected for data coherency. The guard bits are set and cleared by special-purpose instructions. Responsive to attempting access to translated data obtained from the original data, the guard bit(s) associated with the original data is checked to determine whether the guard bit(s) fail to indicate coherency of the original data, and if so, discarding of the translated data is initiated to facilitate maintaining data coherency between the original data and the translated data.

Abstract: A method is provided for fine-grained detection of data modification of original data by associating separate guard bits with granules of memory storing original data from which translated data has been obtained. The guard bits indicating whether the original data stored in the associated granule is protected for data coherency. The guard bits are set and cleared by special-purpose instructions. Responsive to attempting access to translated data obtained from the original data, the guard bit(s) associated with the original data is checked to determine whether the guard bit(s) fail to indicate coherency of the original data, and if so, discarding of the translated data is initiated to facilitate maintaining data coherency between the original data and the translated data.

Abstract: Fine-grained detection of data modification of original data is provided by associating separate guard bits with granules of memory storing the original data from which translated data has been obtained. The guard bits facilitate indicating whether the original data stored in the associated granule is indicated as protected. The guard bits are set and cleared by special-purpose instructions. Responsive to initiating a data store operation to modify the original data, the associated guard bit(s) are checked to determine whether the original data is indicated as protected. Responsive to the checking indicating that a guard bit is set for the associated original data, the data store operation to modify the original data is faulted and the translated data is discarded, thereby facilitating data coherency between the original data and the translated data.