Patents Examined by Christopher Do
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Patent number: 9208114Abstract: A storage device being one of a plurality of storage devices storing data includes a memory and a processor coupled to the memory. The processor executes determining, when having received a new request and a new priority information during a preparation for an execution of another update processing, whether a new priority indicated by the new priority information is higher than a priority of the update processing in the preparation. The process including canceling the update processing in the preparation when having determines at the determining that the new priority is higher than the priority of the update processing in the preparation. The process includes forwarding the new request and the new priority information to another storage device when having determined at the determining that the new priority is higher than the priority of the update processing in the preparation.Type: GrantFiled: September 14, 2012Date of Patent: December 8, 2015Assignee: FUJITSU LIMITEDInventors: Munenori Maeda, Jun Kato, Tatsuo Kumano, Masahisa Tamura, Ken Ilzawa, Yasuo Noguchi, Toshihiro Ozawa
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Patent number: 9201795Abstract: A computing device-implemented method for implementing dynamic hierarchical memory cache (HMC) awareness within a storage system is described. Specifically, when performing dynamic read operations within a storage system, a data module evaluates a data prefetch policy according to a strategy of determining if data exists in a hierarchical memory cache and thereafter amending the data prefetch policy, if warranted. The system then uses the data prefetch policy to perform a read operation from the storage device to minimize future data retrievals from the storage device. Further, in a distributed storage environment that include multiple storage nodes cooperating to satisfy data retrieval requests, dynamic hierarchical memory cache awareness can be implemented for every storage node without degrading the overall performance of the distributed storage environment.Type: GrantFiled: June 21, 2012Date of Patent: December 1, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Binny S. Gill, Haim Helman, Edi Shmueli
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Patent number: 9201794Abstract: Described is a system and computer program product for implementing dynamic hierarchical memory cache (HMC) awareness within a storage system. Specifically, when performing dynamic read operations within a storage system, a data module evaluates a data prefetch policy according to a strategy of determining if data exists in a hierarchical memory cache and thereafter amending the data prefetch policy, if warranted. The system then uses the data prefetch policy to perform a read operation from the storage device to minimize future data retrievals from the storage device. Further, in a distributed storage environment that include multiple storage nodes cooperating to satisfy data retrieval requests, dynamic hierarchical memory cache awareness can be implemented for every storage node without degrading the overall performance of the distributed storage environment.Type: GrantFiled: May 20, 2011Date of Patent: December 1, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Binny S. Gill, Haim Helman, Edi Shmueli
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Patent number: 9158328Abstract: Dynamic power consumption is reduced by clock gating registers that synchronize memory input signals in an embedded memory array. Where a memory enable signal associated with a memory interface input signal does not meet setup timing for clock gating input registers of the memory interface signal, a clock gate enable signal may be generated prior to evaluation of the memory enable signal. The clock gate enable signal includes all functions of the memory enable signal and additional conditions because it is generated prior to evaluation of conditions on which the memory enable signal may depend. Pre-evaluated clock gate enable signals may be generated within a processor core and used to clock gate read address registers, write address registers, data input registers, and/or CAM reference address registers of an embedded memory array.Type: GrantFiled: December 20, 2011Date of Patent: October 13, 2015Assignee: Oracle International CorporationInventors: Heechoul Park, Song Kim, Jungyong Lee
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Patent number: 9141568Abstract: A memory controller receives memory operations via an interface which may include multiple ports. Each port is coupled to real-time or non-real-time requestors, and the received memory operations are classified as real-time or non-real-time and stored in queues prior to accessing memory. Within the memory controller, pending memory operations from the queues are scheduled for servicing. Logic throttles the scheduling of non-real-time memory operations in response to detecting a number of outstanding memory operations has exceeded a threshold. The throttling is proportional to the number of outstanding memory operations.Type: GrantFiled: August 25, 2011Date of Patent: September 22, 2015Assignee: Apple Inc.Inventors: Sukalpa Biswas, Hao Chen
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Patent number: 9063862Abstract: A method and system for cache management in a storage device is disclosed. A portion of unused memory in the storage device is used for temporary data cache so that two levels of cache may be used (such as a permanent data cache and a temporary data cache). The storage device may manage the temporary data cache in order to maintain clean entries in the temporary data cache. In this way, the storage area associated with the temporary data cache may be immediately reclaimed and retasked for a different purpose without the need for extraneous copy operations.Type: GrantFiled: May 17, 2011Date of Patent: June 23, 2015Assignee: SanDisk Technologies Inc.Inventors: William Wu, Sergey Anatolievich Gorobets, Steven Sprouse, Alan Bennett
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Patent number: 9047015Abstract: A method for migrating volumes in a storage system includes identifying an extent of data (belonging to a volume) requiring migration from a source extent to a target extent. The method allocates a selected number of copiers to the extent of data to migrate the extent of data from the source extent to the target extent. Each copier is configured to copy a unit of data, which is a smaller division of the extent of data. The method monitors destages (i.e., writes) that occur to the source extent as the copiers migrate the extent of data from the source extent to the target extent. In the event the destages occur faster than the copiers can copy units to the target extent, the method allocates additional copiers to the extent of data to assist in migrating the extent of data. A corresponding apparatus and computer program product are also disclosed.Type: GrantFiled: April 13, 2012Date of Patent: June 2, 2015Assignee: International Business Machines CorporationInventors: Xue Dong Gao, Kurt A. Lovrien, Richard A. Ripberger, Cheng-Chung Song
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Patent number: 9015439Abstract: A system and method are disclosed for an event lock storage device. The storage device includes a user partition and an event partition (which may be associated with an event). The storage device receives data from a host device, and stores the data in the user partition. In response to receiving an indication of an event, the storage device may designate the data as part of the event partition. The event partition may include a set of access rules that is different from the user partition, such as more restrictive rules for modification or deletion of a file containing the data.Type: GrantFiled: May 30, 2014Date of Patent: April 21, 2015Assignee: SanDisk Technologies, Inc.Inventors: Filip Verhaeghe, Bsa Chung, Samuel Yu, Michael Lavrentiev
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Patent number: 9003136Abstract: A system and method provide for a reception of data at a computer processor. The data relates to a dataset in a computer system. The computer processor calculates a weight for the dataset as a function of the data, and the processor executes an action on the dataset as a function of the weight. In an embodiment, the action is a backup of data on the computer system, and through recalculation of the weight over a period of time, the backup schedule, backup media, and other parameters are altered based on the changing weight for a dataset.Type: GrantFiled: December 26, 2012Date of Patent: April 7, 2015Assignee: CA, Inc.Inventor: Siva Sai Prasad Palagummi
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Patent number: 8990485Abstract: This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or pages. By performing a test transaction to program each bit of each such unit, the maximum expected programming time of each unit may be determined in advance and used for scheduling purposes. For example, in a straightforward implementation, a relatively accurate, empirically measured time limit may be identified and used to efficiently manage and schedule flash memory transactions without awaiting ultimate resolution of attempts to write to a non-responsive page. This disclosure also provides other uses of empirically-measured maximum flash memory transaction times, including via multiple memory modes and prioritized memory; for example, if a high performance mode is desired, low variation in flash memory transaction times may be tolerated, and units not satisfying these principles may be marked relatively quickly.Type: GrantFiled: June 13, 2013Date of Patent: March 24, 2015Assignee: Rambus Inc.Inventors: Brent Haukness, Ian Shaeffer
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Patent number: 8977810Abstract: Systems and methods for using memory commands are described. The systems include a memory controller. The memory controller receives a plurality of user transactions. The memory controller converts each user transaction into one or more row and column memory commands. The memory controller reorders the memory commands associated with the plurality of user transactions before sending the memory commands to a memory device.Type: GrantFiled: April 6, 2012Date of Patent: March 10, 2015Assignee: Altera CorporationInventors: Gordon Raymond Chiu, Teik Ming Goh, Muhamad Aidil Jazmi, Yu Ying Ong
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Patent number: 8959310Abstract: An approach is provided which a system selects a first virtual function from a plurality of virtual functions executing on a network adapter that includes a memory area. Next, the system allocates, in the memory area, a memory corresponding to the first virtual function. The system then stores one or more translation entries in the allocated memory partition, which are utilized to send data traversing through the first virtual function. As such, the system sends, utilizing one or more of the translation entries, the data packets from the network adapter to one or more destinations. In turn, the system dynamically resizes the memory partition based upon an amount of the memory partition that is utilized to store the one or more translation entries.Type: GrantFiled: July 28, 2012Date of Patent: February 17, 2015Assignee: International Business Machines CorporationInventors: Omar Cardona, Vinit Jain, Jayakrishna Kidambi, Renato J. Recio
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Patent number: 8954704Abstract: An approach is provided which a system selects a first virtual function from a plurality of virtual functions executing on a network adapter that includes a memory area. Next, the system allocates, in the memory area, a memory corresponding to the first virtual function. The system then stores one or more translation entries in the allocated memory partition, which are utilized to send data traversing through the first virtual function. As such, the system sends, utilizing one or more of the translation entries, the data packets from the network adapter to one or more destinations. In turn, the system dynamically resizes the memory partition based upon an amount of the memory partition that is utilized to store the one or more translation entries.Type: GrantFiled: August 12, 2011Date of Patent: February 10, 2015Assignee: International Business Machines CorporationInventors: Omar Cardona, Vinit Jain, Jayakrishna Kidambi, Renato J. Recio
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Patent number: 8935506Abstract: MemX provides a distributed system that virtualizes cluster-wide memory to support data-intensive and large memory workloads in virtual machines (VMs), and provides benefits in virtualized settings: (1) VM workloads that access large datasets can perform low-latency I/O over virtualized cluster-wide memory; (2) VMs can transparently execute very large memory applications that require more memory than physical DRAM present in the host machine; (3) reduces the effective memory usage of the cluster by de-duplicating pages that have identical content; (4) existing applications do not require any modifications to benefit from MemX such as the use of special APIs, libraries, recompilation, or relinking; and (5) supports live migration of large-footprint VMs by eliminating the need to migrate part of their memory footprint resident on other nodes.Type: GrantFiled: March 22, 2012Date of Patent: January 13, 2015Assignee: The Research Foundation for The State University of New YorkInventor: Kartik Gopalan
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Patent number: 8924682Abstract: In one embodiment, a system includes a main data system, a virtual tape volume coupled to receive a write request from the main data system, and an accidental loss protection system configured to receive the write request to the virtual tape volume, detect whether the write request overwrites a label of the virtual tape volume, and prevent the overwriting of the label.Type: GrantFiled: April 11, 2012Date of Patent: December 30, 2014Assignee: EMC CorporationInventors: Larry W. McCloskey, Thomas McCafferty
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Patent number: 8924656Abstract: One or more techniques and/or systems are provided for configuring a storage environment. In particular, the storage environment may be configured with a symmetric frontend and an asymmetric backend. That is, an owner storage controller may be granted read/write access to a storage device owned by the owner storage controller, while a non-owner storage controller may be granted merely read access. In this way, the owner storage controller may execute, log, and/or commit a write command to the storage device, while the non-owner storage controller may merely execute, but not log and/or commit, a write command. Write buffers, log memories, and/or file system metadata may be synchronized between the owner storage controller and the non-owner storage controller, such that the non-owner storage controller may efficiently take ownership of the storage device in response to a failure of the owner storage controller.Type: GrantFiled: April 26, 2012Date of Patent: December 30, 2014Assignee: NetApp, Inc.Inventors: Ameya Prakash Usgaonkar, Parag Deshmukh, Siddhartha Nandi, Bipul Raj
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Patent number: 8924665Abstract: A primary storage device maintaining recovery data in connection with ordering data writes includes the primary storage device receiving a plurality of data writes, the primary storage device associating data writes begun after a first time and before a second time with a first chunk of data, and the primary storage device associating data writes begun after the second time with a second chunk of data different from the first chunk of data. After completion of all writes associated with the first chunk of data, the primary storage device initiates transfer of writes associated with the first chunk of data to a secondary storage device. The primary storage device maintains a transfer log of data from the first chunk that is successfully transferred to the secondary storage device.Type: GrantFiled: August 31, 2011Date of Patent: December 30, 2014Assignee: EMC CorporationInventors: Vadim Longinov, Mark Halstead, Benjamin Yoder
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Patent number: 8904107Abstract: A storage apparatus and program update method for reducing tediousness and complications of drive inventory management. A storage apparatus 10 includes a disk unit 400 composed of a plurality of first drives 420 storing first firmware of the same type, a controller 100 for controlling data during operation of the first firmware, a relay device 300, and a second drive 520. Then, the second drive 520 stores second firmware of the same type as that of the first firmware and third firmware of a type different from that of the first firmware. The controller 100 includes: a firmware comparison unit for comparing the first firmware with the second firmware; a firmware comparison unit for deciding firmware to operate on the storage apparatus 10 based on the comparison result; and a firmware update unit for updating the firmware operating on the first drive 420 or the second drive 520 with the decided firmware.Type: GrantFiled: March 14, 2012Date of Patent: December 2, 2014Assignee: Hitachi, Ltd.Inventors: Yusuke Matsumura, Tomohisa Ogasawara, Yukiyoshi Takamura, Ryoma Ishizaka
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Patent number: 8898372Abstract: A memory storage device, a memory controller, and a data writing method are provided. The memory storage device has a rewritable non-volatile memory chip including a plurality of physical units, and each of the physical units has a plurality of physical pages. The data writing method includes configuring a plurality of logical units to be mapped to a portion of the physical units, and each of the logical unit has a plurality of logical pages. The data writing method also includes receiving a first write data from a host system and writing the first write data into the ith physical page in a substitute physical unit selected from the physical units. The data writing method further includes writing a first address access information corresponding to the first write data and a second address access information into the ith physical page. Herein i is a positive integer.Type: GrantFiled: May 20, 2011Date of Patent: November 25, 2014Assignee: Phison Electronics Corp.Inventor: Chih-Kang Yeh
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Patent number: 8892828Abstract: Apparatuses and methods for storing a validity mask and operating apparatuses are described. A number of methods for operating an apparatus include storing a validity mask that is associated with a number of pages of memory cells in a group of pages and that provides validity information for the number of pages of memory cells in the group of pages.Type: GrantFiled: November 18, 2011Date of Patent: November 18, 2014Assignee: Micron Technology, Inc.Inventor: Steven R. Narum