Abstract: A file system is capable of retrieving image information stored in a microfilm file and image information stored in a disk through common input information.

Abstract: An interrupt system provides interrupt signals to devices to be interrupted by indicating the presence of interrupts in a random access memory associated with each of the devices to be interrupted. The address of the interrupt signal that is written is assigned to a respective one of a plurality of addresses, each of which is assigned to a respective one of a plurality of interrupting devices and is indicative of the priority of the interrupt. The controller associated with each of the devices to be interrupted causes a scan of the associated memory and when an interrupt is detected, the address of the interrupt is sent to the interrupted device. The interrupted device then recognizes the interrupt by reason of its address and performs the appropriate interrupt routine. When an interrupt is written into the memory, a comparison is made of the address of the newly written interrupt with the address of the last scanned position.

Abstract: A multiprocessor which includes a plurality of processing units interconnected by a global bus. Each processing unit has the capability for initiating control instructions including notification instructions and for selectively transmitting the control instructions over the global bus to the plurality of processing units and trigger device for initiating execution of the control instructions as a destination processing unit. A multiprocessor so constructed is capable of executing blocks of instructions sequentially or concurrently or both at required by a single program to reduce program execution time to a minimum.

Abstract: A system for recognizing individually spoken words includes an acousto-electric transducer with a controllable amplifier and a high-pass filter connected to a level calculation path for calculating the level of the output signal by detecting the signal envelope and converting the envelope signal to a 1-bit digital signal to be supplied to a microprocessor. A signal analysis path is also connected to the transducer and includes a low-pass filter followed by a 1-bit analog to digital converter and a digital processing unit which supplies data units to the microprocessor. Individually spoken words are recognized and actions taken accordingly.

Abstract: A data processing system which includes a central processor unit which has an arithmetic logic unit (ALU) for performing fixed point arithmetic operations and a separate floating point unit (FPU) for performing floating point operations and which uses multi-level microcode architecture wherein each unit has its own control store (a "horizontal" store) which responds to addresses of execution control signals supplied thereto from a common control store (a "vertical" store) to produce horizontal microinstructions for performing ALU and FPU operations, respectively. Selected ones of such addresses are recognized for ALU operations by the CPU control store only, other selected ones are recognized for FPU operations by the FPU control store only, while still other selected ones are recognized for both ALU and FPU operations by both control stores so that such operations can be performed simultaneously in parallel.

Abstract: A system for implementing a bus window interlock scheme between a first and a second bus utilizes two bus window modules. The first bus window module coupled to the processor bus includes an interlock state bit which is set upon the acceptance of an interlock transaction from a processor. No further interlock transactions will be accepted while the interlock state bit is set. The interlock transaction is passed to a transaction buffer in the second bus window module which is coupled to memory through the memory bus. The transaction buffer passes the interlock data for memory to the memory bus while simultaneously loading a one deep interlock buffer. A confirmation is sent from the memory back to the transaction buffer. If the confirmation is interlock busy, then the interlock transaction is retried from the interlock buffer thus allowing the transaction buffer to process other commands.

Abstract: A central processing unit for a digital computer. In one embodiment, the central processing unit comprises a plurality of pointer registers that may be used during instruction execution to directly address other registers. In a second embodiment, the central processing unit comprises a size register that is loaded during the decode of an operation code with a size code indicating the data path width for that operation code. During instruction execution, the size code may be used at various times to determine data path width.

Abstract: A pipelined paralled vector processor decreases the time required to process the elements of a single vector stored in a vector register. Each vector register of a plurality of vector registers is subdivided into a plurality of smaller registers. A vector, stored in a vector register, includes N elements; however, each of the smaller registers store M elements of the vector, where M is less than N. A pipelined element processor is associated with each smaller register for processing the M elements of the vectors stored in the smaller register and storing a result of the processing in a result register. Each of the smaller registers of the vector registers, and its corresponding element processor, comprise a unit. A plurality of units are connected in a parallel configuration. The element processors, associated with each unit, have been loaded with the result, the result being stored in a result register.

Abstract: The computer (10) includes a memory control unit (12), a central processing unit (14) and a memory array unit (16). A plurality of memory array planes (36, 38, 40 and 42) are included within the memory array unit (16). A latch (82) receives write data from the memory control unit (12) through a bus (26). Address and control information is transferred from the memory control unit (12) to timing and address circuits (28, 30, 32, 34). The write data is transferred from the latch (82) into a selected one of the memory array planes (36, 38, 40, 42). For each of the memory array planes (36, 38, 40, 42) there is provided a respective read latch (60, 62, 64, 66) for receiving read data. The ouputs of the memory array planes are not connected in common. The ouputs to read latches (60, 62, 64,66) are connected in common through a bus (76) for transferring read data through the data bus (26) back to the memory control unit (12).

Abstract: A parallel vector processor includes a plurality of vector registers, each vector register being subdivided into a plurality of smaller registers. A vector is stored in each vector register, the vector has a plurality of elements. The elements of the vector are assigned for storage in the smaller registers of the vector register. In the parallel vector processor, assume that each vector register is subdivided into M smaller registers. The first successive M elements of an N element vector are assigned for storage in the M smaller registers of the vector register. An element processor is connected to each smaller register. Therefore, the first successive M elements of the N element vector are processed by the element processors 1 through M. The second successive M elements of the N element vector are assigned for storage in the same M smaller registers. The third successive M elements of the N element vector are assigned for storage in the M smaller registers.

Abstract: A control system for a micro-Winchester or smaller disk file includes head position control circuitry including at least one servo loop for controlling an electromechanical head positioner relative to a rotating data storage disk, a data controller for controlling reading and writing of data blocks from and to a storage surface of the disk, an interface circuit for connecting the disk file directly to data, address and control buses of a host computer, and a single microprocessor programmed to supervise operations of the head position control circuitry, data controller and interface circuit.

Abstract: A data processor and method includes a timer system for producing a first output compare signal when a counter value equals a compare value. A register alternatively produces a second output compare signal in response to having a given bit value written therein. Logic circuitry provides an output compare function in response to either the first or the second output compare signals.

Abstract: Disclosed is a method and system for creating a visual display of data from an input data set in which the data are not fixed into display-acceptable format until the data are stored in a local memory of the visual display. At least one of a plurality of sources of resource information is initially selected as required by the input data set. Control signals corresponding to the sources of resource information are thereafter embedded into the input data set to form an output data set. Subsequently, the selected sources of resource information and the output data set are applied to the local memory. They are concurrently taken from this local memory to produce a visual display. Fixation of the data into display acceptable format is thereby postponed until just prior to actual display to thereby provide a substantial increase in system flexibility.

Abstract: The invention disclosed provides an intelligent input/output system for a programmable controller and includes a plurality of input/output (I/O) modules, each of which may be located in proximity to the process being controlled. Each module is interconnected, via a communications link, to a central processor unit (CPU) through an I/O controller. Each module is made up of a plurality of input/output circuits and each may be selectively operated as an input circuit or as an output circuit. The selection is preferably under control of the CPU. Each I/O module includes an operations control unit for controlling each I/O circuit and for providing an exchange of diagnostic and control signals between each I/O circuit and the I/O controller and CPU. Communications between the operations control unit and each I/O circuit is preferably carried out via a pair of conductors, one conductor of which conveys a set of recurring control signals (e.g.

Abstract: A computer system having a disk cache unit between a disk unit and the main storage unit. Ordinarily, the data transfer processing is carried out between the disk unit and the disk cache unit and between the disk cache unit and the main storage unit in this case. The present invention is characterized by enabling these two data transfer operations to be executed in parallel and to prevent a director from becoming the bottleneck of the processing due to the concentrated processing requests. For this purpose, the present invention provides for conducting a data transfer between the disk cache unit and a disk unit while a data transfer is taking place between the main storage unit and the disk cache unit. The director is configured, for example, with two data transfer controlling systems and two data transfer units for carrying out data transfer according to instructions for the two data transfer controlling systems.

Abstract: The identity of a desired video disk is compared to the identity of a video disk in use in a video disk player. If the desired video disk is not the same as the video disk in the player, instructions are given to change the video disk, and a comparison is again made.

Abstract: A block diagram editor system and method is implemented in a computer workstation that includes a Cathode Ray Tube (CRT) and a mouse, graphics and windowing software, and an external communications interface for test instruments. The computer is programmed for constructing, interconnecting and displaying block diagrams of functional elements on the CRT. From prestored routines for each functional element, the software assembles and executes a program that emulates the functional operations of each element and transfers data from output from each element in turn to an input of a succeeding block, as determined by the block diagram configuration. The block functions include signal generating and analysis functions, and functions for control of various types of test instruments, which can be interactively controlled through the CRT and mouse. The computer converts desired outputs of the instruments into control settings and receives, analyzes and displays data from the instruments.

Abstract: In a speech recognition system for effecting substantially linear matching, a start point of an input speech pattern is detected to start counting the frames of the input speech pattern for updating a speech frame number. Each time the speech frame number is updated, a plurality of frame numbers of reference templates are generated in substantially a linear relationship to the frame number, thus providing a plurality of matching paths between each of the reference templates and the input speech pattern. The distance between the input pattern data and the reference template data between the corresponding frames specified by each matching path is calculated each time the speech frame number is updated. An accumulated value of the distances along a matching path from the start point of the input speech until a desired speech frame is regarded as a dissimilarity, and the dissimilarity corresponding to each matching path in each reference template is calculated each time the speech frame is updated.

Abstract: A digital computing system includes at least a first and a second bus with at least a first master connected to the first bus and a second master connected to the second bus. The first master is capable of requesting the second bus through the first bus and the second master is capable of requesting the first bus through the second bus. Central conversion means receives both requests and has circuitry for generating a response signal to the first bus when both requests come simultaneously. The first master receives the response signal and continues the cycle, but without continuing the request for the second bus. The cycle is completed as though the request had been completed.

Abstract: An electronic apparatus such as a compact computer stores a certain set of information which is useful in its operation such as a list of character codes and corresponding characters or the names of commands that can be used and the methods of using them. Such information can be displayed by entering a specified command or a character string with one or more characters, including a help requesting key.