Abstract: Apparatus for performing mixed precision calculations in the floating point unit of a microprocessor from a single instruction opcode. 80-bit floating-point registers (44) may be specified as the source or destination address of a floating-point instruction. When the address range of the destination indicates (26) that a floating point register is addressed, the result of that operation is not rounded to the precision specified by the instruction, but is rounded (58) to extended 80-bit precision and loaded into the floating point register (FP-44). When the address range of the source indicates (26) that an FP register is addressed, the data is loaded from the FP register in extended precision, regardless of the precision specified by the instruction. In this way, real and long-real operations can be made to use extended precision numbers without explicitly specifying that in the opcode.

Abstract: An improved control system for a disk file includes head position control circuitry including at least one servo loop for controlling an electromechanical head positioner relative to a rotating data storage disk, a data controller for controlling reading and writing of data blocks from and to a storage surface of the disk, an interface circuit for connecting the disk file directly to data, address and control buses of a host computer, and a single microprocessor programmed to supervise operations of the head position control circuitry, data controller and interface circuit.

Abstract: A multi-microprocessor implemented data processing system having a single cycle data transfer capability for its memory mapped peripheral devices is described. A host or controlling microprocessor provides address and control signals for memory accesses. In addition, it also determines that a peripheral operation is desired. When this occurs, a command is sent to the selected peripheral and a memory cycle, fetch or store, for the data transfer is initiated. The address bus is provided with the memory address for the needed data and a special decode that indicates the unique nature of this memory access. Logic circuit means are provided to detect the special decode and to intercept the data bus at the appropriate point in the bus cycle in response thereto. The logic circuit means is adapted to then responsively apply the correct control signals to the peripheral to enable the desired data transfer after the data bus has been intercepted.

Abstract: A central processing unit for a digital computer. In one embodiment, the central processing unit comprises a plurality of pointer registers that may be used during instruction execution to directly address other registers. In a second embodiment, the central processing unit comprises a size register that is loaded during the decode of an operation code with a size code indicating the data path width for that operation code. During instruction execution, the size code may be used at various times to determine data path width.

Abstract: A Dynamic Memory Access (DMA) control device for transmitting data between a data transmitter and a data receiver via an external bus formed of a data bus, an address bus and a control bus, and has a multiplicity of data transmitters/receivers and at least one microprocessor connected thereto. The transmission of the data in the external bus depends upon a channel program containing channel transfer commands and channel control commands, and includes a central control unit for addressing, dependent upon a channel command, a microcommand, address and control signals corresponding to the microcommand on an internal address-control bus; an address unit is connected to the internal address/control bus and to an internal data bus wherein addresses of a data transmitter, data receiver and the channel program are stored.

Abstract: A controlled flow parallel computer incorporating a node drive register which designates the location of executable instructions. The node drive register allows instructions to be executed concurrently and non-deterministically without a complex control.Control token locations in the node drive register associated with a given instruction are filled upon the completion of a prior instruction required to be executed before executing that instruction. The instruction is ready for execution once the control token locations are filled.

Abstract: Data processing apparatus includes a data path having a path delay, from a source latch point to a destination latch point, of greater than one clock cycle. For an n-cycle path, where the path delay is between n- 1 and n clock cycles, data is latched into the source latch point at least n clock cycles in advance of the cycle on which it is needed at the destination latch point. The data and gating signals along the data path are held glitch-free in the source latch point until after the clock cycle on which the data is used in the destination latch point.

Abstract: A garbage collection system for digital computers classifies memory objects into generations. Objects in older generations which need to reference younger generations must do so indirectly through indirection cells located in the older generation. Thus, all pointers into a generation come from younger generations or indirection cells. When a generation is collected, the indirection cells in that generation are defined to be oldspace and collected in the usual manner. Indirection cells of older generations which can point to the generation being collected are processed by a scavenger.The system also includes read and write barriers which function to filter out undesirable pointers based on the classification and volatility of memory regions to which they point or are destined to be stored.

Abstract: A microprogram controlled data processing apparatus executes multi-operand instructions in which one or more operand specifiers are provided for specifying the addressing for each operand independently from the operation code of the instruction. An instruction execution unit receives a top address of a microprogram from a decoding unit, a ready status signal and a signal from the decoding unit indicating whether a destination of an operand is in a general purpose register or in a memory unit, and writes an operand into a destination address of a register on the memory unit under control of a microprogram. Because the destination of the operand is indicated by the instruction decoding unit, it is not necessary to determine this information by microinstruction execution, with the result that execution of the instruction can be performed at high speed.

Abstract: An interruption control apparatus includes registers storing priority data and a circuit producing scanning data in a priority order. The priority data is compared with the scanning data by a scanning operation. If the priority data is equal to the scanning data, a coincidence signal is generated. An interruption request signal from an interruption source is transferred to an interruption processing unit only when the coincidence signal is being generated. Thus, a priority control for a plurality of interruption requests can be performed by using a simple hardware circuit without complex software processing.

Abstract: A massively parallel processor comprising 65,534 (=2.sup.16) individual processors is organized so that there are 16 (=2.sup.4) individual processors on each of 4,096 (=2.sup.12) integrated circuits. The integrated circuits are interconnected in the form of a Boolean cube of 12 dimensions for routing of message packets. Each circuit board carries 32 (=2.sup.5) integrated circuits and each backplane carries 16 (=2.sup.4) circuit boards. There are eight (=2.sup.3) backplanes advantageously arranged in a cube that is 2.times.2.times.2. Each integrated circuit on a circuit board is connected to five integrated circuits on the same board which are its nearest neighbors in the first five dimensions. Further, each integrated circuit is also connected to four other integrated circuits on different circuit boards, but on the same backplane. Finally, each integrated circuit is also connected to three other integrated circuits, each on a different backplane.

Abstract: The various functional units which comprise a central processing unit of a computer are organized so as to enable a main arithmetic logic unit and special function units including an auxilliary arithmetic logic unit to access data registers, literal constants, and data from a memory cache. A general purpose bus closely couples the functional units to the main data paths and allows the CPU sequencer to branch on numerous conditions which may be indicated via test lines. Parity from the functional units is sent to clock cycle later than results in order that the parity path does not affect machine cycle time. The architecture allows unused microcode options to be used to check for correct CPU operation by halting CPU operation on a miscompare of two buses.

Abstract: The present invention relates to a computer system having a disk cache unit between a disk unit and the main storage unit. Ordinarily, the data transfer processing is carried out between the disk unit and the disk cache unit and between the disk cache unit and the main storage unit in this case under control of a director. The present invention is characterized by enabling these two data transfer operations to be executed in parallel and to prevent the director from becoming the bottleneck of the processing due to the concentrated processing requests. For this purpose, the present invention provides for a data transfer between the disk cache unit and a disk unit while a data transfer is taking place between the main storage unit and the disk cache unit.

Abstract: A dual language numerical controller includes a terminal (8') for entering both a numerical control (NC) language program and a higher level language, such as BASIC, program, a language discriminator (31) for determining which language has been entered, a higher level language interpreter (32) and an NC language interpreter (33), both for producing NC instruction data and an NC data table formatter (34) for arranging the instruction data in the order of which the entered programs produced them.

Abstract: The embodiments enable address translations for a virtual machine in the TLB (translation lookaside buffer) of a CPU to be retained from exiting a SIE (start interpretive execution) instruction to the next SIE entry to interpretive execution for the same guest (virtual machine CPU). Conditions are defined which determine when guest TLB entries must be invalidated. These conditions require invalidation of guest TLB entries only within and on entry to interpretive execution. A single invalidation of guest TLB entries on entry to interpretive execution is required for any number of conditions recognized while a CPU is not in interpretive execution state. For a guest in a virtual multi-processor (MP) machine, an interlock is provided to allow the use of guest virtual addresses by host instruction simulation and the need for guest TLB invalidation is broadcast to all other real CPUs in a real MP system so that all guest TLBs on all real CPUs can be invalidated to maintain integrity.

Abstract: A memory system for association with a user processor for operation independently from the user processor includes a physical memory and an interface unit for enabling the associated user processor to access the physical memory. The physical memory is represented in a virtual address space which is garbage collected in parallel with the operation of the user processor. The garbage collection process includes reference count deallocation and a garbage collection algorithm for deallocating cyclic structures not deallocated by the reference count process. The reference count process includes providing for a reference count indicating the number of pointer references to a memory block in the virtual address space. When the reference count becomes zero, and no other references to a memory block exist, the block may be freed. In the garbage collection algorithm, the virtual memory space is traced in areas, called OLDSPACE, and compactly copied into a new area, called NEWSPACE.

Abstract: Disk drive control apparatus for controlling operation of a disk drive. The disk drive control apparatus has hierarchical control and includes control apparatus for controlling other components of the disk drive control apparatus, a controller interface receiving a bus connecting the disk drive control apparatus to a controller, a read-write processor for processing data received from or read to the disk, and data transfer apparatus for transferring data alternatively between the bus connected to the controller interface and the read-write processor, between the bus and the control apparatus, and between the read-write processor and the control apparatus. The control apparatus receives operational instructions from the controller via the bus, and responds to the operational instructions by providing internal instructions for the data transfer apparatus and the read-write processor.

Abstract: An electrical interface system provides a set of signals to be used in transferring information between first and second terminals. To transfer information from the first terminal to the second terminal, a WRITE CLOCK, FUNCTION/DATA READY, four CODE, one CODE PARITY, 16 DATA and DATA PARITY signals are provided. To transfer information from a second terminal to the first terminal, a READ CLOCK, STATUS/DATA READY, ERROR, DONE, INDEX/SECTOR MARK, STATUS PARITY, 16 DATA and one DATA PARITY signals are provided. The four CODE signals may be formed to signal any one of a plurality of requested functions to the second terminal, while the second terminal may indicate its general status to the first terminal with the ERROR, DONE, READY and MARK signals, each terminal capable of further defining functions or status by formation of words with the data signals.

Abstract: A digital logic controller providing instruction execution times on the order of 50 nanoseconds and employing a read-only memory outputting instructions to a pipeline register, a portion of each instruction providing a status-select control signal and address signals for controlling selection of the next instruction from the read-only memory.

Abstract: A microcomputer has the capacity for executing instructions, requesting prefetches of instructions, and experiencing a change in instruction flow, or a branch. The microcomputer also knows in advance that a change in instruction flow is going to occur. At such time that a branch becomes known there may also be a pending instruction prefetch request. Because a branch is going to occur, there is no need to execute the prefetch. Consequently, the pending instruction prefetch is flushed which thus avoids wasting time making an unnecessary instruction prefetch.