Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.

Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.

Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.

Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.

Abstract: Provided is a semiconductor device and a fabricating method thereof. The semiconductor device includes a first trench having a first depth to define a fin, a second trench formed directly adjacent the first trench having a second depth that is greater than the first depth, a field insulation layer filling a portion of the first trench and a portion of the second trench, and a protrusion structure protruding from a bottom of the first trench and being lower than a surface of the field insulation layer.

Abstract: A magnetoresistive random-access memory (MRAM) device is disclosed. The device described herein has a spin current injection capping layer between the free layer of a magnetic tunnel junction and the orthogonal polarizer layer. The spin current injection capping layer maximizes the spin torque through very efficient spin current injection from the polarizer. The spin current injection capping layer can be comprised of a layer of MgO and a layer of a ferromagnetic material.

Abstract: Post-processing steps for integrating of micro devices into system (receiver) substrate or improving the performance of the micro devices after transfer. Post processing steps for additional structures such as reflective layers, fillers, black matrix or other layers may be used to improve the out coupling or confining of the generated LED light. Dielectric and metallic layers may be used to integrate an electro-optical thin film device into the system substrate with transferred micro devices. Color conversion layers may be integrated into the system substrate to create different outputs from the micro devices.

Abstract: Provided is a semiconductor device including a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected town input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.

Abstract: Techniques for forming an odd number of fins by SIT are provided. In one aspect, a method of forming an odd number of fins by SIT includes the steps of: forming a pad layer on a substrate; forming at least one mandrel on the pad layer; forming a first pair of spacers on opposite sides of the mandrel; forming a second pair of spacers on a side of the first pair of spacers opposite the mandrel; removing the first pair of spacers selective to the mandrel and the second pair of spacers; and patterning the odd number of fins in the substrate using a combination of the mandrel and the second pair of spacers as fin masks. A method of forming a finFET device and a fin device structure are also provided.

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. An isolation insulating layer is formed so that the channel layer of the fin structure protrudes from the isolation insulating layer and a part of or an entirety of the oxide layer is embedded in the isolation insulating layer. A gate structure is formed over the fin structure. A recessed portion is formed by etching a part of the fin structure not covered by the gate structure such that the oxide layer is exposed. A recess is formed in the exposed oxide layer. An epitaxial seed layer in the recess in the oxide layer. An epitaxial layer is formed in and above the recessed portion. The epitaxial layer is in contact with the epitaxial seed layer.

Abstract: A method for the fabrication of organic electronic devices includes forming a fluoropolymer layer over a first area of a substrate and a first set of organic electronic devices. The first set of organic electronic devices are pre-fabricated on a second area of the substrate. The method further includes selectively removing the formed fluoropolymer layer from areas within the first area of the substrate by using a liquid solvent. The method further includes subsequent fabrication of organic electronic devices on the substrate.

Abstract: A semiconductor device includes a TSV that penetrates a silicon substrate. A seal ring is provided from a first low relative permittivity film that is closest to the silicon substrate to a second low relative permittivity film that is farthest from the silicon substrate. The seal ring is formed to surround the TSV in bird's eye view on the silicon substrate from a wafer front surface. This achieves suppression of generation or progress of a crack in a low relative permittivity film in a semiconductor device including the low relative permittivity film and a TSV.

Abstract: An integrated circuit includes a first device having a first threshold voltage (Vt) adjusting implant extension region having a first conductivity type and extending from a first implant rail region under an entirety of a first channel region. The first implant rail region and first Vt adjusting implant extension region are contiguous, and the first channel region is over an insulating layer and the insulating layer is over the first implant rail region and first Vt adjusting implant extension region. A second device has a second Vt adjusting implant extension region having the first conductivity type and extending from a second implant rail region under an entirety of a second channel region. The second implant rail region and second Vt adjusting implant extension region are contiguous, and the second channel region is over the insulating layer and the insulating layer is over the second implant rail region and second Vt adjusting implant extension region.

Abstract: Integrated circuits and methods of forming the same are provided herein. In an embodiment, an integrated circuit includes a semiconductor substrate that has an isolated well. A multilayer metallization stack overlies the semiconductor substrate. The multilayer metallization stack includes a metal layer, a functional via, and a dummy metal feature. The metal layer includes a first line in electrical communication with the isolated well through a contact. The functional via is in electrical communication with the first line and the contact. The dummy metal feature is in electrical communication with the functional via.

Abstract: A stacked body including an organic film stacked on and in contact with an inorganic substrate, a wiring pattern, a first resin layer, a light-emitting element layer, and a second resin layer is prepared. The inorganic substrate is detached from the organic film. The stacked body from which the inorganic substrate is detached, an anisotropic conductive layer containing conductive particles having a diameter larger than the thickness of the organic film, and a wiring terminal of a flexible wiring board are disposed on top one another. The stacked body, the anisotropic conductive layer, and the flexible wiring board disposed are thermocompression bonded to cause the conductive particles to enter the organic film, and the wiring pattern and the wiring terminal are electrically connected by means of the conductive particles.

Abstract: A junction-less transistor structure and fabrication method thereof are provided. The method includes providing a semiconductor substrate; and forming an epitaxial layer having a first surface and a second surface on the semiconductor substrate. The method also includes forming a plurality of trenches in the epitaxial layer from the first surface thereof; and forming a gate dielectric layer on side and bottom surfaces of the plurality of trenches. Further, the method includes forming a gate electrode layer on the gate dielectric layer and in the plurality of trenches; and forming an insulation layer on the gate electrode layer. Further, the method also includes forming a drain electrode layer on the first surface of the epitaxial layer; removing the semiconductor substrate; and forming a source electrode layer on the second surface of the epitaxial layer.

Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

Abstract: A lead frame includes a first electrode, a second electrode, two hanger leads, and an outer frame, and partially forms a box-shaped package which has a first recess for mounting a light emitting element as combined with a support member that supports the first electrode and the second electrode. At least a portion of lower faces of the electrodes, at least a portion of lower faces of the hanger leads, and at least a portion of a lower face of the planned formation area for the support member are coplanarly formed. Lower face corners of the first electrode and the second electrode are rounded while upper face corners of the first electrode and the second electrode are not rounded, and upper face corners of the hanger leads are rounded while lower face corners of the hanger leads are not rounded.

Abstract: There is provided a method of reducing stress in a metal film that is highly stressed, the method including: processing the metal film by supplying a metal chloride gas containing a metal of the metal film and a reduction gas for reducing the metal chloride gas onto the metal film; and forming a process film on the metal film to reduce stress in the metal film.

Abstract: A semiconductor device includes a TSV that penetrates a silicon substrate. A seal ring is provided from a first low relative permittivity film that is closest to the silicon substrate to a second low relative permittivity film that is farthest from the silicon substrate. The seal ring is formed to surround the TSV in bird's eye view on the silicon substrate from a wafer front surface. This achieves suppression of generation or progress of a crack in a low relative permittivity film in a semiconductor device including the low relative permittivity film and a TSV.