Patents Examined by Christopher Johnson
  • Patent number: 10962424
    Abstract: The structure of a micro-electro-mechanical system (MEMS) thermal sensor and a method of fabricating the MEMS thermal sensor are disclosed. A method of fabricating a MEMS thermal sensor includes forming first and second sensing electrodes with first and second electrode fingers, respectively, on a substrate and forming a patterned layer with a rectangular cross-section between a pair of the first electrode fingers. The first and second electrode fingers are formed in an interdigitated configuration and suspended above the substrate. The method further includes modifying the patterned layer to have a curved cross-section between the pair of the first electrode fingers, forming a curved sensing element on the modified patterned layer to couple to the pair of the first electrode fingers, and removing the modified patterned layer.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: March 30, 2021
    Inventors: Tsai-Hao Hung, Shih-Chi Kuo
  • Patent number: 10928047
    Abstract: A package for a power supply circuit and an LED illumination module are provided. The package includes: a first package body, configured to package a power device, a control chip and a passive element; an inductive element; a connector configured to connect an electrode of the inductive element to a corresponding electrode of the power device; an encapsulant configured to encapsulate the first package body, the inductive element and the connector; and multiple pins exposed through the encapsulant and configured to achieve external electrical connection. In the package, the control chip, the inductive element and the passive element are packaged together, thereby reducing an area occupied by the drive circuit in the LED illumination module.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: February 23, 2021
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD
    Inventors: Wei Chen, Jian Wei
  • Patent number: 10923499
    Abstract: The present disclosure relates to a semiconductor device having improved structural stability and a method of manufacturing such a semiconductor device. The semiconductor device includes a first stacked structure and a second stacked structure. The semiconductor device further includes a first support including a first upper pillar passing through the second stacked structure and including at least two first lower pillars extending from the first upper pillar and passing through the first stacked structure.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: February 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10916731
    Abstract: An organic light emitting diode (OLED) display device includes an OLED display panel, where a surface of the OLED display panel includes a plurality of pixel display units and a plurality of non-pixel display units; an optical film including an optical film body layer, a black matrix layer, a protective layer, and an adhesive layer which are disposed layer by layer, where the black matrix layer includes a plurality of first black matrix layers and a plurality of second black matrix layers, each of the first black matrix layers is alternated with each of the second black matrix layers.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: February 9, 2021
    Inventor: Chunmei He
  • Patent number: 10886448
    Abstract: A method for producing a lead frame includes press-punching a metal sheet to form the lead frame such that a radius of curvature at a corner of a lower face of each of electrodes is larger than a radius of curvature at a corner of an upper face of each of the electrodes while a radius of curvature at a corner of a lower face of each of hanger leads is smaller than a radius of curvature at a corner of an upper face of each of the hanger leads. The lead frame includes the electrodes, the hanger leads spaced apart from the electrodes, and an outer frame attached to the electrodes and the hanger leads. The lead frame partially defines a box-shaped package that defines a first recess having an opening defining by the support member and a bottom face at least partially formed by the electrodes.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: January 5, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Mayumi Fukuda
  • Patent number: 10879447
    Abstract: A buffer layer can be used to smooth the surface roughness of a galvanic contact layer (e.g., of niobium) in an electronic device, the buffer layer being made of a stack of at least four (e.g., six) layers of a face-centered cubic (FCC) crystal structure material, such as copper, the at least four FCC material layers alternating with at least three layers of a body-centered cubic (BCC) crystal structure material, such as niobium, wherein each of the FCC material layers and BCC material layers is between about five and about ten angstroms thick. The buffer layer can provide the smoothing while still maintaining desirable transport properties of a device in which the buffer layer is used, such as a magnetic Josephson junction, and magnetics of an overlying magnetic layer in the device, thereby permitting for improved magnetic Josephson junctions (MJJs) and thus improved superconducting memory arrays and other devices.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: December 29, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Thomas F. Ambrose, Melissa G. Loving
  • Patent number: 10879422
    Abstract: A light emitting element includes: a first conductivity type semiconductor rod having a plurality of side surfaces arranged to form a polygonal column shape; an active layer formed of a semiconductor and covering the side surfaces; and a second conductive type semiconductor layer covering the active layer. The active layer includes a plurality of well layers respectively disposed over at least two adjacent side surfaces among the plurality of side surfaces. Adjacent well layers among the plurality of well layers are separated from each other along a ridge line where the at least two adjacent side surfaces are in contact with each other. The active layer further includes a ridge portion formed of a semiconductor and disposed on the ridge line, the ridge portion connecting the adjacent well layers. A bandgap of the ridge portion is wider than a bandgap of each of the plurality of well layers.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: December 29, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Atsuo Michiue
  • Patent number: 10879299
    Abstract: A semiconductor device including a semiconductor substrate having a first surface and a second surface that face each other, and having an element region and an isolation region, the element region including a transistor in the first surface, and the isolation region including an element isolation layer surrounding the element region; and a contact plug extending from the first surface to the second surface in the isolation region of the semiconductor substrate.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 29, 2020
    Assignee: SONY CORPORATION
    Inventors: Takashi Yokoyama, Taku Umebayashi
  • Patent number: 10879102
    Abstract: A system for the flux free processing of a plurality of solder balls on a wafer, comprising: an articulable vacuum support chuck for maintaining support of a plurality of solder balls on a wafer being processed. An articulable flux-free binder applicator arranged in binder depositing relationship with the wafer within the treatment chamber. An articulable fluid dispenser is arranged in a binder-applied minimization-treatment with respect to the flux free binder applied to the wafer within the treatment chamber.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: December 29, 2020
    Assignee: Boston Process Technologies, Inc
    Inventor: Jian Zhang
  • Patent number: 10872850
    Abstract: A package structure includes a semiconductor device, a first redistribution line, a dielectric layer, a first conductive bump and a first sealing structure. The dielectric layer is over the first redistribution line and has a first opening therein. The first conductive bump is partially embedded in the first opening and electrically connected to the first redistribution line. The first sealing structure surrounds a bottom portion of the first conductive bump. The first sealing structure has a curved surface extending from an outer surface of the bottom portion of the first conductive bump to a top surface of the dielectric layer.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin
  • Patent number: 10867854
    Abstract: Double plug methods for tone inversion patterning are described. In an embodiment, a method may include receiving the substrate having a multi-line layer formed thereon. Such a method may also include forming a patterned recess in the multi-line layer, the recess defining an inversion pattern on the substrate. The methods may also include depositing a first plug layer in the patterned recess using a first deposition process. Additionally, the methods may include depositing a second plug layer in the patterned recess using a second deposition process, the second deposition process being different from the first deposition process.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: December 15, 2020
    Assignee: Tokyo Electron Limited
    Inventor: Angelique Raley
  • Patent number: 10861977
    Abstract: A device includes a semiconductive substrate, a stop layer over the semiconductive substrate, first and second semiconductive fins over the stop layer, a fin isolation structure between the first and second semiconductive fins, and a spacer at least partially extending along a sidewall of the fin isolation structure. A bottom of the fin isolation structure is lower than a top of the stop layer.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10854447
    Abstract: A film forming method of forming a film on a substrate includes: annealing the substrate; and supplying mist of a raw material solution of the film to a surface of the substrate after the annealing while heating the substrate at a temperature lower than a temperature of the substrate during the annealing.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: December 1, 2020
    Assignee: Denso Corporation
    Inventor: Tatsuji Nagaoka
  • Patent number: 10854629
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. A staircase region having stepped surfaces is formed by patterning the alternating stack. Memory opening fill structures are formed in a memory array region, and support pillar structures are formed in the staircase region. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. The support pillar structures include first support pillar structures and having a first maximum lateral dimension and second support pillar structures having a second maximum lateral dimension that is less than the first maximum lateral dimension and interlaced with the first support pillar structures. The sacrificial material layers are replaced with electrically conductive layers.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: December 1, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chun Ge, Jixin Yu, Fabo Yu, Xin Yuan Li, Yanli Zhang
  • Patent number: 10847571
    Abstract: Post-processing steps for integrating of micro devices into system (receiver) substrate or improving the performance of the micro devices after transfer. Post processing steps for additional structures such as reflective layers, fillers, black matrix or other layers may be used to improve the out coupling or confining of the generated LED light. Dielectric and metallic layers may be used to integrate an electro-optical thin film device into the system substrate with transferred micro devices. Color conversion layers may be integrated into the system substrate to create different outputs from the micro devices.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 24, 2020
    Assignee: VueReal Inc.
    Inventors: Gholamreza Chaji, Ehsanollah Fathi
  • Patent number: 10840247
    Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Bruce B. Doris, Hong He, Rajasekhar Venigalla
  • Patent number: 10840378
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Chang-Yin Chen, Che-Cheng Chang, Yung-Jung Chang
  • Patent number: 10833030
    Abstract: A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be arranged in a circular shape, and a passivation layer may be formed over the landing pad and the mesh holes. An opening is formed through the passivation layer and an underbump metallization is formed in contact with an exposed portion of the landing pad and extends over the mesh holes. By utilizing the mesh holes, sidewall delamination and peeling that might otherwise occur may be reduced or eliminated.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chen-Hua Yu, Tsung-Shu Lin, Wei-Cheng Wu
  • Patent number: 10833265
    Abstract: According to one embodiment, a storage device includes a first conductive layer, a second conductive layer, a resistance-variable layer, between the first conductive layer and the second conductive layer, that includes germanium, antimony, and tellurium, a first layer, between the resistance-variable layer and the first conductive layer, that includes carbon, a second layer, between the resistance-variable layer and the second conductive layer, that includes carbon, a third layer, between the resistance-variable layer and the first layer, that includes at least one of tungsten nitride or tungsten carbide, and a fourth layer, between the resistance-variable layer and the second layer, that includes at least one of tungsten nitride or tungsten carbide.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 10, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Ikeno, Akihiro Kajita, Atsuko Sakata
  • Patent number: 10818771
    Abstract: A plurality of trenches are formed so as to reach a prescribed depth from the surface of an n-type epitaxial layer. A refractory metal carbide film, such as a TaC film is formed via sputtering on the surface of sections (mesa regions) of the n-type epitaxial layer interposed between the adjacent trenches. Sections of the TaC film on the inner walls of the trenches are removed via etching. While the surface of the mesa regions is covered by the TaC film, the inside of the trenches is filled with a p-type epitaxial layer that is grown by CVD, thereby forming a parallel pn structure. Then, sections of the p-type epitaxial layer protruding above the surface of the parallel pn structure and the TaC film above the surface of the mesa regions are ground until top surfaces of n-type regions and p-type regions of the parallel pn structure are exposed.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: October 27, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuyuki Kawada