Patents Examined by Christopher Johnson
  • Patent number: 11903190
    Abstract: A three-dimensional memory device includes an alternating stacks of insulating layers and electrically conductive layers. Memory opening fill structures located in memory openings include a memory film and plural vertical semiconductor channels.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: February 13, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Yukihiro Sakotsubo
  • Patent number: 11903197
    Abstract: A semiconductor device includes gate electrodes and insulating layers spaced apart from each other on a substrate and alternately stacked in a direction perpendicular to an upper surface of the substrate, and channel structures that extend through stack structures. Ones of the structures include a channel insulating layer, a pad layer on the channel insulating layer, and a channel layer. The channel layer includes a first channel region, and a second channel region including a semiconductor material having a length shorter than a length of the first channel region and having an impurity concentration of a first conductivity type and the pad layer includes a semiconductor material doped with a second conductivity type impurity. A height level of a lower surface of the second channel region is lower than a height level of a lower surface of a first erase gate electrode.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: February 13, 2024
    Inventors: Suhwan Lim, Jaehun Jung, Sanghoon Kim, Taehun Kim, Seongchan Lee
  • Patent number: 11895838
    Abstract: A vertical memory device includes a first gate structure on a substrate, the first gate structure including first gate electrodes spaced from each other in a first direction and stacked in a staircase shape, a second gate structure on the first gate structure and including second gate electrodes spaced from each other in the first direction and stacked in the staircase shape, a channel extending through the first and second gate structures, and a contact plug extending in the first direction through the first and second gate structures, wherein second steps at end portions of the second gate electrodes overlap first steps at end portions of the first gate electrodes, and wherein the contact plug extends through at least one of the first steps and through at least one of the second steps, while being electrically connected only to the first steps or to the second steps.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: February 6, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seokcheon Baek
  • Patent number: 11889696
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material-string structures of memory cells extend through the insulative tiers and the conductive tiers. The channel-material-string structures individually comprise an upper portion above and joined with a lower portion. Individual of the channel-material-string structures comprise at least one external jog surface in a vertical cross-section where the upper and lower portions join. Other embodiments, including method are disclosed.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Nancy M. Lomeli
  • Patent number: 11882685
    Abstract: A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: January 23, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 11876019
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: January 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Kim, Sunhom Steve Paak, Heon-Jong Shin, Dong-Ho Cha
  • Patent number: 11862589
    Abstract: A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: January 2, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung Sun Jang, Yeo Hoon Yoon
  • Patent number: 11864384
    Abstract: A nonvolatile memory device includes a mold structure having a stack of word lines on a substrate and first and second string selection lines on the word lines, a first cutting structure through the mold structure, a second cutting structure through the mold structure, the second cutting structure being spaced apart from the first cutting structure, a channel structure penetrating the mold structure to be connected to the substrate, the channel structure being between the first and second cutting structures, a first cutting line cutting through the first string selection line but not through the second string selection line, the first cutting line being between the first and second cutting structures, and a second cutting line cutting through the second string selection line but not through the first string selection line, the second cutting line being between the second cutting structure and the channel structure.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je Suk Moon, Seo-Goo Kang, Young Hwan Son, Kohji Kanamori, Jee Hoon Han
  • Patent number: 11862454
    Abstract: A change in electrical characteristics in a semiconductor device including an oxide semiconductor film is inhibited, and the reliability is improved. The semiconductor device includes a gate electrode, a first insulating film over the gate electrode, an oxide semiconductor film over the first insulating film, a source electrode electrically connected to the oxide semiconductor film, a drain electrode electrically connected to the oxide semiconductor film, a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode, a first metal oxide film over the second insulating film, and a second metal oxide film over the first metal oxide film. The first metal oxide film contains at least one metal element that is the same as a metal element contained in the oxide semiconductor film. The second metal oxide film includes a region where the second metal oxide film and the first metal oxide film are mixed.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: January 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Masami Jintyou
  • Patent number: 11855154
    Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao
  • Patent number: 11856765
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: December 26, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Koichi Matsuno, Masaaki Higashitani, Johann Alsmeier
  • Patent number: 11856773
    Abstract: A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: December 26, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yujin Seo, Euntaek Jung, Byoungil Lee, Seul Lee, Joonhee Lee, Changdae Jung, Bonghyun Choi, Sejie Takaki
  • Patent number: 11855018
    Abstract: A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be arranged in a circular shape, and a passivation layer may be formed over the landing pad and the mesh holes. An opening is formed through the passivation layer and an underbump metallization is formed in contact with an exposed portion of the landing pad and extends over the mesh holes. By utilizing the mesh holes, sidewall delamination and peeling that might otherwise occur may be reduced or eliminated.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chen-Hua Yu, Tsung-Shu Lin, Wei-Cheng Wu
  • Patent number: 11830913
    Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, a doped group III-V semiconductor layer and a gate layer. The first nitride semiconductor layer has a first surface. The second nitride semiconductor layer is formed on the first surface of the first nitride semiconductor layer and has a greater bandgap than that of the first nitride semiconductor layer. The doped group III-V semiconductor layer is over the second nitride semiconductor layer. The doped group III-V semiconductor layer includes a first portion and a second portion having different thicknesses. The gate layer is disposed on the first portion and the second portion of the doped group III-V semiconductor layer.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: November 28, 2023
    Assignee: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.
    Inventor: Anbang Zhang
  • Patent number: 11824147
    Abstract: In an embodiment a component includes a carrier, at least one optoelectronic part arranged on the carrier, the optoelectronic part configured to emit electromagnetic radiation, a frame arranged on the carrier and enclosing a part space, wherein the optoelectronic part is arranged in the part space, and wherein the frame comprises a reflector, and a lens arranged on the frame and at least partially covering an opening of the part space, wherein the reflector is configured to direct the electromagnetic radiation onto the lens, wherein the lens is configured to direct the electromagnetic radiation of the optoelectronic part, and wherein the lens comprises at least a partial pyramidal-shaped section on a first side face facing toward the optoelectronic part.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: November 21, 2023
    Assignee: OSRAM OLED GmbH
    Inventor: Claus Jäger
  • Patent number: 11810878
    Abstract: A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: November 7, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung Sun Jang, Yeo Hoon Yoon
  • Patent number: 11805650
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes the following operations. First, a slit structure and a support structure are formed in a stack structure having interleaved a plurality of sacrificial material layers and a plurality of insulating material layers, the initial support structure between adjacent slit openings of the slit structure. A source structure is formed to include a source portion in each of the slit openings. A pair of first portions of a connection layer is formed in contact with and conductively connected to the source portion. A second portion of the connection layer is formed in contact with and conductively to the pair of first portions of the connection layer.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: October 31, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Wenxiang Xu, Wei Xu, Pan Huang, Ji Xia
  • Patent number: 11804437
    Abstract: A semiconductor device according to an embodiment of the present disclosure may include: a stack structure including a plurality of first conductive patterns and a plurality of dielectric layers, which are alternately stacked, the stack structure having a stepped structure such that any one of the first conductive patterns further protrudes than the first conductive pattern positioned immediately above it; a plurality of second conductive patterns which are respectively formed over protrusions of the first conductive patterns; a plurality of contact plugs which overlap the plurality of second conductive patterns, respectively, and pass through the overlapping second conductive patterns and the stack structure; and a sealing layer pattern which is interposed between the first conductive patterns and the contact plugs and separates the first conductive patterns from the contact plugs.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: October 31, 2023
    Assignee: SK hynix Inc.
    Inventors: Nam-Kuk Kim, Nam-Jae Lee
  • Patent number: 11800712
    Abstract: A semiconductor memory device includes a substrate having a first region, a second region, and a third region main separation regions extending in the first direction and apart from each other in a second direction, first auxiliary separation regions extending in the first direction and spaced apart from each other in the second direction, and second auxiliary separation regions extending in the first direction and spaced apart from each other in the second direction. The first auxiliary separation regions are at a first pitch in the second direction between the main separation regions, the second auxiliary separation regions are disposed at a second pitch, smaller than the first pitch in the second direction between the main separation regions, and the first auxiliary separation regions and the second auxiliary separation regions are shifted from each other in the second direction.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: October 24, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Juyeon Jung, Kwanyong Kim, Haemin Lee, Juyoung Lim, Wonseok Cho
  • Patent number: 11800711
    Abstract: Some embodiments include a method of forming an integrated assembly. Laterally alternating first and second sacrificial materials are formed over a conductive structure, and then a stack of vertically alternating first and second levels is formed over the sacrificial materials. The first levels include first material and the second levels include insulative second material. Channel-material-openings are formed to extend through the stack and through at least some of the strips. Channel-material-pillars are formed within the channel-material-openings. Slits are formed to extend through the stack and through the sacrificial materials. The first sacrificial material is replaced with first conductive material and then the second sacrificial material is replaced with second conductive material. At least some of the first material of the stack is replaced with third conductive material. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Anilkumar Chandolu, Indra V. Chary