Microelectronics package with self-aligned stacked-die assembly

- Qorvo US, Inc.

The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.

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Description

FIELD OF THE DISCLOSURE

The present disclosure relates to a microelectronics package and a process for making the same, and more particularly to a microelectronics package with a self-aligned stacked-die assembly, and a process to achieve self-alignment for the stacked dies in the microelectronics package.

BACKGROUND

With the popularity of portable consumer electronic products, such as smart phones, tablet computers, and so forth, stacked-die assemblies become more and more attractive in microelectronics packages to achieve electronics densification in a small footprint. However, traditional stacked-die assemblies suffer poor alignment between stacked semiconductor dies. Accurate alignment techniques, such as optical alignment, are very expensive and not preferred for low cost products. In addition, the thickness of each stacked semiconductor die may result in a large thickness of the microelectronics package, which may not meet low-profile requirements for modern portable products. Such low profile requirements limit significantly the number of the semiconductor dies that can be stacked.

In the microelectronics package, the stacked semiconductor dies may convey signals to each other by different coupling methods. In a front-end-module (FEM), for instance, an integrated circuit (IC) die may utilize capacitive coupling to transfer signals to a stacked filter die. The capacitive coupling has well defined capacitive coupling coefficients and does not suffer significantly from shifts and misalignments in a stacked-die assembly process. The key requirement for the capacitive coupling is to have electric connections between the stacked semiconductor dies. However, in some cases, like a flip chip die with no through-silicon vias used in the stacked-die assembly, such electric connections may not be available. Consequently, in these cases, magnetic coupling, which does not require electric connections, may be used to transfer signals between non-electrical-connection stacked dies. Herein, the signal transfer function is critically dependent on the precise value of magnetic coupling coefficients, and such precision in the magnetic coupling coefficients impose strict constraints on the stacked-die assembly and the way inductive coupling components are realized in the stacked dies.

In general, the magnetic coupling coefficients have a high degree of variability and depend both on the vertical distance between the inductive coupling components and the horizontal alignment in both X direction and Y-direction dimensions. The misalignment will be significant for a small size inductive coupling component when the horizontal shift is a significant percentage of the diameter of the inductive coupling component. For example, having a 50 μm misalignment is a reasonable value in the stacked-die assembly, but it may be 25% or more of the diameter of the small inductive coupling component. Such horizontal shifts will result in very large magnetic coupling coefficient variations and thus may significantly impact the signal transfer performance. Getting the variability of the magnetic coupling coefficients under control mandates horizontal shifts of 5 to 10 μm, which require expensive and complicated alignment techniques. Further, the distance between the inductive coupling components may also be impacted by the thicknesses of the stacked dies. A large distance between the inductive coupling components may result in lower magnetic coupling coefficients and thus less energy transferred between the stacked dies (more energy lost in the suroundings through escaped magnetic flux).

Accordingly, there remains a need for an improved stacked-die assembly in the microelectronics package, which improves the alignment of stacked dies and enhances the signal transferring performance without expensive and complicated processes. In addition, there is also a need to further reduce the thickness of the final product.

SUMMARY

The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly, and a process for making the same. The disclosed microelectronics package includes a module substrate, a first thinned flip chip die, a second die, and a first mold compound. The first thinned flip chip die includes a first device layer, a first dielectric layer residing over an upper surface of the first device layer, and a number of first interconnects extending from a lower surface of the first device layer to an upper surface of the module substrate. Herein, the first device layer includes a first coupling component embedded therein. The first mold compound resides over the upper surface of the module substrate, surrounds the first thinned flip chip die, and extends above an upper surface of the first thinned flip chip die to define a first opening within the first mold compound and vertically above the first thinned flip chip die. The first mold compound does not reside over the first thinned flip chip die and provides vertical walls of the first opening, which are aligned with edges of the first thinned flip chip die in both X-direction and Y-direction. Herein, the X-direction and the Y-direction are parallel to the upper surface of the module substrate, and the X-direction and the Y-direction are orthogonal to each other. The upper surface of the first thinned flip chip die is exposed at a bottom of the first opening. The second die is stacked with the first thinned flip chip die and in the first opening. The second die includes a second coupling component embedded therein, and the second coupling component is mirrored to the first coupling component.

In one embodiment of the microelectronics package, the second die has at least one of an X-direction dimension and a Y-direction dimension essentially the same as the first thinned flip chip die, such that the second die stacked in the first opening is self-aligned with the first thinned flip chip die.

In one embodiment of the microelectronics package, the second die has both the X-direction dimension and the Y-direction dimension essentially the same as the first thinned flip chip die, such that the second die stacked in the first opening is self-aligned with the first thinned flip chip die.

In one embodiment of the microelectronics package, the first thinned flip chip die and the second die do not have electrical connections.

In one embodiment of the microelectronics package, a distance between the first coupling component and the second coupling component is between 0.1 μm and 100 μm.

In one embodiment of the microelectronics package, the first coupling component and the second coupling component are inductive components, and the first coupling component is magnetically coupled to the second coupling component.

In one embodiment of the microelectronics package, the first coupling component and the second coupling component are photonic components, and the first coupling component is optically coupled to the second coupling component.

In one embodiment of the microelectronics package, the first thinned flip chip die and the second die convey signals to each other by one type of energy from a group consisting of electro-magnetic energy, optical energy, thermal energy, vibration mechanical energy, acoustic wave energy, and X-ray energy.

In one embodiment of the microelectronics package, the first thinned flip chip die is formed from a silicon-on-insulator (SOI) die. The first device layer of the first thinned flip chip die is a silicon epitaxy layer with integrated electronic components of the SOI die, and the first dielectric layer of the first thinned flip chip die is a buried oxide layer of the SOI die.

According to another embodiment, the microelectronics package further includes a second mold compound encapsulating the second die. Herein, the second mold compound is formed from a same or different material as the first mold compound.

In one embodiment of the microelectronics package, the first opening includes a lower region and an upper region that resides over the lower region. The second die resides within the lower region of the first opening, and the second mold compound fills the upper region of the first opening and is in contact with the second die.

In one embodiment of the microelectronics package, the second die extends vertically beyond the first opening. The second mold compound resides over the first mold compound and encapsulates the second die.

In one embodiment of the microelectronics package, an upper surface of the second die and an upper surface of the first mold compound are coplanar. A coating layer is applied over the upper surface of the first mold compound to encapsulate the second die.

In one embodiment of the microelectronics package, the second die is a thinned die that includes a second device layer and a second dielectric layer over the second device layer. The second device layer resides directly over the upper surface of the first thinned flip chip die, and the second coupling component is embedded in the second device layer.

According to another embodiment, the microelectronics package further includes a third die stacked with the first thinned flip chip die and the second die. The first opening includes a lower region and an upper region that resides over the lower region. The second die resides within the lower region of the first opening, and the third die resides over the second die and in the upper region of the first opening.

According to another embodiment, the microelectronics package further includes a third thinned flip chip die and a fourth die. The third thinned flip-chip die includes a second device layer, a second dielectric layer residing over an upper surface of the second device layer, and a number of second interconnects extending from a lower surface of the second device layer to the upper surface of the module substrate. The second device layer includes a third coupling component embedded therein. The first mold compound surrounds the third thinned flip chip die and extends above an upper surface of the third thinned flip chip die to define a second opening within the first mold compound and over the third thinned flip chip die. Herein, the upper surface of the third thinned flip chip die is exposed at a bottom of the second opening. The fourth die is stacked with the third thinned flip chip die and in the second opening. The fourth die includes a fourth coupling component embedded therein, and the fourth coupling component is mirrored to the third coupling component.

According to an exemplary process, a precursor package including a module substrate, a first flip-chip die, and a first mold compound is provided. The first flip chip die is attached to the upper surface of the module substrate, and the first mold compound is over and surrounding the first flip chip die. Herein, the first flip chip die includes a first device layer, a number of first interconnects extending from a lower surface of the first device layer to the upper surface of the module substrate, a first dielectric layer over an upper surface of the first device layer, and a first silicon substrate over the first dielectric layer. The first device layer includes a first coupling component embedded therein. Next, the first mold compound is thinned down to expose a backside of the first silicon substrate of the first flip chip die. The first silicon substrate is then removed substantially to form a first opening within the first mold compound and provide a first thinned flip chip die with an upper surface. The first mold compound provides vertical walls of the first opening, which are aligned with edges of the first thinned flip chip die in both X-direction and Y-direction. Herein, the X-direction and the Y-direction are parallel to the upper surface of the module substrate, and the X-direction and the Y-direction are orthogonal to each other. The upper surface of the first thinned flip chip die is exposed at a bottom of the first opening. After the first opening is formed, a second die is placed in the first opening to stack with the first thinned flip chip die. The second die includes a second coupling component embedded therein, and the second coupling component is mirrored to the first coupling component.

In one embodiment of the exemplary process, the second die has at least one of an X-direction dimension and a Y-direction dimension essentially the same as the first thinned flip chip die, such that the second die stacked in the first opening is self-aligned with the first thinned flip chip die.

In one embodiment of the exemplary process, the second die has both the X-direction dimension and the Y-direction dimension essentially the same as the first thinned flip chip die, such that the second die stacked in the first opening is self-aligned with the first thinned flip chip die.

In one embodiment of the exemplary process, the first thinned flip chip die and the second die do not have electrical connections.

In one embodiment of the exemplary process, the first thinned flip chip die and the second die convey signals to each other by one type of energy from a group consisting of electro-magnetic energy, optical energy, thermal energy, vibration mechanical energy, acoustic wave energy, and X-ray energy.

In one embodiment of the exemplary process, the first flip chip die is formed from a SOI die. The first device layer of the first flip chip die is a silicon epitaxy layer with integrated electronic components of the SOI die, the first dielectric layer of the first flip chip die is a buried oxide layer of the SOI die, and the first silicon substrate of the first flip chip die is a silicon substrate of the SOI die.

According to another embodiment, the exemplary process further includes applying a second mold compound to encapsulate the second die. Herein, the second mold compound is formed from a same or different material as the first mold compound.

In one embodiment of the exemplary process, applying the second mold compound is provided by one of a group consisting of sheet molding, overmolding, compression molding, transfer molding, dam fill encapsulation, and screen print encapsulation.

In one embodiment of the exemplary process, the second mold compound is applied with a molding pressure between 250 psi and 1000 psi. Herein, the second mold compound has a thermal conductivity greater than 2 W/m·K.

In one embodiment of the exemplary process, the second mold compound has a thermal conductivity less than 2 W/m·K.

In one embodiment of the exemplary process, the second die is formed from a laminate structure with at least one hole extending vertically through the second die, such that air elimination is allowed during placement of the second die in the first opening.

In one embodiment of the exemplary process, at least one of an X-direction dimension and a Y-direction dimension of the second die is between 0.5 μm and 10 μm smaller than the first opening, such that air elimination is allowed during placement of the second die in the first opening.

In one embodiment of the exemplary process, the second die is one of a group consisting of an integrated passive device (IPD) die, a low temperature cofired ceramic (LTCC) die, a bulk acoustic wave (BAW) filter die, a surface acoustic wave (SAW) filter die, a film bulk acoustic resonator (FBAR) filter die, and an active integrated circuit (IC) die.

In one embodiment of the exemplary process, the second die includes a second device layer over the upper surface of the first thinned flip chip die, a second dielectric layer over the second device layer, and a second silicon substrate over the second dielectric layer. The second coupling component is embedded in the second device layer.

According to another embodiment, the exemplary process further includes removing substantially the second silicon substrate to release a portion of the first opening and provide a second thinned die with an upper surface. The upper surface of the second thinned die is exposed to the released portion of the first opening.

According to another embodiment, the exemplary process further includes applying a second mold compound to fill the released portion of the first opening and encapsulate the second thinned die.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

FIG. 1 shows an exemplary microelectronics package with one self-aligned die according to one embodiment of the present disclosure.

FIG. 2 shows an alternative microelectronics package with one self-aligned die according to one embodiment of the present disclosure.

FIG. 3 shows an alternative microelectronics package with one self-aligned die according to one embodiment of the present disclosure.

FIG. 4 shows an exemplary microelectronics package with one self-aligned thinned die according to one embodiment of the present disclosure.

FIG. 5 shows an exemplary microelectronics package with one self-aligned die for optical energy transferring according to one embodiment of the present disclosure.

FIG. 6 shows an exemplary microelectronics package with multiple self-aligned dies according to one embodiment of the present disclosure.

FIG. 7 shows an alternative microelectronics package with multiple self-aligned dies according to one embodiment of the present disclosure.

FIG. 8 shows an alternative microelectronics package with multiple self-aligned dies according to one embodiment of the present disclosure.

FIG. 9 shows an exemplary microelectronics package with multiple sets of self-aligned dies according to one embodiment of the present disclosure.

FIGS. 10A-10F provide exemplary steps that illustrate a process to fabricate the exemplary microelectronics package shown in FIG. 1.

FIGS. 11A-11G provide exemplary steps that illustrate a process to fabricate the exemplary microelectronics package shown in FIG. 4.

It will be understood that for clear illustrations, FIGS. 1-11G may not be drawn to scale.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly, and a process for making the same. FIG. 1 provides an exemplary microelectronics package 10 according to one embodiment of the present disclosure. For the purpose of this illustration, the exemplary microelectronics package 10 includes a module substrate 12, a thinned flip chip die 14, a second die 16, an underfilling layer 18, a first mold compound 20, and a second mold compound 22.

In detail, the module substrate 12 may be formed from a laminate, a wafer level fan out (WLFO) carrier, a lead frame, a ceramic carrier, or the like. The first thinned flip chip die 14 includes a first device layer 24, a number of first interconnects 26 (only one interconnect is labeled with a reference number for clarity) extending from a lower surface of the first device layer 24 and coupled to an upper surface of the module substrate 12, a first dielectric layer 28 over an upper surface of the first device layer 22, and essentially no silicon substrate over the first dielectric layer 28. Herein, essentially no silicon substrate over the first dielectric layer 28 refers to at most 0.25 μm silicon substrate (not shown) over the first dielectric layer 28. In some applications, the first thinned flip chip die 14 does not include any silicon substrate, such that an upper surface of the first thinned flip chip die 14 is an upper surface of the first dielectric layer 28. For other cases, the upper surface of the first thinned flip chip die 14 is an upper surface of the thin silicon substrate.

The first device layer 24 with a thickness between 0.1 μm and 50 μm may be formed of silicon, silicon oxide, gallium arsenide, gallium nitride, silicon germanium, or the like. A first inductive component 30 (such as inductor, transformer, transmission line, and coupler) is embedded within the first device layer 24. In different applications, there may be multiple inductive components included in the first device layer 24. The first interconnects 26 with a height between 5 μm and 200 μm may be copper pillar bumps, solder ball bumps, or the like. The first dielectric layer 28 with a thickness between 10 nm and 10000 nm may be formed of silicon oxide, silicon nitride, or aluminum nitride.

In one embodiment, the first thinned flip chip die 14 may be formed from a silicon-on-insulator (SOI) die, which refers to a die including a silicon substrate, a silicon epitaxy layer with integrated electronic components, and a buried oxide layer sandwiched between the silicon substrate and the silicon epitaxy layer. The first device layer 24 of the first thinned flip chip die 14 is the silicon epitaxy layer with the integrated electronic components of the SOI die. The first dielectric layer 28 of the first thinned flip chip die 14 is the buried oxide (BOX) layer of the SOI die. In addition, the silicon substrate of the SOI die is removed substantially to complete the first thinned flip chip die 14 (more details in the following discussion). In addition, the first thinned flip chip die 14 may also be formed from a silicon on sapphire (SOS) die, an integrated passive device (IPD) die, or an acoustic die, any of which has a device layer, a semiconductor substrate, and a stopping layer sandwiched between the device layer and the semiconductor substrate. The stopping layer may be formed of oxide or polymer and used as an etching stop to protect the device layer during an elimination process of the semiconductor substrate.

The underfilling layer 18 resides over the upper surface of the module substrate 12, such that the underfilling layer 18 encapsulates the first interconnects 26 and underfills the first thinned flip chip die 14 between the lower surface of the first device layer 24 and the upper surface of the module substrate 12. The underfilling layer 18 may be formed from conventional polymeric compounds, which serve to mitigate the stress effects caused by Coefficient of Thermal Expansion (CTE) mismatch between the first thinned flip chip die 14 and the module substrate 12.

The first mold compound 20 resides over the underfilling layer 18, surrounds the first thinned flip chip die 14, and extends above the upper surface of the first thinned flip chip die 14 to define a first opening 32 within the first mold compound 20 and vertically above the upper surface of the first thinned flip chip die 14. The first mold compound 20 does not reside over the first thinned flip chip die 14 and provides vertical walls of the first opening 32 in Z-direction. The vertical walls of the first opening 32 are well aligned with edges of the first thinned flip chip die 14 in both X-direction and Y-direction. Herein, the X-direction and the Y-direction are parallel to the upper surface of the module substrate 12, and the Z-direction is perpendicular to the upper surface of the module substrate 12. The X-direction, the Y-direction, and the Z-direction are all orthogonal to each other.

The first opening 32 includes a lower region LR and an upper region UR that resides over the lower region LR, and the upper surface of the first thinned flip chip die 14 is exposed to the lower region LR of the first opening 32. The first mold compound 20 may be formed from a same or different material as the underfilling layer 18. When the first mold compound 20 and the underfilling layer 18 are formed from a same material, the first mold compound 20 and the underfilling layer 18 may be formed simultaneously. One exemplary material used to form the first mold compound 20 is an organic epoxy resin system.

The second die 16 with a second inductive component 34 (such as inductor, transformer, transmission line, and coupler) is stacked with the first thinned flip chip die 14 and in the first opening 32. Herein, no electrical contact may be realized at the upper surface of the first thinned flip chip die 14 and all electrical contacts (not shown) are on the lower surface of the first device layer 24 where the first interconnects 26 extend from. As such, the first thinned flip chip die 14 and the second die 16 do not have electrical connections, and the first thinned flip chip die 14 and the second die 16 may convey signals to each other by magnetic coupling, which does not require such electrical connections. In this embodiment, the second inductive component 34 embedded in the second die 16 and the first inductive component 30 in the first thinned flip chip die 14 are magnetically coupled and used to transfer signals between the first thinned flip chip die 14 and the second die 16. The first thinned flip chip die 14 may be an active integrated circuit (IC) die, such as a switch IC die and a low noise amplifier (LNA) IC die. The second die 16 may be an IPD die, a low temperature cofired ceramic (LTCC) die, a bulk acoustic wave (BAW) filter die, a surface acoustic wave (SAW) filter die, a film bulk acoustic resonator (FBAR) filter die, and another active IC die.

The second die 16 has at least one of an X-direction dimension and a Y-direction dimension essentially the same as the first thinned flip chip die 14. Herein and hereinafter, an X-direction dimension refers to a largest dimension in the X-direction (between 100 μm to 1 mm or even larger), and a Y-direction dimension refers to a largest dimension in the Y-direction (between 100 μm to 1 mm or even larger). Further, essentially the same refers to between 95% and 100%. In detail, the X-direction dimension of the second die 16 may be between 95% and 100% of the X-direction dimension of the first thinned flip chip die 14, while the Y-direction dimension of the second die 16 may be smaller than the Y-direction dimension of the first thinned flip chip die 14. Alternatively, the Y-direction dimension of the second die 16 may be between 95% and 100% of the Y-direction dimension of the first thinned flip chip die 14, while the X-direction dimension of the second die 16 is smaller than the X-direction dimension of the first thinned flip chip die 14. In addition, the X-direction dimension of the second die 16 may be between 95% and 100% of the X-direction dimension of the first thinned flip chip die 14, and the Y-direction dimension of the second die 16 may be between 95% and 100% of the Y-direction dimension of the first thinned flip chip die 14. Consequently, at least one of the X-direction dimension and the Y-direction dimension of the second die 16 matches the first opening 32.

Notice that the first opening 32 is vertically over the first thinned flip chip die 14, and the first mold compound 20 provides the vertical walls of the first opening 32, which are well aligned with the edges of the first thinned flip chip die 14 in both the X-direction and the Y-direction. As such, the second die 16 stacked in the first opening 32 will be self-aligned with the first thinned flip chip die 14 due to the vertical walls of the first opening 32 provided by the first mold compound 20.

The precise alignment between the first flip chip die 14 and the second die 16 allows that the first inductive component 30 embedded in the first thinned flip chip die 14 is accurately mirrored to the second inductive component 34 embedded in the second die 16, and thus ensures stable magnetic coupling coefficients between the first inductive component 30 and the second inductive component 34 without an obvious variability. Consequently, this ensures a stable energy transfer between the magnetically coupled first and second inductive components 30 and 34. In addition, the stacked configuration of the first flip chip die 14 and the second die 16 significantly reduces the footprint of the microelectronics package 10, while the thinness of the first thinned flip chip die 14 preserves a low profile of the microelectronics package 10. Furthermore, the thinness of the first thinned flip chip die 14 allows a short distance between the first inductive component 30 and the second inductive component 34 between 0.1 μm and 100 μm, and consequently leads to high magnetic coupling coefficients.

In this embodiment, the second die 16 resides within the lower region LR of the first opening 32, and the second mold compound 22 fills the upper region UR of the first opening 32, is in contact with the second die 16, and encapsulates the second die 16. The second mold compound 22 may be formed of thermoplastics or thermoset materials with a thermal conductivity greater than 2 W/m·K, such as poly phenyl sulfide (PPS), overmold epoxies doped with boron nitride or alumina thermal additives, or the like. In general, the higher the thermal conductivity of the second mold compound 22, the better the thermal performance of the second die 16. In some applications, if the second die 16 is a low heat-generation die (such as a low-power filter die, a low-power capacitor die, or a MEMS die), the second mold compound 22 may also be formed from an organic epoxy resin system with a thermal conductivity less than 2 W/m·K. The second mold compound 22 may be formed of the same or different material as the first mold compound 20. Herein, a portion of the second mold compound 22 may reside over a top surface of the first mold compound 20.

In another embodiment, the second die 16 may be taller than the first opening 32 as illustrated in FIG. 2. The second die 16 is stacked with the first thinned flip chip die 14 and extends vertically beyond the first opening 32. The second mold compound 22 may reside over the first mold compound 20 and encapsulates the second die 16. Herein, the second mold compound 22 may be formed by a low compression molding process to prevent physical damage of the second die 16.

Further, as shown in FIG. 3, an upper surface of the second die 16 and the upper surface of the first mold compound 20 are coplanar. A coating layer 36, instead of the second mold compound 22, may be applied over the upper surface of the first mold compound 20 to encapsulate the second die 16. The coating layer 36 may be formed of a same material as the underfilling layer 18, such as a sealing polymer, or may be formed of a thermal polymer or any other suitable material. In some applications, the microelectronics package 10 may not include the coating layer 36 or the second mold compound 22 to encapsulate the second die 16 (not shown). The upper surface of the second die 16 is exposed.

In one embodiment, a second thinned die 16T, instead of the second die 16, is stacked with the first thinned flip chip die 14, as illustrated in FIG. 4. The second thinned die 16T has a second device layer 38 directly over the upper surface of the first thinned flip chip die 14, a second dielectric layer 40 over the second device layer 38, and essentially no silicon substrate over the second dielectric layer 40. Herein, essentially no silicon substrate over the second dielectric layer 40 refers to at most 0.25 μm silicon substrate (not shown) over the second dielectric layer 40. In desired cases, the second thinned die 16T does not include any silicon substrate over the second dielectric layer 40, such that a top surface of the second thinned die 16T is a top surface of the second dielectric layer 40. For other cases, the top surface of the second thinned die 16T may be a top surface of the thin silicon substrate.

The second device layer 38 with a thickness between 0.1 μm and 50 μm may be formed of silicon, silicon oxide, gallium arsenide, gallium nitride, silicon germanium, or the like. Herein, the second inductive component 34 is embedded in the second device layer 38. The second dielectric layer 40 with a thickness between 10 nm and 10000 nm may be formed of silicon oxide, silicon nitride, or aluminum nitride. In one embodiment, the second thinned die 16T may be formed from an SOI die, an SOS die, an IPD die, or an acoustic die, any of which has a device layer, a semiconductor substrate and a stopping layer sandwiched between the device layer and the semiconductor substrate. The stopping layer may be formed of oxide or polymer and used as an etching stop to protect the device layer during an elimination process of the semiconductor substrate. For instance, the second device layer 38 of the second thinned die 16T is a silicon epitaxy layer with integrated electronic components of the SOI die. The second dielectric layer 40 of the second thinned die 16T is a BOX layer of the SOI die. In addition, a silicon substrate of the SOI die is removed substantially to complete the second thinned die 16T (more details in the following discussion).

It will be clear to those skilled in the art that other coupling components, such as photonic components, capacitive coupled components, magnetically coupled components, and coupled vibrational sensors, may also be used to transfer different types of signal energies, such as electro-magnetic energy, optical energy, thermal energy, vibration mechanical energy, acoustic wave energy, and X-ray energy. As shown in FIG. 5, a number of first photonic components 42 (photo detectors/emitters), instead of the first inductive component 30, are embedded in the first device layer 24 of the first thinned flip chip die 14, and a number of second photonic components 44 (photo emitters/detectors) instead of the second inductive component 34 are embedded in the second die 16. Each first photonic component 42 is mirrored to a corresponding second photonic component 44. Herein, the first thinned flip chip die 14 and the second die 16 do not have electrical connections, and the first thinned flip chip die 14 and the second die 16 convey signals to each other by transferring optical energy.

In some applications, the microelectronics package 10 may include multiple dies stacked with the first thinned flip chip die 14, as illustrated in FIGS. 6-8. In FIG. 6, the microelectronics package 10 includes the second die 16 and a third die 46 over the second die 16, both of which are stacked with the first thinned flip chip die 14. Herein, the second die 16 is fully within the first opening 32, and at least a portion of the third die 46 is in the first opening 32. The second mold compound 22 is in contact with and encapsulates the third die 46.

The third die 46 may have at least one of an X-direction dimension and a Y-direction dimension essentially the same as the first thinned flip chip die 14. Herein, essentially the same refers to between 95% and 100%. In detail, the X-direction dimension of the third die 46 may be between 95% and 100% of the X-direction dimension of the first thinned flip chip die 14, while the Y-direction dimension of the third die 46 may be smaller than the Y-direction dimension of the first thinned flip chip die 14. Alternatively, the Y-direction dimension of the third die 46 may be between 95% and 100% of the Y-direction dimension of the first thinned flip chip die 14, while the X-direction dimension of the third die 46 is smaller than the X-direction dimension of the first thinned flip chip die 14. In addition, the X-direction dimension of the third die 46 may be between 95% and 100% of the X-direction dimension of the first thinned flip chip die 14, and the Y-direction dimension of the third die 46 may be between 95% and 100% of the Y-direction dimension of the first thinned flip chip die 14. Consequently, at least one of the X-direction dimension and the Y-direction dimension of the third die 46 matches the first opening 32.

Notice that the first opening 32 is vertically over the first thinned flip chip die 14, and the first mold compound 20 provides the vertical walls of the first opening 32, which are well aligned with the edges of the first thinned flip chip die 14 in both the X-direction and the Y-direction. As such, the third die 46 stacked in the first opening 32 will be self-aligned with the first thinned flip chip die 14 due to the vertical walls of the first opening 32 provided by the first mold compound 20. Herein, the third die 46 and the second die 16 may have different dimensions in the X-direction, the Y-direction, and/or the Z direction, respectively.

As shown in FIG. 7, the second thinned die 16T and a third thinned die 46T are stacked with the first thinned flip chip die 14. The third thinned die 46T has a third device layer 48 directly over the upper surface of the second thinned die 16T, a third dielectric layer 50 over the third device layer 48, and essentially no silicon substrate over the third dielectric layer 50. Herein, essentially no silicon substrate over the third dielectric layer 50 refers to at most 0.25 μm silicon substrate (not shown) over the third dielectric layer 50. In desired cases, the third thinned die 46T does not include any silicon substrate over the third dielectric layer 50, such that a top surface of the third thinned die 46T is a top surface of the third dielectric layer 50. The third thinned die 46T may be formed from an SOI die, an SOS die, an IPD die, or an acoustic die. For instance, the third device layer 48 of the third thinned die 46T is a silicon epitaxy layer with integrated electronic components of the SOI die. The third dielectric layer 50 of the third thinned die 46T is a BOX layer of the SOI die. In addition, a silicon substrate of the SOI die is removed substantially to complete the third thinned die 46T.

Furthermore, the microelectronics package 10 may include the second die 16 and the third thinned die 46T stacked with the first thinned flip chip die 14, as illustrated in FIG. 8. And in some applications, the microelectronics package 10 may include the second thinned die 16T and the third die 46 stacked with the first thinned flip chip die 14 (not shown).

FIG. 9 shows that the microelectronics package 10 may include multiple sets of stacked dies attached to the module substrates 12. Besides the first thinned flip chip die 14 and the second die 16, the microelectronics package 10 also includes a fourth thinned flip chip die 52 and a fifth die 54. The fourth thinned flip chip die 52 includes a fourth device layer 56, a number of fourth interconnects 58 (only one interconnect is labeled with a reference number for clarity) extending from a lower surface of the fourth device layer 56 and coupled to the upper surface of the module substrate 12, a fourth dielectric layer 60 over an upper surface of the fourth device layer 56, and essentially no silicon substrate over the fourth dielectric layer 60. Herein, essentially no silicon substrate over the fourth dielectric layer 60 refers to at most 0.25 μm silicon substrate (not shown) over the fourth dielectric layer 60. In some applications, the fourth thinned flip chip die 52 does not include any silicon substrate, such that an upper surface of the fourth thinned flip chip die 52 is an upper surface of the fourth dielectric layer 60.

The fourth device layer 56 with a thickness between 0.1 μm and 50 μm may be formed of silicon, silicon oxide, gallium arsenide, gallium nitride, silicon germanium, or the like. A third inductive component 62 (such as inductor, transmission line, and coupler) is embedded within the fourth device layer 56. In different applications, there may be multiple inductive components included in the fourth device layer 56. The fourth interconnects 58 with a height between 5 μm and 200 μm may be copper pillar bumps, solder ball bumps, or the like. The fourth dielectric layer 60 with a thickness between 10 nm and 10000 nm may be formed of silicon oxide, silicon nitride, or aluminum nitride.

Similar to the first thinned flip chip die 14, the fourth thinned flip chip die 52 may be formed from an SOI die, an SOS die, an IPD die, or an acoustic die. The underfilling layer 18 encapsulates the fourth interconnects 58 and underfills the fourth thinned flip chip die 52 between the lower surface of the fourth device layer 56 and the upper surface of the module substrate 12. The first mold compound 20 also surrounds the fourth thinned flip chip die 52, and extends above the upper surface of the fourth thinned flip chip die 52 to define a second opening 64 within the first mold compound 20 and vertically above the upper surface of the fourth thinned flip chip die 52. Herein, the first mold compound 20 does not reside over the fourth thinned flip chip die 52 and provides vertical walls of the second opening 64 in the Z-direction. The vertical walls of the second opening 64 are well aligned with edges of the fourth thinned flip chip die 52 in both the X-direction and the Y-direction.

The fifth die 54 with a fourth inductive component 66 (such as inductor, transmission line, and coupler) is stacked with the fourth thinned flip chip die 52 and in the second opening 64. Herein, the fourth thinned flip chip die 52 and the fifth die 54 do not have electrical connections, and the fourth thinned flip chip die 52 and the fifth die 54 may convey signals to each other by magnetic coupling, which does not require such electrical connections. In this embodiment, the fourth inductive component 66 embedded in the fifth die 54 and the third inductive component 62 embedded in the fourth thinned flip chip die 52 are magnetically coupled and used to transfer signals between the fourth thinned flip chip die 52 and the fifth die 54.

The fifth die 54 has at least one of an X-direction dimension and a Y-direction dimension essentially the same as the fourth thinned flip chip die 52. Herein, essentially the same refers to between 95% and 100%. In detail, the X-direction dimension of the fifth die 54 may be between 95% and 100% of the X-direction dimension of the fourth thinned flip chip die 52, while the Y-direction dimension of the fifth die 54 may be smaller than the Y-direction dimension of the fourth thinned flip chip die 52. Alternatively, the Y-direction dimension of the fifth die 54 may be between 95% and 100% of the Y-direction dimension of the fourth thinned flip chip die 52, while the X-direction dimension of the fifth die 54 is smaller than the X-direction dimension of the fourth thinned flip chip die 52. In addition, the X-direction dimension of the fifth die 54 may be between 95% and 100% of the X-direction dimension of the fourth thinned flip chip die 52, and the Y-direction dimension of the fifth die 54 may be between 95% and 100% of the Y-direction dimension of the fourth thinned flip chip die 52. Consequently, at least one of the X-direction dimension and the Y-direction dimension of the fifth die 54 matches the second opening 64.

Notice that the first opening 32 is vertically over the first thinned flip chip die 14, and the first mold compound 20 provides the vertical walls of the second opening 64, which are well aligned with edges of the fourth thinned flip chip die 52 in both the X-direction and the Y-direction. As such, the fifth die 54 stacked in the second opening 64 will be self-aligned with the fourth thinned flip chip die 52 due to the vertical walls of the second opening 64 provided by the first mold compound 20. The precise alignment between the fourth flip chip die 52 and the fifth die 54 allows that the third inductive component 62 embedded in the fourth thinned flip chip die 52 is accurately mirrored to the fourth inductive component 66 embedded in the fifth die 54, and thus ensures stable magnetic coupling coefficients between the third inductive component 62 and the fourth inductive component 66 without an obvious variability. A distance between the third inductive component 62 and the fourth inductive component 66 is between 0.1 μm and 100 μm. In addition, the second mold compound 22 is in contact with and encapsulates the fifth die 54.

FIGS. 10A-10F provide exemplary steps to fabricate the exemplary wafer-level package 10 shown in FIG. 1. Although the exemplary steps are illustrated in a series, the exemplary steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in FIGS. 10A-10F.

Initially, a precursor package 68 is provided as depicted in FIG. 10A. For the purpose of this illustration, the precursor package 68 includes the module substrate 12, a first flip chip die 14F, the underfilling layer 18, and the first mold compound 20. In different applications, the precursor package 68 may include multiple flip chip dies. In detail, the first flip chip die 14F includes the first device layer 24, the first interconnects 26 extending from the lower surface of the first device layer 24 to the upper surface of the module substrate 12, the first dielectric layer 28 over the upper surface of the first device layer 24, and a first silicon substrate 70 over the first dielectric layer 28. As such, the backside of the first silicon substrate 70 is an upper surface of the first flip chip die 14F. In addition, the underfilling layer 18 resides over the upper surface of the module substrate 12, such that the underfilling layer 16 encapsulates the first interconnects 26 and underfills the first flip chip die 14F between the lower surface of the first device layer 24 and the upper surface of the module substrate 12. The first mold compound 20 resides over the underfilling layer 18 and encapsulates the first flip chip die 14F. The first mold compound 20 may be used as an etchant barrier to protect the first flip chip die 14F against etching chemistries such as Tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), sodium hydroxide (NaOH), and acetylcholine (ACH) in the following steps.

Next, the first mold compound 20 is thinned down to expose the backside of the first silicon substrate 70 of the first flip chip die 14F, as shown in FIG. 10B. The thinning procedure may be done with a mechanical grinding process. The following step is to remove substantially the first silicon substrate 70 of the first flip chip die 14F to create the first opening 32 and provide the first thinned flip chip die 14 with the upper surface exposed to the first opening 32, as shown in FIG. 10C. Herein, removing substantially the first silicon substrate 70 refers to removing at least 99% of the entire first silicon substrate 70, and perhaps a portion of the first dielectric layer 28. In desired cases, the first silicon substrate 70 is fully removed. As such, the first thinned flip chip die 14 may refer to a thinned die including the first device layer 24, the first interconnects 26 extending from the lower surface of the first device layer 24 and coupled to the module substrate 12, and the first dielectric layer 28 over the upper surface of the first device layer 24, where the upper surface of the first dielectric layer 28 is the upper surface of the first thinned flip chip die 14. Removing substantially the first silicon substrate 70 may be provided by an etching process with a wet/dry etchant chemistry, which may be TMAH, KOH, ACH, NaOH, or the like.

Since the first opening 32 is formed by removing the first silicon substrate 70 from the first flip chip die 14F, the first opening is the same size as the removed first silicon substrate 70 and consequently has the same X-direction dimension and the same Y-direction dimension as the thinned flip chip die 14. Herein, the first mold compound 20 surrounding the thinned flip chip die 14 provides vertical walls of the first opening 32, which are aligned with edges of the first thinned flip chip die 14 in both the X-direction and the Y-direction.

In this embodiment, the first opening 32 includes the lower region LR and the upper region UR that resides over the lower region LR, and the upper surface of the first thinned flip chip die 14 is exposed to the lower region LR of the first opening 32. The second die 16 is then placed within the lower region LR of the first opening 32 and stacked with the first thinned flip chip die 14, as illustrated in FIG. 10D. Herein, the first thinned flip chip die 14 and the second die 16 do not have electrical connections, and the first thinned flip chip die 14 and the second die 16 may convey signals to each other by magnetic coupling, which does not require electrical connections. Once the second die 16 has at least one of the X-direction dimension and the Y-direction dimension essentially the same as the first thinned flip chip die 14, at least one of the X-direction dimension and the Y-direction dimension of the second die 16 will match the first opening 32 that is surrounded by the first mold compound 20. Consequently, the second die 16 stacked in the first opening 32 is self-aligned with the first thinned flip chip die 14, which allows the first inductive component 30 embedded in the first thinned flip chip die 14 to be accurately mirrored to the second inductive component 34 embedded in the second die 16 and thus ensures a stable magnetic coupling coefficient between the first inductive component 30 and the second inductive component 34. In some cases, both the X-direction dimension and the Y-direction dimension of the second die 16 are essentially the same as the X-direction dimension and the Y-direction dimension of the first thinned flip chip die 14, respectively, such that both the X-direction dimension and the Y-direction dimension of the second die 16 match the first opening 32.

When placing the second die 16 in the first opening 32, the air between the second die 16 and the first thinned flip chip die 14 needs to be evacuated. If the second die 16 is formed from a laminate structure, one or more holes (not shown) may be formed vertically through the second die 16 to allow for air elimination. If the second die 16 is an IPD/LTCC/BAW filter/SAW filter/FBAR filter/active IC die, at least one of the X-direction dimension and the Y-direction dimension of the second die 16 may be 0.5-10 μm smaller than the first opening 32 to allow for air elimination without a significant inaccuracy in the self-aligned assembly. Further, the X-direction dimension and the Y-direction dimension of the second die 16 0.5-10 μm smaller than the first opening 32 may ensure a smooth placement of the second die 16 in the first opening 32. In some applications, there may be additional dies (not shown) placed in the first opening 32 and stacked with the first thinned flip chip die 14 and the second die 16.

In this embodiment, after the second die 16 is placed in the lower region LR of the first opening 32, the second mold compound 22 is applied to substantially fill the upper region UR of the first opening 32 and encapsulate the second die 16, as depicted in FIG. 10E. Herein, substantially filling the upper region UR refers to filling at least 75% of the upper region UR. The second mold compound 22 directly resides over the upper surface of the second die 16 and may further reside over the first mold compound 20. The second mold compound 22 may be applied by various procedures, such as sheet molding, overmolding, compression molding, transfer molding, dam fill encapsulation, and screen print encapsulation.

In one embodiment, if the second die 16 is a high heat-generation die, the second mold compound 22 may be formed of thermoplastics or thermoset materials with a thermal conductivity greater than 2 W/m·K for superior heat dissipation. A typical molding pressure, between 250 psi and 1000 psi, may be used for applying the second mold compound 22. If the second die 16 is a low heat-generation die, the second mold compound 22 directly residing over the second die 16 is not required to have a high thermal conductivity. As such, the second mold compound 22 may be formed from an organic epoxy resin system with a thermal conductivity less than 2 W/m·K. A low molding pressure, as low as 100 psi, may be used for applying the second mold compound 22. The second mold compound 22 may be formed of the same or different material as the first mold compound 20. With the same material, the second mold compound 22 and the first mold compound 20 may have the same expansion/compression coefficients over temperature, which is desired in some applications.

A curing process (not shown) is followed to harden the second mold compound 22. The curing temperature is between 100° C. and 320° C. depending on which material is used as the second mold compound 22. Finally, an upper surface of the second compound component 22 is planarized to form the microelectronic package 10 as depicted in FIG. 10F. A mechanical grinding process may be used for planarization. The upper portion of the second mold compound 22 may reside over the first mold compound 20.

FIGS. 11A-11G provide exemplary steps to fabricate the exemplary wafer-level package 10 shown in FIG. 4. Although the exemplary steps are illustrated in a series, the exemplary steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in FIGS. 11A-11G.

FIGS. 11A-11C show a same process to form the first thinned flip chip die 14 and the first opening 32 surrounded by the first mold compound 20 as FIGS. 10A-10C. Herein, the first opening 32 is vertically above the first thinned flip chip die 14, and the vertical walls of the first opening 32 provided by the first mold compound 20 are aligned with edges of the first thinned flip chip die 14 in both the X-direction dimension and the Y-direction dimension.

Next, a second intact die 16D is placed in the first opening 32 and stacked with the first thinned flip chip die 14, as illustrated in FIG. 11D. The second intact die 16D includes the second device layer 38 with the embedded second inductive component 34, the second dielectric layer 40 over the second device layer 38, and a second silicon substrate 72 over the second dielectric layer 40. As such, the backside of the second silicon substrate 72 is an upper surface of the second intact die 16D. In some applications, the second silicon substrate 72 may extend above the first opening 32. Herein, the second intact die 16D has at least one of an X-direction dimension and a Y-direction dimension essentially the same as the first thinned flip chip die 14, such that at least one of the X-direction dimension and the Y-direction dimension of the second intact die 16D matches the first opening 32 surrounded by the first mold compound 20. Consequently, the second intact die 16D stacked in the first opening 32 is self-aligned with the first thinned flip chip die 14, which allows the first inductive component 30 embedded in the first thinned flip chip die 14 to be accurately mirrored to the second inductive component 34 embedded in the second intact die 16D and thus ensures a stable magnetic coupling coefficient between the first inductive component 30 and the second inductive component 34. In some cases, both the X-direction dimension and Y-direction dimension of the second intact die 16D are essentially the same as the X-direction dimension and Y-direction dimension of the first thinned flip chip die 14, respectively, such that both the X-direction dimension and the Y-direction dimension of the second intact die 16D match the first opening 32. During the placement of the second intact die 16D in the first opening 32, the air between the second intact die 16D and the first thinned flip chip die 14 needs to be evacuated.

After the second intact die 16D is placed in the first opening 32, the second silicon substrate 72 is then removed substantially to release a portion of the first opening 32 and provide the second thinned die 16T, as illustrated in FIG. 11E. Removing substantially the second silicon substrate 72 may be provided by an etching process with a wet/dry etchant chemistry, which may be TMAH, KOH, ACH, NaOH, or the like. Herein, removing substantially the second silicon substrate 72 refers to removing at least 99% of the entire second silicon substrate 72, and perhaps a portion of the second dielectric layer 40. In desired cases, the second silicon substrate 72 is fully removed. As such, the second thinned die 16T may refer to a thinned die including the second device layer 38 and the second dielectric layer 40 over the second device layer 30, where the upper surface of the second dielectric layer 40 is the upper surface of the second thinned die 16T. The thinned second die 16T remains aligned with the first thinned flip chip die 14, and the upper surface of the second thinned die 16T is exposed in the first opening 32. In some applications, there may be additional dies (not shown) placed in the released portion of the first opening 32 and stacked with the first thinned flip chip die 14 and the second thinned die 16T.

In this embodiment, after the second thinned die 16T is formed, the second mold compound 22 is applied to substantially fill the released portion of the first opening 32 and encapsulate the thinned second die 16T, as depicted in FIG. 11F. Herein, substantially filling the released portion of the first opening 32 refers to filling at least 75% of the released portion of the first opening 32. The second mold compound 22 directly resides over the upper surface of the second thinned die 16T and may further reside over the first mold compound 20. In general, the higher the thermal conductivity of the second mold compound 22, the better the thermal performance of the second thinned die 16T.

A curing process (not shown) is followed to harden the second mold compound 22. The curing temperature is between 100° C. and 320° C. depending on which material is used as the second mold compound 22. Finally, an upper surface of the second compound component 22 is planarized to form the microelectronic package 10 as depicted in FIG. 11G. A mechanical grinding process may be used for planarization. The upper portion of the second mold compound 22 may reside over the first mold compound 20.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

1. A method comprising:

providing a precursor package including a module substrate, a first flip chip die attached to an upper surface of the module substrate, and a first mold compound over and surrounding the first flip chip die, wherein: the first flip chip die comprises a first device layer, a plurality of first interconnects extending from a lower surface of the first device layer to the upper surface of the module substrate, a first dielectric layer over an upper surface of the first device layer, and a first silicon substrate over the first dielectric layer; and the first device layer includes a first coupling component that is embedded in the first device layer;
thinning down the first mold compound to expose a backside of the first silicon substrate of the first flip chip die;
removing substantially the first silicon substrate to form a first opening within the first mold compound and provide a first thinned flip chip die with an upper surface, wherein: the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first thinned flip chip die in both X-direction and Y-direction; the X-direction and the Y-direction are parallel to the upper surface of the module substrate, and the X-direction and the Y-direction are orthogonal to each other; and the upper surface of the first thinned flip chip die is exposed at a bottom of the first opening; and
placing a second die in the first opening to stack with the first thinned flip chip die, wherein: the second die comprises a second coupling component embedded therein; and the second coupling component is mirrored to the first coupling component.

2. The method of claim 1 wherein the second die has at least one of an X-direction dimension and a Y-direction dimension essentially the same as the first thinned flip chip die, such that the second die stacked in the first opening is self-aligned with the first thinned flip chip die.

3. The method of claim 2 wherein the second die has both the X-direction dimension and the Y-direction dimension essentially the same as the first thinned flip chip die.

4. The method of claim 1 wherein the first thinned flip chip die and the second die do not have electrical connections.

5. The method of claim 4 wherein the first thinned flip chip die and the second die convey signals to each other by one type of energy from a group consisting of electro-magnetic energy, optical energy, thermal energy, vibration mechanical energy, acoustic wave energy, and X-ray energy.

6. The method of claim 1 wherein the first flip chip die is formed from a silicon-on-insulator (SOI) die, wherein the first device layer of the first flip chip die is a silicon epitaxy layer with integrated electronic components of the SOI die, the first dielectric layer of the first flip chip die is a buried oxide layer of the SOI die, and the first silicon substrate of the first flip chip die is a silicon substrate of the SOI die.

7. The method of claim 1 further comprising applying a second mold compound to encapsulate the second die.

8. The method of claim 7 wherein applying the second mold compound is provided by one of a group consisting of sheet molding, overmolding, compression molding, transfer molding, dam fill encapsulation, and screen print encapsulation.

9. The method of claim 7 wherein the first mold compound is formed from a same material as the second mold compound.

10. The method of claim 7 wherein the first mold compound and the second mold compound are formed from different materials.

11. The method of claim 7 wherein applying the second mold compound with a molding pressure between 250 psi and 1000 psi, wherein the second mold compound has a thermal conductivity greater than 2 W/m·K.

12. The method of claim 7 wherein the second mold compound has a thermal conductivity less than 2 W/m·K.

13. The method of claim 7 further comprising planarizing an upper surface of the second mold compound.

14. The method of claim 1 wherein the second die is formed from a laminate structure with at least one hole extending vertically through the second die, such that air elimination is allowed during placement of the second die in the first opening.

15. The method of claim 1 wherein at least one of an X-direction dimension and a Y-direction dimension of the second die is between 0.5 μm and 10 μm smaller than the first opening, such that air elimination is allowed during placement of the second die in the first opening.

16. The method of claim 1 wherein the second die is one of a group consisting of an integrated passive device (IPD) die, a low temperature cofired ceramic (LTCC) die, a bulk acoustic wave (BAW) filter die, a surface acoustic wave (SAW) filter die, a film bulk acoustic resonator (FBAR) filter die, and an active integrated circuit (IC) die.

17. The method of claim 1 wherein:

the second die comprises a second device layer over the upper surface of the first thinned flip chip die, a second dielectric layer over the second device layer, and a second silicon substrate over the second dielectric layer; and
the second coupling component is embedded in the second device layer.

18. The method of claim 17 wherein:

the first flip chip die is formed from a first SOI die, wherein the first device layer of the first flip chip die is a first silicon epitaxy layer with integrated electronic components of the first SOI die, the first dielectric layer of the first flip chip die is a first buried oxide layer of the first SOI die, and the first silicon substrate of the first flip chip die is a first silicon substrate of the first SOI die; and
the second die is formed from a second SOI die, wherein the second device layer of the second die is a second silicon epitaxy layer with integrated electronic components of the second SOI die, the second dielectric layer of the second die is a second buried oxide layer of the second SOI die, and the second silicon substrate of the second die is a second silicon substrate of the second SOI die.

19. The method of claim 17 further comprising removing substantially the second silicon substrate to release a portion of the first opening and provide a second thinned die with an upper surface, wherein the upper surface of the second thinned die is exposed to the released portion of the first opening.

20. The method of claim 19 further comprising applying a second mold compound to fill the released portion of the first opening and encapsulate the second thinned die.

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Patent History

Patent number: 10325896
Type: Grant
Filed: Sep 5, 2017
Date of Patent: Jun 18, 2019
Patent Publication Number: 20190074271
Assignee: Qorvo US, Inc. (Greensboro, NC)
Inventors: Julio C. Costa (Oak Ridge, NC), George Maxim (Saratoga, CA)
Primary Examiner: Peniel M Gumedzoe
Assistant Examiner: Christopher Johnson
Application Number: 15/695,629

Classifications

Current U.S. Class: And Additional Electrical Device (438/200)
International Classification: H01L 25/065 (20060101); H01L 25/00 (20060101); H01L 21/56 (20060101);