Patents Examined by Christopher Lattin
  • Patent number: 6916727
    Abstract: A structure includes a tensile strained layer disposed over a substrate, the tensile strained layer having a first thickness. A compressed layer is disposed between the tensile strained layer and the substrate, the compressed layer having a second thickness. The first and second thicknesses are selected to define a first carrier mobility in the tensile strained layer and a second carrier mobility in the compressed layer.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: July 12, 2005
    Assignee: Massachusetts Institute of Technology
    Inventors: Christopher W. Leitz, Minjoo L. Lee, Eugene A. Fitzgerald
  • Patent number: 6900859
    Abstract: An in-plane switching mode active matrix liquid crystal display panel includes a substrate structure having a black matrix defining openings and color filter layers disposed in the openings, another substrate structure formed with thin film transistors, pixel electrodes and common electrodes for generating local lateral electric fields and liquid crystal filling the gap between the substrate structures, wherein a highly resistive layer is inserted in the gap between the black matrix and the color filter layers for blocking the color filter layers from electric charges induced in the black matrix due to a potential variation on the pixel electrodes, thereby preventing the visual images from an after image and irregularity in colors.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: May 31, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Kimikazu Matsumoto
  • Patent number: 6812108
    Abstract: A low temperature coefficient resistor(TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: November 2, 2004
    Assignee: Intersil Corporation
    Inventors: Donald Hemmenway, Jose Delgado, John Butler, Anthony Rivoli, Michael D. Church, George V. Rouse, Lawrence G. Pearce, George Bajor
  • Patent number: 6808974
    Abstract: A method is provided for maximizing activation of a gate electrode while preventing source and drain regions from being excessively doped. The gate electrode is partially doped when exposed the source/drain implantation step. Then, the gate electrode is fully doped by the selective implantation step while the source/drain regions are blocked. Separate annealing steps are provided subsequent to the gate doping step and the source and drain implantation step.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: October 26, 2004
    Assignee: International Business Machines Corporation
    Inventors: Heemyong Park, Dominic J. Schepis, Fariborz Assaderaghi
  • Patent number: 6803285
    Abstract: A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile. A conventional two threshold voltage CMOS process is modified to produce four transistor threshold voltages with only one additional masked implant operation. This additional implant raises the threshold voltage of one type of MOSFET while lowering that of the other MOSFET type.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: October 12, 2004
    Assignee: Intel Corporation
    Inventors: Kaizad R. Mistry, Ian R. Post
  • Patent number: 6790736
    Abstract: In accordance with a particular embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer, and an isolation structure is formed adjacent at least a portion of the active region. A gate oxide is formed adjacent at least a portion of the active region. The method also includes forming a polysilicon layer adjacent at least a portion of the gate oxide. At least a portion of the polysilicon layer is removed to form a polysilicon definition structure. The polysilicon definition structure at least substantially surrounds and defines an emitter contact region. The method also includes forming an implant region of the emitter contact region, wherein the implant region is self-aligned.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: September 14, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Xiaoju Wu
  • Patent number: 6787427
    Abstract: A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: September 7, 2004
    Assignee: International Business Machines Corporation
    Inventors: David R. Greenberg, Basanth Jagannathan, Shwu-Jen Jeng, Joseph T. Kocis, Samuel C. Ramac, David M. Rockwell
  • Patent number: 6780795
    Abstract: A temperature drop is be prevented when a plurality of substrates are processed one after another so as to improve a uniformity of process quality between the substrate. An offset temperature value is obtained which is a difference between a temperature of a processing atmosphere at a time immediately before a first one of the substrates is carried into a reaction container and a temperature of the processing atmosphere at a time the temperature has become constant after the substrate are subjected to a heat treatment process one after another. An electric power is supplied to a heater so as to obtain a time period necessary for raising the temperature of a processing atmosphere to a temperature higher than a setting temperature for the heat treatment process by the offset temperature value.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: August 24, 2004
    Assignee: Tokyo Electron Limited
    Inventors: Fujio Suzuki, Hideki Wakai
  • Patent number: 6774060
    Abstract: The method provides a temperature controlled environment for processing semiconductor wafers at elevated temperatures. A hot wall process chamber is used for the process steps. The process chamber includes three zones with independent temperature control capabilities. The method may include rotating the wafers in addition to providing a gas flow velocity gradient above the wafer for improved temperature and processing uniformity results.
    Type: Grant
    Filed: July 7, 2001
    Date of Patent: August 10, 2004
    Assignee: Avansys, LLC.
    Inventor: James J. Mezey, Sr.
  • Patent number: 6764913
    Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor further comprises a first spacer and a second spacer situated on the top surface of the base. The heterojunction bipolar transistor further comprises an intermediate oxide layer situated on the first and second oxide spacers. The heterojunction bipolar transistor further comprises an amorphous layer situated on the intermediate oxide layer. The heterojunction bipolar transistor further comprises an antireflective coating layer on the amorphous layer. The heterojunction bipolar transistor further comprises an emitter window opening situated between the first and second spacers, where the emitter window opening is defined by the top surface of the base, the first and second spacers, the intermediate oxide layer, the amorphous layer, and the antireflective coating layer.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: July 20, 2004
    Assignee: Newport Fab, LLC
    Inventors: Amol M. Kalburge, Kevin Q. Yin, Klaus F. Schuegraf
  • Patent number: 6764923
    Abstract: An SOI wafer includes a substrate, and an insulating intermediate layer and a surface layer successively thereon. At least one laterally limited suicide area is formed in and/or on the surface layer. Then an oxide layer is provided on the surface layer of the SOI wafer and/or on a second silicon wafer, before the two wafers are bonded to each other along the oxide layer. The substrate and the insulating intermediate layer are removed to leave a bonded multi-layered wafer. At least one device component is fabricated in and/or on the surface layer to include the silicide area as a functional element of the device component. Different types of components, e.g. MOS and bipolar transistors, can be fabricated together on the same wafer, and HF characteristics are improved by the low ohmic suicide area(s).
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: July 20, 2004
    Assignee: Atmel Germany GmbH
    Inventors: Harry Dietrich, Volker Dudek, Andreas Schueppen
  • Patent number: 6764908
    Abstract: A method of manufacturing a semiconductor device comprises steps of: (a) providing a semiconductor substrate comprising an upper, tensilely strained lattice semiconductor layer and a lower, unstressed semiconductor layer; and (b) forming at least one MOS transistor on or within the tensilely strained lattice semiconductor layer, wherein the forming comprises a step of regulating the drive current of the at least one MOS transistor by adjusting the thickness of the tensilely strained lattice semiconductor layer. Embodiments include CMOS devices formed in substrates including a strained Si layer lattice-matched to a graded composition Si—Ge layer, wherein the thickness of the strained Si layer of each of the PMOS and NMOS transistors is adjusted to provide each transistor type with maximum drive current.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Daniel Kadosh, Derick J. Wristers, Qi Xiang, Bin Yu
  • Patent number: 6756281
    Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: June 29, 2004
    Assignee: Ziptronix
    Inventor: Paul Enquist
  • Patent number: 6753240
    Abstract: The present invention provides a semiconductor device production method that eliminates the risk of the occurrence of residual resist in the production process, and as a result, allows the electrical characteristics and reliability of the device to be improved. In this semiconductor device production method comprising steps of: subsequently laminating a first resist layer and a second resist layer having desired patterns on a semiconductor substrate, forming a first conductive region on the semiconductor substrate by injecting a first ion into the semiconductor substrate using the first and second resist layers as masks, removing the second resist layer, forming a second conductive region on the semiconductor substrate by injecting a second ion into the semiconductor substrate using the remaining first resist layer as a mask, and removing the first resist layer.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: June 22, 2004
    Assignee: UMC Japan
    Inventor: Yukinobu Hayashida
  • Patent number: 6753196
    Abstract: An electron source 10 has an n-type silicon substrate 1, a drift layer 6 formed on one surface of the substrate 1, and a surface electrode 7 formed on the drift layer 6. A voltage is applied so that the surface electrode 7 becomes positive in polarity relevant to the substrate 1, whereby electrons injected from the substrate 1 into the drift layer 6 drift within the drift layer 6, and are emitted through the surface electrode 7. In a process for manufacturing this electron source 10, when the drift layer 6 is formed, a porous semiconductor layer containing a semiconductor nanocrystal is formed in accordance with anodic oxidation. Then, an insulating film is formed on the surface of each semiconductor nanocrystal. Anodic oxidation is carried out while emitting light that essentially contains a wavelength in a visible light region relevant to the semiconductor layer.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: June 22, 2004
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Takuya Komoda, Tsutomu Ichihara, Koichi Aizawa, Yoshiaki Honda, Yoshifumi Watabe, Takashi Hatai, Toru Baba
  • Patent number: 6740561
    Abstract: There is provided a semiconductor device in which improvement of drive capacity and miniaturization are made. A P-type transistor is composed of a surface channel type transistor so that a channel length is easily reduced. Thus, improvement of drive capacity and miniaturization are promoted. Further, since a gate insulating film is nitrided, reliability of the gate insulating film is improved and passing of boron contained in a p-type polycrystalline silicon gate electrode toward a channel region can be prevented. A step of forming the gate insulating film, a step of nitriding the gate insulating film, a step of performing thermal treatment using an inert gas, a step of forming a gate electrode on the gate insulating film, and a step of introducing a p-type impurity into the gate electrode are performed. Thus, a surface channel P-type transistor and a buried channel N-type transistor are constructed.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: May 25, 2004
    Assignee: Seiko Instruments Inc.
    Inventors: Yoshifumi Yoshida, Jun Osanai
  • Patent number: 6740536
    Abstract: Integrated circuits and methods for producing them are provided. In particular, integrated circuits with shielding elements are provided.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: May 25, 2004
    Assignee: Hewlett-Packard Develpment Corporation, L.P.
    Inventors: Simon Dodd, Frank Randolph Bryant, Paul I. Mikulan
  • Patent number: 6740551
    Abstract: A semiconductor integrated circuit is provided in which a change in timing of a circuit or variation in a driving ability do not occur even if the potential of a support substrate is fixed.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: May 25, 2004
    Assignee: Seiko Instruments Inc.
    Inventors: Yoshifumi Yoshida, Miwa Wake
  • Patent number: 6734073
    Abstract: According to one embodiment of the invention, a method for manufacturing a bipolar junction transistor includes implanting a first base dopant in a semiconductor substrate, forming an epitaxial layer outwardly from the semiconductor substrate, and forming a dielectric layer outwardly from the epitaxial layer. The method also includes etching a first portion of the dielectric layer to form an emitter region, forming an emitter polysilicon layer on the semiconductor substrate, and implanting an emitter dopant in the emitter polysilicon layer. The method further includes etching a portion of the emitter polysilicon layer and a second portion of the dielectric layer to form an emitter polysilicon region having sidewalls, forming nitride regions on the sidewalls, and implanting a second base dopant in the semiconductor substrate. After implanting the second base dopant, an annealing process is performed for the semiconductor substrate to form an emitter and a base.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: May 11, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory E. Howard, Angelo Pinto
  • Patent number: 6734538
    Abstract: A high-density electronics package compromises a chip-stack having a plurality of ICs. Oblong-shaped bumps comprising an electrically-conductive bonding material are disposed along one side of each IC in the chip-stack. The one side of each IC bearing the bumps is aligned with the bump-bearing side of all other ICs in the chip-stack. A portion of each oblong-shaped bump extends beyond the edge of its host IC. This portion of each bump is available to electrically and mechanically connect the chip stack to the next packaging layer, such as a printed circuit board.
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: May 11, 2004
    Assignee: BAE Systems Information & Electronic Systems Integration, Inc.
    Inventor: Keith K. Sturcken