Abstract: In a semiconductor device, at the time of resin sealing, a conductor within the resin is exposed at a surface on which a cooling device is to be mounted. With this configuration, a semiconductor device is capable of determining deterioration in cooling efficiency of the cooling device mounted on the package.

Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

Abstract: A method of fabricating a fluid-ejecting chip for an inkjet printer includes the step of forming CMOS layers on a wafer substrate. Nozzle chambers with ink ejection ports are formed on the wafer substrate. A sacrificial material is deposited on the wafer substrate. A shape memory material is deposited on the sacrificial material at a temperature above a transition temperature of the shape memory material with the shape memory material in a post-actuation shape. Heating circuits are formed on the sacrificial material to be in electrical contact with the CMOS layers and to heat the shape memory material upon receipt of an electrical signal from the CMOS layers to a temperature above the transition temperature. A stressed material is deposited on the sacrificial material. The sacrificial material is removed so that the shape memory material and the stressed material define a plurality of actuators that are operatively arranged with respect to the nozzle chambers.

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract: There is provided a method of producing a bonded wafer comprising bonding a bond wafer and a base wafer via an oxide film or directly and then reducing thickness of the bond wafer, characterized in that the base wafer is a wafer produced by processes comprising slicing a silicon single crystal ingot, and then subjected at least to chamfering, lapping, etching, mirror polishing and cleaning, and the etching process is conducted by subjecting the wafer to alkali etching, and then acid etching, and an etching amount in the alkali etching is larger than an etching amount in the acid etching, and a chamfered part of the base wafer is subjected to a mirror finishing process after the etching, and a bonded wafer produced by the method.

Abstract: The transfer apparatus includes a light source, a transmission type image display device in which a liquid crystal layer is held between two sets of substrates and polarizing plates and a photosensitive recording medium. The light source, the image display device and the photosensitive recording medium are arranged in series along a direction in which light from the light source advances and the image display device and the photosensitive recording medium are arranged in a non-contact state. A display image transmitted from the transmission type image display device is transferred to the photosensitive recording medium. A distance between the image display device and the photosensitive recording medium and a sum total of thicknesses of the substrate and the polarizing plate at least on a side of the photosensitive recording medium in the image display device are set in accordance with a definition of the display image.

Abstract: A benchtop processing system utilizing a wafer receptacle for wafer processing is provided. The wafer receptacle has a plurality of sloped projections capable of receiving a plurality of wafers having different diameter sizes. The wafer receptacle is transported to a processing chamber from a wafer reception module which can also be used as a cooling module. Advantageously, the benchtop processing system and method of the present invention allows for efficient and compact wafer processing.

Abstract: The spaces in chuck grooves 3a and 3b are evacuated to chuck the entire surface of a wafer 1 to the chuck surface of a wafer support table 3 and curve the wafer 1. A wafer 2 is horizontally opposed to the wafer 1, and the center of the wafer 2 is pressed by a press pin 6a. The centers of the two wafers 1 and 2 are contacted, and the contact portion gradually spreads to the vicinity of the periphery of a central portion 3c and takes a substantially circular shape. After that, the chuck by the chuck grooves 3a is stopped. Consequently, the wafer 1 flattens, and the entire surfaces of the wafers 1 and 2 are contacted.

Abstract: A process for fabricating CMOS devices, featuring a channel region comprised with a strained SiGe layer, has been developed. The process features the selective growth of a composite silicon layer on the top surface of N well and P well regions. The composite silicon layer is comprised of a thin, strained SiGe layer sandwiched between selectively grown, undoped silicon layers. The content of Ge in the SiGe layer, between about 20 to 40 weight percent, allows enhanced carrier mobility to exist without creation of silicon defects. A thin silicon dioxide gate insulator is thermally grown from a top portion of the selectively grown silicon layer, located overlying the selectively grown SiGe layer.

Abstract: The invention relates to the protection of devices in a monolithic chip fabricated from an epitaxial wafer, such as a wafer for a Group III-V compound semiconductor or a wafer for a Group IV compound semiconductor. Devices fabricated from Group III-V compound semiconductors offer higher speed and better isolation than comparable devices from silicon semiconductors. Semiconductor devices can be permanently damaged when exposed to an undesired voltage transient such as electrostatic discharge (ESD). However, conventional techniques developed for silicon devices are not compatible with processing techniques for Group III-V compound semiconductors, such as gallium arsenide (GaAs). Embodiments of the invention advantageously include transient voltage protection circuits that are relatively efficiently and reliably manufactured to protect sensitive devices from undesired voltage transients.

Abstract: The disclosure relates to a method of forming a MOS transistor of a semiconductor device and, more particularly, to a method of forming a PMOS transistor of a semiconductor device that minimizes temporary reinforcement and diffusion of dopants for controlling a threshold voltage and dopants for forming a gate electrode due to the selective oxidization of side walls of a conductive layer even though a post heat process is performed at a low temperature by implanting inert ions into the entire semiconductor substrate having a gate pattern including a conductive layer and a metal layer. Thus, the conductive layer and the metal layer are made to have different surface binding capacities to improve the characteristics, reliability and yield of the semiconductor device and to enable high integration of the semiconductor device.

Abstract: The present invention relates to a photoreceiver and method of manufacturing the same. For the purpose of a selective detection of a specific wavelength, if a waveguide type photodetector using a multiple quantum-well layer having a quantum confined stark effect as an optical absorption layer, the wavelength that is absorbed by the stark effect by which the transition energy edge of the optical absorption band is varied depending on the intensity of an electric field applied to the multiple quantum-well layer is varied. Thus, a wavelength selective detection characteristic can be varied simply implemented. The waveguide type photodetector of this structure is integrated on a semi-insulating InP substrate with a heterogeneous bipolar transistor having an n+InP/p+InGaAs/n−InGaAs/n+InGaAsP high-gain amplification characteristic.

Abstract: An electronic device having a component containing a refractory metal such as tungsten is cleaned by using a cleaning solution composed of an acidic solution which does not substantially contain aqueous hydrogen peroxide or an alkaline solution which does not substantially contain aqueous hydrogen peroxide.

Abstract: A semiconductor device is provided having angled dopant implantation and vertical trenches in the silicon on insulator substrate adjacent to the sides of a semiconductor gate. A second dopant implantation is in the exposed the source/drain junctions. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.

Abstract: A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-x Gex layer on the Si substrate, and a strained surface layer on said relaxed Si1-x Gex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-x Gex layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.

Abstract: The invention provides a circuit section of a TFT layer disposed behind an adjacent EL display device, so that a gap defined between pixels at peripheries of the adjacent EL display devices may be 10 &mgr;m. Thus, four EL display devices appear to be unified, forming a large EL display panel. In addition, in the case in which a plurality of EL display devices are arranged in a matrix pattern, pitch between the pixels provided in the pixel section of the TFT array is maintained constant.

Abstract: A hole metal-filling method, applied to hole filling and electroplating a printed circuit board which has been mechanical-drilled with holes. A plurality of holes is drilled in a substrate. The substrate is placed on a platform. A plurality of metal balls is disposed on a surface of the substrate. By vibrating the platform, a part of the metal balls roll into the holes, while the metal balls not rolling into the holes are removed. The substrate is then placed on a press down unit. The metal balls in the holes are pressed to level with surfaces of the substrate. The substrate is directly electroplated for forming a plating layer closely dovetail to the metal balls.

Abstract: A semiconductor package includes a relatively thin substrate epoxy attached to a packaging substrate, such as a lead frame. A relatively thick semiconductor epoxy is attached to a semiconductor. The relatively thin substrate epoxy and the relatively thick semiconductor epoxy are attached to one another forming a stack including the packaging substrate, the relatively thin substrate epoxy, the relatively thick semiconductor epoxy, and the semiconductor. A housing encloses the stack.

Abstract: A firing chamber is formed in a fluid ejection device. The firing chamber is substantially defined by a barrier layer and a thin film stack. The barrier layer is formed over the thin film stack. The thin film stack is on a substrate and defines the bottom of the firing chamber. A sacrificial layer is encapsulated between the thin film stack and the barrier layer. The sacrificial layer is removed.

Abstract: According to a disclosed embodiment, an etch stop layer is fabricated on top of a base. For example, the etch stop layer can be silicon oxide fabricated on top of the base of a silicon-germanium heterojunction bipolar transistor. An amorphous layer is then formed on top of the etch stop layer. For example, the amorphous layer can be formed of a silicon amorphous layer. An opening is then etched in the amorphous layer and the etch stop layer. For example, a dry etch can be used to etch the amorphous layer, and hydrogen fluoride can be used to etch the silicon oxide etch stop layer. The opening is etched with an opening width substantially equal to a critical dimension. For example, control can be achieved over the width of the etching by limiting the thickness of the etch stop layer, and adding silicon oxynitride antireflective coating on the amorphous layer prior to patterning photoresist. The opening with opening width substantially equal to a critical dimension is then filled with a polycrystalline emitter.