Abstract: The disclosure relates to battery powered hand-held data entry terminals wherein a peripheral module may contain an automatically operating full image reader and a wireless communication unit. The reader reads at least one full line of indicia and may comprise a laser bar code scanner or a flash type image reader. Preferably the reader has uniform resolution in orthogonal directions in the field of view so that an area image can be read at any arbitrary angular orientation and re-oriented as a stored digital image to a normalized orientation before decoding. The user interface may lie in a first longitudinally extended layer and the peripheral module may lie in a second longitudinally extended adjoining layer. In normal reading disposition of the automatic reader, the user interface may be close to its normal orientation for user interaction therewith to provide for smooth transitions between reading and user interaction operations.
January 7, 1992
Date of Patent:
April 25, 1995
Steven E. Koenck, Phillip Miller, Arvin D. Danielson, Ronald L. Mahany, Dennis A. Durbin, Keith K. Cargin, George E. Hanson, Darald R. Schultz, Robert G. Geers, Darrell L. Boatwright, William T. Gibbs, Stephen J. Kelly
Abstract: DRAM devices embodying the present invention have longer potential effective values of refresh interval. A self-refresh interval signal may be set in association with its refresh interval to minimize power consumption during the self-refresh operation mode. An inspection method may pick up DRAM devices with efficiency and without deterioration of yields. When self-refresh interval control signal SELFS assumes the logic level "H" to turn P channel type MOS transistor Qp off and N channel type MOS transistor Qn on, the node N14 is brought to ground voltage VSS. The P channel type MOS transistor Qp and the N channel type MOS transistor Qn determine the time constant at which oscillation is generated. The oscillation output is applied to memory cells of the DRAM devices to enable the self-refresh mode of operation.
Abstract: An IC card which operates at either an operation mode or a power save mode, the processing in the operation mode being carried but in accordance with a command signal inputted from a predetermined external equipment, and the power save mode being capable of terminating its operations and returning to the operation mode upon reception of a predetermined release signal, the IC card including an information processing circuit provided in the IC card and a release signal generating circuit for outputting, the release signal to the information processing circuit within the IC circuit at the time when the command signal from the external equipment is received, wherein the information processing circuit executes the process corresponding to the command signal received from the external equipment during the operation mode, and thereafter causes the IC card to move to the power save mode.
Abstract: A backup method for a multiple source optical scanner which alerts an operator when one of the sources has failed. A controller monitors the operation of each source and flags the failed sources. In the case of a scanner having dual full-time channels, the controller removes power from the failed source and disregards the signal from the failed source. In the case of a scanner having non-simultaneously operating sources, the controller switches the remaining source of the scanner to full-time operation. If both sources have failed, power to the failed sources is turned off.
May 17, 1993
Date of Patent:
April 4, 1995
AT&T Global Information Solutions Company
Abstract: A dynamic type semiconductor memory device includes a CBR detecting circuit for detecting a timing condition of /CAS before /RAS, an RS flip-flop which is set depending on an output of the CBR detecting circuit, a pulse generating circuit which is activated in response to an output of the RS flip-flop and generates a one-shot pulse in response to the fall of the external row address strobe signal /RAS, a delay circuit which delays an output of the pulse generating circuit by a predetermined time period, an RS flip-flop which is set by an output of the delay circuit and is reset by the row address strobe signal /RAS, and a NOR circuit which receives outputs of the RS flip-flops, the row address strobe signal /RAS and the column address strobe signal /CAS and generates an internal CAS signal .phi.CAS.
Abstract: A memory cell includes gated diodes as load elements. For example, the memory cell includes a word line, a bit line, an inverted bit line, a ground line, a power line, a first transistor, a second transistor, a third transistor, a fourth transistor, a first gated diode and a second gated diode. The first transistor has a first end connected to the inverted bit line, a second end, and a gate connected to the word line. The second transistor has a first end, a second end connected to the bit line, and a gate connected to the word line. The third transistor has a first end connected to the second end of the first transistor, a second end connected to the ground line, and a gate connected to the first end of the second transistor. The fourth transistor has a first end connected to the first end of the second transistor, a second end connected to the ground line, and a gate connected to the second end of the first transistor.
Abstract: A data compressor generates codewords representative of the location and length of a string match between an input data stream and a CAM array vocabulary table. A data decompressor looks up the codewords for a string match in its vocabulary table. The CAM array is arranged in a serpentine configuration to reduce track layout. A column priority encoder reverses the priority of alternate rows to maintain the logical flow through the CAM array. The CAM array uses a flipflop with a common control circuit to transfer and refresh data through the flipflop.
September 20, 1993
Date of Patent:
February 28, 1995
Eugene B. Nusinov, James A. Pasco-Anderson
Abstract: An area of a semiconductor chip, on which a memory is disposed, is divided into a plurality of memory blocks and redundant memory blocks, each memory block is divided into a plurality of unit arrays of columns for replacing, each redundant memory block is divided into a plurality of unit arrays of redundant columns, a plurality of memory cells are disposed in each unit array of columns for replacing and each unit array of redundant columns, a memory cell group in each unit array of columns for replacing is connected to a word line and a data line, a redundant memory cell group of each unit array of redundant columns is connected to a redundant word line and a redundant data line, a first data selection circuit for controlling data selection with respect to the unit array of redundant columns is disposed in each memory block, a second data selection circuit for controlling data selecting with respect to the unit array group of redundant columns is disposed in each redundant memory block, and a third data selec
Abstract: A semiconductor memory device having a memory cell array (MCA) composed of a plurality of memory cells arranged in a matrix pattern including a plurality of columns, a data register section provided with two first and second registers each having "a"-units of one-bit data register; a control section for selecting two sets of "a"-units of the column from a plurality of the columns for each "a"-cycles in accordance with inputted and read addresses, and for storing the "a" units of data of the selected 2 "a"-units of column in either one of the first and second registers alternately on the basis of a sequence of the read addresses; and a data output section for scanning and outputting data of the 2 "a"-units of the one-bit data register in sequence. Data of column bits more than the number of the registers can be accessed continuously in spite of the minimum register configuration. Further, the head column address can be selected freely.
Abstract: The invention relates to a memory cell for a static associative memory comprising two arrays of transistors, a first array having a data storage function and a second array having a comparison function between the stored data item and a data item applied to the input of the cell, the comparison result being obtained on a selection line S, in which the second array (T1,T2,T3,T4) of transistors is partly formed by the transistors of the first array (T3,T4,T7,T8,T5,T6). The structure of the cell thus has reduced overall dimensions compared with known structures.
December 29, 1992
Date of Patent:
January 31, 1995
France Telecom, Establissement Autonome de Droit Public
Abstract: Address pointers (11, 12, 13, 14) include flip-flop circuits and flip-flop circuits including data through circuits. A control circuit (10) controls the flip-flop circuits such that the data through circuits of unnecessary flip-flop circuits cause data to pass through to prevent the flip-flop circuits from selecting unnecessary memory cells (7). The control circuit (10) generates control signals in selection signal producing means including fuses and the like and a decoding portion. Since the decoding portion decodes a flip-flop selection signal, the number of fuses is reduced. This achieves a semiconductor memory comprising address parts for memory cell selection and redundancy circuits which has a reduced area for provision of the fuses for providing redundancy to the semiconductor memory.
Abstract: The present invention provides a test method of the complexity of 7n to test RAM devices, where n is the number of bits. This method tests all cell stuck-at-1/0 faults, state transition 1-to-0 and 0-to-1 faults, state coupling faults between two cells and data retention faults in random access memories. A standardized testable design memory (STD architecture) is presented which keeps the time required to test a RAM constant irrespective of the memory size. The design is shown through four examples to cover both bit and byte oriented memories. The memory address decoder is implemented in two or more levels. The decoder decoding the most significant addressed is modified by addition of an external control signal line. Memory of the RAM (memory cell array) is partitioned into blocks. The size of these blocks is defined by the last level (least significant address) of the memory address decoder. The design is highly structured and requires a very small amount of extra hardware.
Abstract: The present invention provides a memory device for preventing data circulating on a plural number of linear CCD array from being corrupted, for accessing data at a high speed, and for reducing the device's electric power consumption.A memory device according to this invention downsizes a block of a memory cell by circulating data on a plural number of linear CCD arrays which are for storing data by an electric charge on a cell and keeping analog data, which sets a clock generation means for circulating data on all arrays and another clock generation means for circulating at a high speed only the array loops having necessary data.
Abstract: A polygon mirror is made up of a rotor including a ceramic ring, a yoke and a mirror surface formation member. The yoke and the mirror surface formation member are secured to an outer periphery of the ceramic ring. A radial dynamic pressure bearing is defined by an inner periphery of the ceramic ring and an outer periphery of the fixing shaft. A thrust dynamic pressure bearing is defined by both end surfaces of the ceramic ring and surfaces of a thrust plate fixedly secured to the stator and confronting both end surfaces of the ceramic ring. The ceramic ring, the yoke and the mirror surface formation member are integrated by the material making up the mirror surface formation member during the molding of the member to form the rotor.
Abstract: An associative memory device has associative memory cells arranged in matrix and each implemented by a parallel combination of two electrically erasable and programmable non-volatile memory transistors, and a multi-bit data code stored in a row of associative memory cells allows the two electrically erasable and programmable non-volatile memory transistors of each associative memory cell to selectively enter the programmed state so that a multi-bit key code is checked to see whether or not drain current flows through the electrically erasable and programmable non-volatile memory transistors into a source line.
Abstract: A present invention provides a semiconductor memory device including a capacitor, in which the capacitor comprises an upper electrode, a lower electrode, a ferroelectric capacitor insulating film disposed between the upper electrode and the lower electrode, and a side wall spacer consisting of an insulating material being formed on the side wall of the lower electrode and/or the ferroelectric capacitor insulating film.
Abstract: A memory in which a portion of a digit line is isolated from the remainder of the digit line during a write cycle has improved performance. In the conventional architecture of a memory device, cells are arranged in rows and columns and a sense amplifier is employed for a pair of columns, located between a pair of complementary digit lines. An embodiment of the present invention in this architecture provides improved means for isolating the sense amplifier during a write cycle.
Abstract: In a highly integrated semiconductor memory device, apparatus for setting a stress mode without applying a stress voltage from the exterior is provided. A triggered time point T.sub.S to a stress mode can be set by greatly raising an internal supply voltage when the external supply voltage is raised to a voltage over the stress voltage.
Abstract: A semiconductor memory device according to the present invention includes a memory cell array, internal circuits for reading and writing of data of the memory cell array, a test mode controller, and power-on-reset circuits. The test mode controller sets a test mode of the memory cell array in response to a predetermined pattern of change of logic levels of at least several control signals out of a plurality of control signals for controlling the internal circuits. The power-on-reset circuits set the test mode controller in an initial state over a variable period which is defined based on a timing of change of a logic level of a control signal determining a timing of setting of the test mode out of the at least several control signals, in response to power-on. As a result, it is possible to prevent the semiconductor memory device from erroneously entering the test mode caused by a noise or the like after power-on.
Abstract: A method and apparatus for flash EEPROM refresh is provided in which the control gate of a particular memory cell is read at an elevated control gate voltage (42). It is next determined whether the cell has been programmed (44). If the cell has been programmed, then the next memory cell is read (46). If it is initially determined that the cell has not been programmed (44), then the particular memory cell is read at a lowered control gate voltage (48). It is then finally determined whether the cell has been programmed (50). If it is determined that the cell has not been programmed, then the next cell is read (46). If it is determined that the cell has been programmed (50), then the memory is refreshed (52). After refresh, the next memory cell is read (46).