Abstract: A semiconductor memory device comprises a plurality of memory cells arrayed in matrix and each connected to a word line and a pair of bit lines for supplying a power supply voltage. A bit line load is connected to the pair of bit lines to control a current flowing through a memory cell by the power supply voltage. The semiconductor memory device also comprises a control circuit, connected to the bit line load, for detecting a variation in the power supply voltage, outputting a control signal corresponding to a value of the power supply voltage the variation of which is detected, and controlling activation/inactivation of the bit line load by changing a resistance thereof.
Abstract: A plurality of sub chips are formed on a chip. An input/output buffer region is arranged around the plurality of sub chips. Each sub chip includes a sub chip control circuit region and a plurality of memory cell array blocks. Each memory cell array block includes a memory cell array region, a row decoder and control circuit region, a sense amplifier region and an input/output latch region.
Abstract: A content addressable memory is provided that includes a memory cell and a first plurality of lines connected directly to the gates of access transistors to this memory cell. These access transistors are further connected to a second plurality of lines. The first and second plurality of lines each perform different functions during read, write, and comparison modes. In another embodiment of the present invention, p-channel transistors are used for a match transistor and its associated pass transistors.
Abstract: An improved redundancy architecture is provided for an array of flash EEPROM cells which permit repair of defective columns of memory cells in the array with redundant columns of memory cells on a sector-by-sector basis. The redundancy circuitry includes a plurality of sector-based redundancy blocks (2-8) each having redundant columns of memory cells extending through the plurality of sectors. Sector selection transistors (Q1,Q2) are provided for dividing the redundant columns into different segments, each residing in at least one of the plurality of sectors and for isolating the different segments so as to allow independent use from other segments in the same redundant column in repairing defective columns in the corresponding ones of the plurality of sectors.
August 26, 1993
Date of Patent:
September 20, 1994
Advanced Micro Devices, Inc.
Lee E. Cleveland, Michael A. Van Buskirk, Johnny C. Chen, Chung K. Chang
Abstract: A plurality of memory cells are constituted by a large number of belt-like first conductive members, a ferroelectric thin film formed on the first conductive members, and a large number of belt-like second conductive members formed on the film in a direction perpendicular to the first conductive members. A reading/writing section performs a reading/writing operation with respect to each memory cell after applying a predetermined voltage to at least memory cells other than a target memory cell to cause ferroelectric polarization corresponding to crosstalk components. A two-terminal switch integrally stacked on each of the memory cells serves to reduce dielectric polarization for the elimination of crosstalk caused in each memory cell.
Abstract: A voltage generator for low power applications includes a circuit for generating, controlling and maintaining a high voltage for low power applications in an integrated circuit. The circuit includes separate standby and active circuits for pumping V.sub.CCP of a DRAM under different circumstances. The standby and active circuits operate independently of one another, but may operate simultaneously, to pump charge to V.sub.CCP. The standby circuit is generally a low power circuit activated in response to power up and leakage current conditions to maintain V.sub.CCP. The active circuit is generally a larger circuit and can pump more current. The active circuit is generally responsive to the word lines being driven. Accordingly, the voltage generator can maintain V.sub.CCP while minimizing power consumption in DRAM.
January 11, 1993
Date of Patent:
August 9, 1994
United Memories, Inc., Nippon Steel Semiconductor Corp.
Abstract: A magnetic optical disk player comprises a turn table for turning a magnetic optical disk, a recording head and an erasing head movable along two different radial directions of the turn table respectively, and bias magnets for generating bias magnetic fields distributed along moving areas of the recording and erasing heads and having the directions opposite to each other, wherein the recording head and the erasing head each includes an objective, movable coils coupled with the objective, and drive magnet for generating a drive magnetic field interlinking the movable coils in the same direction as that of the bias magnetic fields. The directions of the bias magnetic fields for erasing and recording heads are opposite to each other. The magnetic fields for generating electromagnetic forces to drive the objective in the erasing head and the recording head are also opposite to each other.
Abstract: A two-transistor flash EPROM cell includes a first floating gate transistor for programming the cell and a second merged transistor for reading the cell. The first transistor, a floating gate transistor, has a drain coupled to the write bit line, a gate coupled to the word line, and a source coupled to the source line. The merged transistor effectively consists of a floating gate transistor in series with a NMOS enhancement transistor. The series NMOS transistor has a voltage threshold of about 1 to 2 volts, thus preventing cell activation caused by overerasure (negative voltage threshold) of the floating gate transistor.
Abstract: A modulated-current offset-type or currentunbalance, offset-type sense amplifier for reading programmable memory cells employs loads identical to each other and a differential input pair of transistors of the differential amplifier are "cross-coupled" with said identical loads to realize a latch structure for storing an extracted data. The circuit utilizes three timing signals for sequentially modifying the configuration of the circuit and defining the following phases: start of a new reading cycle, pre-charging of capacitances associated with bit lines, and equalization of output nodes and line potentials, discrimination phase, reading and storing of the extracted data. Different embodiments employing different reference systems are described.
Abstract: A disk drive apparatus includes a shutter operating pin engageable with a pin receptacle on the shutter of a disk cartridge. The shutter operating pin is carried by a shutter operating arm which is pivotable for causing a transverse shift of the shutter operating pin for shifting the shutter from a closed position, at which a disk is inaccessible, to an open position, at which the disk is accessible. An arm lock mechanism is provided for locking the shutter operating arm at the shutter fully opened position. The arm lock mechanism is provided in the cartridge holder. The cartridge holder is also provided with a cartridge lock mechanism which includes a cartridge lock pin engageable with a lock pin receptacle on the disk cartridge. The cartridge lock mechanism is actuated by means of the shutter operating arm at the shutter fully opened position, to establish locking engagement of the cartridge lock pin with the lock pin receptacle of the disk cartridge.
Abstract: A plurality of transfer bit lines each extend longitudinally across a memory array block. Transfer switch circuits are disposed between the transfer bit lines and a serial register. Transfer switch circuits are disposed between the transfer bit lines and a shared sense amplifier circuit. The transfer switch circuits are controlled by internal transfer signals, respectively. Transfer switch circuits are controlled by internal transfer signals, respectively.
Abstract: A structure and method are provided for accurately compensating for the neighbor effect in reading the state of a memory cell in a virtual ground memory array. When the supply voltage Vcc of the memory array increases above a selected maximum value Vccmax, a programmed memory cell reads as an unprogrammed cell. Due to the neighbor effect, a neighboring cell, which was initially unprogrammed during the programming of the memory cell but was subsequently also programmed, causes Vccmax of the memory cell to be lower in a read cycle than in the previous program/verify cycle, resulting in discarding the memory device. In accordance with the present invention, circuitry activated during the read cycle compensates for the neighbor effect by including an unprogrammed replica EPROM transistor identical to the memory cell in parallel with the neighbor of the memory cell being read.
Abstract: There is disclosed a semiconductor memory device comprising memory cells (M11 to Mnn) for storing binary data, and first reference cells (DM11 to Dm1) and second reference cells (DM12 to DMm2) corresponding to respective two storage states of the memory cell, to make comparisons between the storage state of the memory cell and the storage states of the both reference cells at first and second sense amplifiers (1, 2) to compare outputs from the both sense amplifiers at the third sense amplifier (3) to thereby detect storage data of the memory cell. Thus, there can be provided a high speed memory device which has a less number of memory cells and of a high integration structure, and which has a little possibility of an erroneous operation in reading.
August 24, 1993
Date of Patent:
June 14, 1994
Kabushiki Kaisha Toshiba
Hiroshi Iwahashi, Hiroto Nakai, Kazuhisa Kanazawa, Isao Sato
Abstract: A magneto-optical recording device for radiating a laser beam according to recording information onto a magneto-optical recording medium having an easy axis of magnetization in a direction perpendicular to a film face of the recording medium itself to form a reversed domain and record information, which forms a reversed domain by radiating a laser beam and moves the position of the reversed domain to record information. In an embodiment of the present invention, it becomes possible to over-write new information without erasing beforehand information already recorded by only controlling the intensity, pulse width, radiation position and radiation time of the laser beam without providing a special bias magnetic field for reversing the magnetic field.
Abstract: An improved dynamic random access memory (DRAM) having self refresh mode is provided. After initiation of a self refresh term Ts, and in a first term Tc1 and a last term Tc2, a concentrated refresh using a refresh clock signal /REFS having a short period Pc is carried out for all rows in a memory cell array. During the remaining term, a normal self refresh operation using a signal /REFS having a long period Ps is carried out. Stored data is maintained effectively because the refresh interval of each row in a memory cell array is prevented from exceeding significantly a predetermined time length Ps.
Abstract: A semiconductor device having a field effect transistor in which a silicon carbide layer and a ferroelectric film are stacked in this order on the surface of a silicon substrate and the ferroelectric film is used as a gate insulation film. A channel between a source and a drain is formed in the silicon carbide layer. A metal or oxygen contained in a ferroelectric material is difficult to diffuse in silicon carbide. Therefore, the silicon carbide layer is not eroded in the case of heat treatment after forming the ferroelectric film. Therefore, good FET characteristics is obtained.
Abstract: A color data transferring circuit, a color data storing circuit, and a block selecting circuit 1020 are provided separately from an input/output buffer circuit, in order to transmit data stored in a color register to a memory cell block. In a block write mode, data applied to a data input/output terminal is stored in the color data storing circuit through color register and the color data transferring circuit. One block selecting gate is selected in response to a block selecting signal from a block decoder, and data stored in each storage element in the color data storing circuit is transmitted to a corresponding memory cell block. Input/output buffer circuit performs normal data writing only through a sense amplifier +I/O block. A semiconductor memory device capable of easily extending the number of bits of block write with a simple circuit configuration is implemented.
Abstract: A static random access memory (30), resistant to soft error from alpha particle emissions has a high density array of memory cells (44) coupled to word lines (73 and 74) and bit line pairs (68), and operates at low power supply voltages (for example, 3.3 volts). A charging circuit (55) boosts a supply voltage to the memory array above the power supply voltage. The charging circuit (55) includes an oscillator (57), a charge pump (56), and a voltage regulator (58). The boosted supply voltage reduces the effect of an alpha particle hitting the memory array (44) at low power supply voltages. Providing a boosted supply voltage to the memory array (44) improves soft error resistance without adding capacitance to each memory cell (52 and 54).
Abstract: Disclosed is a refresh address test circuit of a semiconductor memory device having a self-refresh function using a plurality of internal refresh address signals, comprising a plurality of the address test paths, each including a first sub-path which receives an initial logic level of one bit of an initial refresh address and a second sub-path of which receives successive corresponding bits of said refresh address, a plurality of comparators, each connected to the first sub-path and the second sub-path, a test output circuit receives the output signals generated from the plurality of comparators to determine whether a complete cycle of refresh addresses have been generated.
Abstract: A row of defective memory cells is replaceable with a row of redundant memory cells for rescuing a random access memory device, and a programming circuit discriminates the address assigned to the row of defective memory cells for allowing a redundant row address decoder circuit to drive a redundant word line coupled with the row of redundant memory cells, wherein the programming circuit checks predetermined row address bits selected from all the row address bits to see whether or not the rows of defective memory cells are accessed for producing an output signal, and the redundant row address decoder circuit identifies one of the redundant word lines on the basis of the other row address bit so that the programming circuit is shared between the redundant word lines, thereby decreasing the real estate for the programming circuit.